JP2001189090A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate malfunction at the time of read-out caused by a coupling noise from a non-selection bit line being adjacent to a selected bit line without increasing chip area and an operation cycle time with respect to a semiconductor memory. SOLUTION: This device is provided with bit line selection transistors 6, 7, 8, 9 coupling a bit line selected by receiving a bit line selecting signal to a bus bit line, and bit line pre-charge transistors 2, 3, 4, 5 receiving a pre-charge signal NPCG, driving all bit lines to a logic state of a bit line selecting signal, charging a selection bit line to a high level, and discharging a non-selection bit line to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory device for performing a read operation by precharging a bit line.

[0002]

2. Description of the Related Art As a conventionally used semiconductor memory device, for example, in the case of a mask ROM, data reading is performed by precharging all bit lines and then determining a memory determined by a selected word line and bit lines. Depending on the data in the cell, the bit line potential is determined by holding the state of the bit line at the time of precharging or by pulling it down to a low level via a memory cell transistor, and the read circuit determines this. Have been.

FIG. 5 shows a circuit configuration diagram of a memory cell in a conventional mask ROM. The memory cell transistor of the mask ROM is usually composed of one N-channel MOS transistor, the source is connected to the ground level, the gate is connected to the word line, and the drain is connected to or connected to the bit line. The data "1" and "0" are determined depending on whether the data is present or not, and this connection is performed in a diffusion process.

There is a parasitic capacitance between the drain of the MOS transistor and the substrate, which is determined by the area and the perimeter of the drain portion. The capacitance per substrate of one bit line of the mask ROM is written to the bit line. It changes according to the ratio of the number of data “0” and “1” of the memory cell that is present. In addition, a parasitic capacitance exists between the drain and the gate. Therefore, the more the drains of the memory cells are connected to the bit line, the greater the capacitance between the bit line and the substrate. That is,
When the capacity of the semiconductor memory device is increased, the capacity between the bit line and the substrate is increased.

Here, the capacitance between the wiring layer and the substrate per unit length of the bit line is C _metal , the wiring length of the bit line is L, the capacitance between the drain and the substrate per memory cell is C _memo , Assuming that the capacitance between the drain and the gate per cell is C _gate , and the number of memory cells connected to one bit line is M, the capacitance C _b between the bit line and one substrate per wiring is It is represented by the following equation. (Equation 1) C _b = C _metal × L + M × (C _memo + C _gate ) (1) Further, in order to achieve high integration of the semiconductor memory device, it is necessary to reduce the wiring layout area by miniaturizing the wiring pattern. As a result, the distance between adjacent bit lines becomes shorter, and the coupling capacitance between the bit lines also increases.

Here, _assuming that the coupling capacitance per unit length between the bit line wirings is C _c and the bit line wiring length is L, the coupling capacitance C _s between the bit lines running in parallel on both sides is Cs. Is represented by the following equation. (Equation 2) C _s = 2 × C _c × L ... (2) For example, in the case of a 0.18 μm process, the above C _metal
And C _c have substantially the same value. Here, when there is a bit line to which no memory cell is connected, that is, when M = 0, from the above equations (1) and (2), ) C _b = 2C _s (3), and the bit line-to-substrate capacitance C _b per wire
Is twice the coupling capacitance C _s between bit lines running parallel on both sides.

FIG. 6 is a circuit diagram of a first conventional mask ROM. In FIG. 6, reference numeral 1 denotes a memory cell array of a mask ROM, which includes N word lines WL1 to WLN.
Then, each memory cell is accessed by the four bit lines BIT1 to BIT4. 2, 3, 4, and 5 are bit line precharge transistors, each of which is formed of an N-channel MOS transistor. A precharge signal NPCG which becomes high level (normally VDD) at the time of precharge is input to a gate of the transistor. The drain is the power supply voltage VDD
The source is connected to the corresponding bit line 1 (BIT1), bit line 2 (BIT2), bit line 3 (BIT3), and bit line 4 (BIT4).

Further, BIT1, BIT2, BIT3,
BIT4 is a BIT1 selection line CA1, BIT2
The select lines CA2, BIT3, CA3 and BIT4 select lines CA4 have four bit line select transistors 6, each comprising an N-channel MOS transistor connected to each gate.
It is connected to a common bus bit line (BBIT) via 7, 8, and 9.

The selection lines CA1 to CA4 of the four bit lines
, Only one selected is high level (normal VDD)
And the other three are applied with a signal that is at a low level (normally 0 V).

A sense amplifier 10 receives a read signal of a selected bit line applied to a bus bit line, amplifies the read signal to a predetermined level necessary for determining a logical level, and outputs the amplified signal as read data S _OUT. I do. Reference numeral 11 denotes a bus bit line precharge transistor, the gate of which is supplied with a precharge signal NPCG via an inverter 13 to precharge the bus bit line BBIT. Reference numeral 12 denotes a transistor constituting a high-level hold circuit for the bus bit line. The gate of the transistor 12 is connected to the output of the sense amplifier 10 to feed back the input of the sense amplifier 10.

FIG. 7 shows the internal structure of the memory cell array 1 of FIG. 6, and includes N word lines WL1 to WL.
N, four bit lines BIT1 to BIT4, and N × 4
It is composed of a number of memory cell transistors.

In FIG. 7, a word line 1 (WL1) is connected to each gate, and the source is grounded.
Four memory cell transistors M (1,1), M (1,2), M (1,3), M
In (1, 4), the memory cell transistor M (1,
The drain of 2) is connected to the bit line 2 (BIT2), but the other memory cell transistors M (1,1), M
The drains of (1,3) and M (1,4) are not connected to the corresponding bit lines BIT1, BIT3, BIT4.

The word line N (WLN) is connected to each gate from the remaining word line 2 (WL2), and the memory cell transistors M (K, 1), M (K,
2), M (K, 3), M (K, 4) (where K = 2
N), the memory cell transistor M (K, 1),
The drains of M (K, 3) and M (K, 4) are respectively connected to bit line 1 (BIT1) and bit line 3 (BIT1).
3) Although connected to the bit line 4 (BIT4), the drain of the memory cell transistor M (K, 2) is not connected to any bit line.

That is, the bit line 2 (BIT2)
Only the drain of the memory cell transistor M (1,2) whose word line 1 (WL1) is connected to the gate is connected, and the remaining bit lines BIT1, BIT3, BIT4 are connected to the other than the word line 2 (WL2). This means that the drains of the N-1 memory cell transistors whose N-1 word lines are connected to the gates are connected.

[0015]

FIG. 8 is a simulation waveform diagram showing an operation state of the first conventional mask ROM shown in FIG. In this description, the word line 2 (WL
The following description focuses on the operation waveforms of bit line 1 (BIT1), bit line 2 (BIT2), and bit line 3 (BIT3) when 2) and bit line 2 (BIT2) are selected.

First, the precharge operation during the period when the precharge signal NPCG shown in FIG.

When the precharge signal NPCG is at a high level, four bit lines BIT1, BIT2, BIT
3 and BIT4 are all set to high level (V) by the bit line precharge transistors 2, 3, 4, and 5, respectively.
0). Usually, to speed up reading,
Bit line precharge transistors 2, 3, 4, 5 are N
V0 is a potential lower than the power supply voltage VDD by the threshold voltage _Vth of the N-channel MOS transistor. (Equation 4) V0 = VDD−V _th (4) Of course, the bit line precharge transistors 2, 3,
4 and 5 may be constituted by P-channel MOS transistors. However, in the case of a pre-charge type memory read such as a mask ROM, the time required to pull down the bit lines via the memory cells in the read after the pre-charge is a read time. When V0 is constituted by P-channel MOS transistors, V0 has a higher VDD and the precharge potential of the bit line, and the read time is longer than that in the case of N-channel MOS transistors. For this reason, the precharge transistor of the bit line is formed of an N-channel MOS transistor, and the precharge potential is set to a potential lower than VDD.

In the precharge period, all word lines are at 0V. This is because if the word line is open during precharge, the precharge transistor 2,
The charging current from 3, 4, 5 is connected to GND via the memory cell.
This causes unnecessary current consumption to increase.

Next, the bit line selection lines CA1, CA2, C
One to be selected from A3 and CA4 is determined in the precharge period. Here, a high-level signal is applied to CA2 (FIG. 8B), and the other CA1, CA3, C
A4 is supplied with a low-level signal, and bit line 2
(BIT2) is selected.

The bus bit line (BBIT) is precharged by a bus bit line precharge circuit 11 having a gate input of an inverted signal of the precharge signal NPCG. The precharge of the bus bit line is performed by the sense amplifier 10
In order to allow a margin between the threshold voltage V _SW and the threshold voltage V _SW , the bus bit line is precharged to VDD (see FIG. 8).
(E)). During this period, since the bus bit line is at VDD, the output S _OUT of the sense amplifier 10 is at low level.

Next, the precharge signal NPCG becomes low level, the precharge is completed, and a read period starts. Upon completion of the precharge, the word line WL2 rises. In the case of the configuration shown in FIG. 7, when the word line WL2 rises, all the memory cells M (2, 1), M (2, 2), M (2, 3), M connected to the word line WL2.
(2, 4) is selected.

At this time, since the memory cell M (2, 2) is not connected to the bit line 2 (BIT2), no discharge occurs, and the potential of the bit line 2 should be maintained at the precharge potential. , BIT2 and the adjacent bit line 1
B that falls to low level due to the coupling capacitance between (BIT1) and bit line 3 (BIT3).
BIT2 is lowered to a low level under the influence of IT1 and BIT3.

This BIT2 and its adjacent BIT1, BI
The coupling capacitance C _s between T3, the potential V1 of the potential of BIT2 reaches after reduction, when the pair foundation capacitance between BIT2 and C _b, are expressed by the following equation. In equation _{(5) V1 = V0 × C b} / (C s + C b) ... (5) deep submicron process, the line width and between lines distance of the aluminum wiring constituting the bit line has become both small, 0 In the process at the level of .18 μm, C _s = 2C _b from the above equation (3). As a result, equation (5)
Therefore, the bit line 2 becomes V1 = V0 / 3 (6) due to the influence of coupling, and the bit line 2 may drop to 1/3 of the high level.

Therefore, the bit line selection transistor 6,
Electric charges are supplied from the bus bit line (BBIT) connected to the sense amplifier 10 via 7, 8, and 9, but the potential of the bus bit line itself drops to V1 and is connected to the bus bit line. If the determination threshold value V _SW of the sense amplifier 10 is higher than this, it is determined that the output is at the low level although the output at the original high level is expected. Usually, a high level hold circuit 1 is connected to this bus bit line.
2 is normally provided, but this hold capability is originally a protection circuit for preventing a small leak current from occurring and malfunctioning, and is configured to cope with such a dynamic decrease in potential. Not.

This is because the high level hold circuit 12
This is because, if the capability of this is increased to prevent a dynamic potential drop, the low-level read speed will be slowed down. Further, the high-level hold circuit 12 is configured to be unable to recover once the bit line potential once drops to a low level.

Therefore, if the potential of the bus signal line drops due to the influence of the coupling due to the discharge of the bit lines on both sides and drops even slightly below the low-level threshold V _{SW of the} sense amplifier 10, a read malfunction occurs.

Further, as described above, the bit line precharge transistor is formed of a P-channel MOS transistor, and the precharge is raised to VDD, thereby increasing the potential of the bit line 2 affected by the coupling capacitance. However, reading of data “1” is delayed.

As a second conventional example, Japanese Patent Application Laid-Open No.
Japanese Patent Application Laid-Open No. 85698 proposes a method of precharging only selected bit lines for the purpose of reducing charging current, as shown in FIG.

However, since uncharged bit lines are not precharged, but remain charged in the previous cycle, it is impossible to prevent malfunction due to coupling capacitance during reading.

That is, in the memory cell having the configuration shown in FIG. 7, when the memory cells are selected in the order of M (1,1) → M (1,3) → M (2,2), the charges of BIT1 and BIT3 are Since the BIT1 and BIT3 are discharged through the memory cell transistors M (2,1) and M (2,3) when M (2,2) is read, the first conventional method is used. A malfunction similar to the example occurs.

FIG. 10 is a circuit diagram showing a modification in which a circuit dedicated to bit line discharge is added to the second conventional example shown in FIG. The operation of this circuit will now be described.

The bit lines are selectively precharged by bit line selection lines CA1 to CA4 and precharge transistors 2 to 5. By adding N-channel transistors 10 to 13 whose sources are connected to the reference potential of GND and whose drains are connected to BIT1 to BIT4, the charges charged in the bit lines are discharged.

FIG. 11 is an operation timing chart for each cycle period of the first conventional example, and FIG. 12 is an operation timing chart for each cycle period of the second conventional example. In any case, one cycle is the sum of the precharge period and the read period.

FIG. 13 is an operation timing chart for each cycle period of a modification example in which a circuit dedicated to bit line discharge is added to the second conventional example shown in FIG. In the method shown in FIG. 10, a separate cycle dedicated to discharging is required as shown in FIG.

When the capacity of the transistor constituting the dedicated circuit for bit line discharge is set to be the same as the capacity of the transistor for precharge, the discharge time is required as long as the precharge time. If the discharge time is to be 1 / T of the precharge time, the capacity of the discharge transistor must be T times the capacity of the precharge transistor.
It is necessary to increase the number of cycles required for discharging or increase the area of the discharging transistor.

Accordingly, an object of the present invention is to provide a semiconductor memory device which eliminates a malfunction at the time of reading due to coupling noise from an unselected bit line adjacent to a selected bit line.

[0037]

In order to achieve the above object, a first semiconductor memory device of the present invention precharges bit lines of a plurality of memory cells to a first potential, and sets each of the bit lines to a first potential. In response to the bit line selection signal corresponding to
A semiconductor memory device for reading information stored in the plurality of memory cells through the bit line, wherein at least immediately before reading information of a bit line selected by the bit selection signal in a current cycle period, And means for fixing the non-selected bit lines precharged in the cycle period to the second potential in the current cycle period.

[0038] In the first semiconductor memory device, it is preferable that the first potential is near a power supply voltage and the second potential is near a ground potential.

In order to achieve the above object, the second aspect of the present invention
The semiconductor memory device of the present invention precharges bit lines of a plurality of memory cells in response to a precharge signal, and responds to a bit line selection signal corresponding to each of the bit lines, through the bit lines. A semiconductor memory device for reading information stored in a memory cell of the memory cell, wherein the semiconductor memory device is connected between a bit selection line to which the bit line selection signal is supplied and the corresponding bit line, and responds to the precharge signal. Means for driving the bit line to a potential corresponding to the logic state of the corresponding bit line selection signal.

In order to achieve the above object, a third semiconductor memory device of the present invention precharges bit lines of a plurality of memory cells in response to a precharge signal and responds to each of the bit lines. A semiconductor memory device that reads information stored in the plurality of memory cells via the bit line in response to the bit line selection signal,
The bit line select signal is connected between a bit select line to which the bit line select signal is supplied and the corresponding bit line, and in response to the precharge signal, charges the selected bit line by the bit line select signal and And a charge / discharge circuit for discharging a non-selected bit line.

Further, in order to achieve the above object, the fourth semiconductor memory device of the present invention precharges bit lines of a plurality of memory cells in response to a precharge signal,
A semiconductor memory device which reads information stored in the plurality of memory cells via the bit lines in response to a bit line selection signal corresponding to each of the bit lines, wherein a gate is provided for each of the bit lines. A first N-channel MOS transistor connected to a bit selection line to which a line selection signal is supplied, a drain connected to the corresponding bit line, and a source commonly connected to a bus bit line; Are commonly supplied, a drain is connected to the corresponding bit line, and a source is connected to the second N-channel MOS transistor connected to the bit selection line to which the corresponding bit selection signal is supplied; An output unit connected to a bus bit line for outputting information of the selected bit line via the first N-channel MOS transistor; The second NMOS transistor charges a selected bit line according to the bit line selection signal to a high level and discharges an unselected bit line to a low level in response to the precharge signal. I do.

According to the first to fourth semiconductor memory devices, only the selected bit line is charged to the high level at the time of precharge in accordance with the bit line selection signal, and simultaneously the unselected bit lines are set to the low level. (GND), the unselected bit line adjacent to the selected bit line to be held at the high level can be fixed at the low level, the coupling noise from the unselected bit line can be prevented, and the read time can be reduced. Can be eliminated.

Further, by performing both precharging and discharging for the bit line in the same period and with the same circuit, a discharging period is provided after the conventional reading period to sacrifice the operation cycle time of the memory, The disadvantage of providing a transistor and increasing the chip area is eliminated.

Furthermore, by using an N-channel MOS transistor as the bit line precharge transistor, the precharge potential can be reduced, thereby shortening the memory read time and enabling high-speed access.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a mask R according to an embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of an OM. In FIG. 1, reference numeral 1 denotes N word lines WL1 to WLN and four bit lines BIT1 to BIT1.
This is a memory cell array of a mask ROM composed of IT4, and has the same configuration as that shown in FIG. 7 in the description of the conventional example. 2, 3, 4, and 5 are bit line precharge transistors (fixing means, driving means, charging / discharging circuit, second N-channel MOS transistor),
The gate of the transistor is supplied with a precharge signal NPCG which is at a high level (normally VDD) at the time of precharging and at a low level at the time of reading, and its drain is a bit line 1 (BIT1) and a bit line 2 ( BIT2), bit line 3 (BIT3) and bit line 4 (BIT4), the sources of which are respectively connected to bit line selection lines C to which corresponding bit line selection signals are supplied.
A1, CA2, CA3, and CA4 are connected.

Reference numerals 6, 7, 8, and 9 denote bit selection transistors (first N-channel MOS transistors), which are N-channel MOS transistors, and whose gates are supplied with corresponding bit line selection signals. Connected to the bit line selection lines CA1, CA2, CA3, and CA4, the drains of which are connected to the bit lines BIT1, B1, respectively.
It is connected to IT2, BIT3, BIT4, and its source is connected to a common bus bit line (BBIT).

The select lines CA1 to CA4 of the four bit lines
, Only one selected is high level (normal VDD)
And the other three not selected are low level (usually 0
V) is applied.

A sense amplifier 10 receives a read signal of a selected bit line applied to a bus bit line, amplifies the read signal to a predetermined level required for determining a logical level, and outputs it as read data S _OUT. I do. Reference numeral 11 denotes a bus bit line precharge transistor, the gate of which is supplied with a precharge signal NPCG via an inverter 13 to precharge the bus bit line BBIT. Reference numeral 12 denotes a transistor constituting a high-level hold circuit for the bus bit line. The gate of the transistor 12 is connected to the output of the sense amplifier 10 to feed back the input of the sense amplifier 10.

FIG. 2 is a simulation waveform diagram showing an operation state of the mask ROM according to the embodiment of the present invention shown in FIG. In this description, when the word line 2 (WL2) and the bit line 2 (BIT2) are selected, the bit line 1 (B
IT1), bit line 2 (BIT2), bit line 3 (BI
A description will be given focusing on the operation waveform at T3).

First, the precharge operation during the period when the precharge signal NPCG shown in FIG. 2A is at a high level will be described.

The four bit lines BIT1, BIT2, BI
T3 and BIT4 correspond to bit line precharge transistors 2, 3, 4, 5 and bit line select lines CA1, CA2, CA, respectively.
3 and CA4, one is selectively high level (V
0: the first potential) and the other three are discharged to 0 V (the second potential).

Normally, in order to speed up reading, the bit line precharge transistors 2, 3, 4, and 5 are composed of N-channel MOS transistors, and V0 is a threshold voltage V _{th of the} N-channel MOS transistor from the power supply voltage VDD. And V0 = VDD− _Vth .

In the precharge period, all word lines WL1 to WLN are at 0V. This is because if the word line is open at the time of precharge, the charging current from the precharge transistors 2, 3, 4, and 5 flows to GND via the memory cell, which leads to an unnecessary increase in current consumption.

The bit line selection lines CA1, CA2, CA3,
By CA4, one bit line to be selected is determined in the precharge period. Here, CA2 is at a high level (FIG. 2B), the other CA1, CA3, and CA4 are at a low level, and the bit line BIT2 is selected. Therefore, only the bit line BIT2 is precharged, and the other 3
The book holds 0V.

If bit line BI
Even if the charged state of each bit line other than T2 is maintained, it is discharged via the bit line precharge transistor during the precharge period. This discharge is at most limited to one bit line precharged last time.

The bus bit line BBIT is precharged by a bus bit line precharge circuit 11 having a gate input of an inverted signal of the precharge signal NPCG (FIG. 2 (e)). The pre-charging of the bus bit line has a margin between it and the determination threshold value V _SW of the sense amplifier 10,
The bus bit lines are precharged to VDD for this purpose (FIG. 2E). During this period, since the bus bit line is at VDD, the output S _OUT of the sense amplifier 10 is at low level.

Next, the precharge signal NPCG becomes low level, and the precharge is completed to start a readout period. Upon completion of the precharge, the word line WL2 rises (FIG. 2C). When the word line WL2 rises, all the memory cells M connected to the word line WL2
(2,1), M (2,2), M (2,3), M (2,
4) is selected.

At this time, since the memory cell M (2, 2) is not connected to the bit line BIT2, no discharge occurs, and the potential of the bit line BIT2 is maintained at the precharge potential. Since the bit lines BIT1 and BIT3 are discharged during the precharge period, the precharge potential does not decrease due to the coupling capacitance between the bit lines BIT1 and BIT3 and the bit line BIT2, and the data "0" on the bit line BIT2 is not generated. Accurate reading of (memory cell not connected) becomes possible.

FIG. 3 shows a mask R according to an embodiment of the present invention.
FIG. 7 is an operation timing chart for each OM cycle period. FIG.
As can be understood from the above description, in the method of the present embodiment, the non-selected bit lines are simultaneously discharged during the period in which the selected bit lines are precharged, so that the cycle as in the second conventional example shown in FIG. No increase in time occurs.

In the embodiment of the present invention, the mask RO
Although M has been described as an example, in order to eliminate the charging / discharging current of the non-selected bit lines during the precharge period, the present invention employs a multi-port type static RAM having a configuration as shown in FIG. In this case, the current consumption of the circuit can be reduced.

[0062]

As described above, according to the present invention,
Malfunction at the time of reading due to coupling noise from an unselected bit line adjacent to the selected bit line without providing a dedicated transistor for discharge and increasing the chip area, or providing a discharge period after the reading period and extending the operation cycle period. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a mask ROM according to an embodiment of the present invention.

FIG. 2 is a simulation waveform diagram showing an operation state of the mask ROM according to the embodiment of the present invention.

FIG. 3 is an operation timing chart for each cycle period of the mask ROM according to the embodiment of the present invention;

FIG. 4 is a circuit configuration diagram of a multiport static RAM memory cell.

FIG. 5 is a configuration diagram of a mask ROM memory cell.

FIG. 6 is a circuit configuration diagram of a mask ROM according to a first conventional example.

FIG. 7 is a circuit diagram of a mask ROM memory cell array.

FIG. 8 is a simulation waveform diagram showing an operation state of the mask ROM according to the first conventional example.

FIG. 9 is a circuit diagram of a mask ROM according to a second conventional example.

FIG. 10 is a circuit configuration diagram of a mask ROM modified from the second conventional example.

FIG. 11 is an operation timing chart for each cycle period of the mask ROM according to the first conventional example.

FIG. 12 is an operation timing chart for each cycle period of the mask ROM according to the second conventional example.

FIG. 13 is an operation timing chart for each cycle period of a mask ROM modified from the second conventional example.

[Explanation of symbols]

1 Memory cell array 2, 3, 4, 5 Bit line precharge transistor (second N-channel MOS transistor) 6, 7, 8, 9 Bit line select transistor (first N
Channel MOS transistor) 10 sense amplifier (output unit) 11 bus bit line precharge circuit 12 high-level hold circuit (output unit)

Claims (5)

[Claims] 1. A method for precharging bit lines of a plurality of memory cells to a first potential and responding to a bit line selection signal corresponding to each of the bit lines, the plurality of memory cells via the bit lines. In the semiconductor memory device for reading the information stored in the bit line, before reading the information of the bit line selected by the bit selection signal in the current cycle period, at least the non-selected bit line precharged in the immediately preceding cycle period is read. A semiconductor memory device comprising: means for fixing the potential to a second potential in a current cycle period. 2. The method according to claim 1, wherein the first potential is near a power supply voltage,
2. The semiconductor memory device according to claim 1, wherein said second potential is near a ground potential. 3. A method for precharging bit lines of a plurality of memory cells in response to a precharge signal, and in response to a bit line selection signal corresponding to each of the bit lines, via the bit lines. In a semiconductor memory device for reading information stored in a memory cell, the semiconductor memory device is connected between a bit selection line to which the bit line selection signal is supplied and the corresponding bit line, and in response to the precharge signal, A semiconductor memory device comprising means for driving a bit line to a logic state of the corresponding bit line selection signal. 4. A method of precharging bit lines of a plurality of memory cells in response to a precharge signal, and responding to a bit line selection signal corresponding to each of the bit lines, via the bit lines. In a semiconductor memory device for reading information stored in a memory cell, the semiconductor memory device is connected between a bit selection line to which the bit line selection signal is supplied and the corresponding bit line, and in response to the precharge signal, A semiconductor memory device comprising a charge / discharge circuit for charging a selected bit line by a bit line selection signal and discharging a non-selected bit line. 5. A method of precharging bit lines of a plurality of memory cells in response to a precharge signal, and responding to a bit line selection signal corresponding to each of the bit lines, via the bit lines. In a semiconductor memory device for reading information stored in a memory cell, a corresponding bit line selection signal is supplied to a gate,
A first N-channel MOS having a drain connected to the corresponding bit line and a source commonly connected to a bus bit line;
A transistor, a second N-channel MOS transistor to which the gate is supplied with the precharge signal in common, a drain connected to the corresponding bit line, and a source supplied with the corresponding bit selection signal; An output unit that is connected to the bus bit line and outputs information on the selected bit line via the first N-channel MOS transistor; and wherein the second N-channel MOS transistor responds to the precharge signal. In response, the semiconductor memory device charges a selected bit line according to the bit line selection signal to a high level and discharges an unselected bit line to a low level.