JP2001185664A - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JP2001185664A JP2001185664A JP36825099A JP36825099A JP2001185664A JP 2001185664 A JP2001185664 A JP 2001185664A JP 36825099 A JP36825099 A JP 36825099A JP 36825099 A JP36825099 A JP 36825099A JP 2001185664 A JP2001185664 A JP 2001185664A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- circuit board
- resist layer
- solder resist
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パワートランジス
タモジュール用基板等に好適なセラミックス回路基板に
係り、特にセラミックス基板上に金属回路板を接合して
構成される回路基板において、その金属回路板上に半導
体ペレットをハンダにより実装する場合にハンダの流動
による不都合を防止したセラミックス名回路基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board suitable for a substrate for a power transistor module and the like, and more particularly to a circuit board formed by bonding a metal circuit board on a ceramic substrate. The present invention relates to a ceramic circuit board which prevents inconvenience due to solder flow when a semiconductor pellet is mounted by soldering.
【０００２】[0002]
【従来の技術】近年、パワートランジスターモジュール
用基板などの回路基板として、セラミックス基板上に銅
板やアルミニウム板、クラッド材等の金属板を接合させ
たものが用いられている。2. Description of the Related Art In recent years, as a circuit substrate such as a substrate for a power transistor module, a substrate obtained by bonding a metal plate such as a copper plate, an aluminum plate, or a clad material to a ceramic substrate has been used.
【０００３】このようなセラミックス基板の製造には種
々の方法が知られており、例えばＤＢＣ法（ダイレクト
・ボンディング・カッパー法）、ＤＢＡ法（ダイレクト
・ボンド・アルミニウム法）、活性金属法等がある。Ｄ
ＢＣ法は、所定形状に打ち抜いた銅回路基板をセラミッ
クス基板上に接触配置させて加熱し、接合界面にＣｕ−
Ｏ共晶液層を生成させ、この液層によりセラミックス基
板を濡らし、次いで冷却固化させてセラミックス基板と
銅回路基板とを直接接合させる方法である。Various methods are known for producing such a ceramic substrate, for example, a DBC method (direct bonding copper method), a DBA method (direct bond aluminum method), an active metal method, and the like. . D
In the BC method, a copper circuit board punched into a predetermined shape is placed in contact with a ceramic substrate and heated, and a Cu-
This is a method in which an O eutectic liquid layer is formed, the ceramic substrate is wetted with the liquid layer, and then cooled and solidified to directly join the ceramic substrate and the copper circuit substrate.
【０００４】また、ＤＢＡ法は、アルミニウム板をＤＢ
Ｃ法と同様に加熱し、接合界面にＡｌ−Ｓｉ共晶液層を
生成させ、この液層によりセラミックス基板を濡らし、
次いで冷却固化させて、セラミックス基板とアルミニウ
ム板とを直接接合させ、あるいはアルミニウム溶湯をセ
ラミックス基板と接触させ、凝固させて直接接合させる
方法である。[0004] In the DBA method, an aluminum plate is converted into a DB.
Heating in the same manner as in Method C, an Al-Si eutectic liquid layer is generated at the joint interface, and the ceramic substrate is wetted with this liquid layer.
Then, it is cooled and solidified, and the ceramic substrate and the aluminum plate are directly bonded, or the molten aluminum is brought into contact with the ceramic substrate, solidified, and directly bonded.
【０００５】さらに活性金属法は、例えば銅回路基板と
セラミックス基板とをロー材であるＣｕ，Ａｇおよび活
性な金属であるＴｉ，Ｈｆ，Ｚｒの寄与により接合させ
る方法である。Further, the active metal method is a method in which, for example, a copper circuit board and a ceramic substrate are joined by the contribution of Cu, Ag which is a brazing material and Ti, Hf, Zr which are active metals.
【０００６】なお、セラミックス基板の材質としては、
窒化珪素、アルミナ、窒化アルミニウム（ＡｌＮ）等が
適用される。The material of the ceramic substrate is as follows.
Silicon nitride, alumina, aluminum nitride (AlN), or the like is applied.
【０００７】図２は、このようにして構成されるセラミ
ックス回路基板の構成を例示したものである。FIG. 2 exemplifies the structure of the ceramic circuit board thus constructed.
【０００８】この図２の例では、セラミックス基板１の
両面に前記の方法を用いて金属回路板２ａ，２ｂが接合
されており、一方の金属回路板２ａには半導体ペレット
３がハンダ４により接合されている。また、他方の金属
回路板２ｂには例えば銅等からなるヒートシンク５がハ
ンダ６により接合されている。In the example shown in FIG. 2, metal circuit boards 2a and 2b are bonded to both surfaces of a ceramic substrate 1 using the above-described method, and a semiconductor pellet 3 is bonded to one of the metal circuit boards 2a by solder 4. Have been. Further, a heat sink 5 made of, for example, copper or the like is joined to the other metal circuit board 2b by solder 6.
【０００９】このようなセラミックス回路基板は、セラ
ミックス基板１と金属回路基板２ａ，２ｂとの接合が強
固であり、かつ単純な構造となるため小型、高実装化が
可能であり、また作業工程も短縮できる等の利点が得ら
れている。In such a ceramic circuit board, the bonding between the ceramic substrate 1 and the metal circuit boards 2a and 2b is strong and has a simple structure, so that the ceramic circuit board can be reduced in size and height, and the working process can be improved. Advantages such as shortening can be obtained.
【００１０】[0010]
【発明が解決しようとする課題】ところが、上述したセ
ラミックス回路基板においては、実際にモジュールに組
込むためにＳｉペレット等の半導体ペレット３を金属回
路板２ａ上にハンダ付けする際、その金属回路板２ａ上
をハンダ４が流れ、半導体ペレット３が位置ずれを起こ
したり、図２に示すように、ハンダブリッジ４ａが生じ
て耐圧不良となる等の問題がある。However, in the above-mentioned ceramic circuit board, when the semiconductor pellets 3 such as Si pellets are soldered onto the metal circuit board 2a in order to actually incorporate them into the module, the metal circuit board 2a There is a problem that the solder 4 flows over the semiconductor pellet 3 to cause a positional shift, and as shown in FIG. 2, a solder bridge 4a is generated to cause a breakdown voltage failure.
【００１１】本発明はこのような事情に鑑みてなされた
もので、半導体ペレットのハンダ付け時にハンダが流れ
て同ペレットが位置ずれしたり、ハンダブリッジによる
耐圧不良が生じることを抑制することができ、良好なハ
ンダ接合の実施、ひいては製造効率向上および高品質化
等が図れるセラミックス回路基板を提供することを目的
とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to suppress the flow of solder at the time of soldering a semiconductor pellet, the pellet being displaced, and the occurrence of withstand voltage failure due to a solder bridge. It is another object of the present invention to provide a ceramic circuit board capable of achieving good solder bonding, improving production efficiency and improving quality.
【００１２】[0012]
【課題を解決するための手段】前記の目的を達成するた
めに、本発明では金属回路板上に、半導体ペレット接合
用ハンダの流動を抑制するための簡易かつ効果的な手段
を設けるものである。In order to achieve the above object, the present invention provides a simple and effective means for suppressing the flow of solder for joining semiconductor pellets on a metal circuit board. .
【００１３】すなわち、本発明では、セラミックス基板
上に金属回路板を接合し、前記金属回路板に半導体ペレ
ットをハンダ付けしてなるセラミックス回路基板におい
て、前記金属回路板の半導体ペレット搭載面のうちハン
ダが塗布されない部位に、ソルダーレジスト層を設けた
ことを特徴とするセラミックス回路基板を提供する。That is, according to the present invention, in a ceramic circuit board in which a metal circuit board is joined on a ceramic substrate and a semiconductor pellet is soldered to the metal circuit board, a soldering portion of the semiconductor pellet mounting surface of the metal circuit board is provided. Provided is a ceramic circuit board characterized in that a solder resist layer is provided in a portion where is not applied.
【００１４】このような構成によると、半導体接合のた
めのハンダが金属回路板上に塗布された場合、そのハン
ダが余分な位置に流動しようとしてもソルダーレジスト
部位で阻止される。したがって、ハンダが金属回路板の
表面の一定範囲内に常時保持され、それにより半導体ペ
レットの移動も阻止されるため、同ペレットが位置ずれ
したり、ハンダブリッジによる耐圧不良が生じることが
抑制され、良好なハンダ接合の実施、ひいては製造効率
の向上および高品質化等が図れるようになる。According to such a configuration, when solder for semiconductor bonding is applied on the metal circuit board, even if the solder attempts to flow to an extra position, it is blocked at the solder resist portion. Therefore, since the solder is always held within a certain range on the surface of the metal circuit board, thereby preventing the movement of the semiconductor pellet, the pellet is prevented from being displaced and the occurrence of withstand voltage failure due to the solder bridge is suppressed, It is possible to achieve good solder joints, thereby improving manufacturing efficiency and improving quality.
【００１５】本発明において、ソルダーレジスト層の厚
さは、５〜１００μｍとすることが望ましい。ハンダの
厚みは５μｍないし同厚みを若干超える量であり、ソル
ダーレジスト層の厚さが５μｍ未満ではハンダの流動阻
止機能が十分に得られない。ソルダーレジスト層の厚さ
が５μｍであると、ハンダがソルダーレジスト上に乗り
上げる可能性があるが、すぐに硬化して乗り越えるに至
らない。ソルダーレジスト層の厚さが１００μｍを超え
ると余分となり、構成が不必要に大型してコンパクト化
の要請に反する結果となる。このような観点からする
と、ソルダーレジストの厚さ（高さ）はハンダ層の厚さ
と同じかそれ以上であることが好ましいと言える。仮
に、ハンダ層の厚さがソルダーレジスト層の厚さより大
きい場合は後述するソルダーレジスト層の幅を０．５ｍ
ｍ以上にすることが好ましい。このようにしておけば、
ハンダが流出したとしてもソルダーレジスト層上で硬化
してしまうため、ハンダブリッジを形成しないで済む。
特に、ハンダ層の厚みがソルダーレジスト層の厚みの２
倍以上のときはソルダーレジスト層の幅が０．５ｍｍ以
上あった方がよい。なお、ソルダーレジスト層は平面視
で枠状に設けることが望ましく、その場合の層の幅は
０．１ｍｍ以上、２ｍｍ以下が望ましい。０．１ｍｍ未
満では上記厚さとの関係でハンダの流動を十分に阻止で
きない場合がある。２ｍｍを超えると、回路構成が不要
に大型化する。なお、最も望ましい幅の範囲は、０．５
ｍｍ以上、２ｍｍ以下である。In the present invention, the thickness of the solder resist layer is desirably 5 to 100 μm. The thickness of the solder is 5 μm or slightly more than the thickness. If the thickness of the solder resist layer is less than 5 μm, the function of preventing the flow of the solder cannot be sufficiently obtained. If the thickness of the solder resist layer is 5 μm, the solder may run on the solder resist, but hardens immediately and does not get over. If the thickness of the solder resist layer exceeds 100 μm, the thickness becomes excessive, and the configuration is unnecessarily large, which is contrary to the demand for compactness. From such a viewpoint, it can be said that the thickness (height) of the solder resist is preferably equal to or greater than the thickness of the solder layer. If the thickness of the solder layer is larger than the thickness of the solder resist layer, the width of the solder resist layer described later is set to 0.5 m.
m or more. If you do this,
Even if the solder flows out, it hardens on the solder resist layer, so that it is not necessary to form a solder bridge.
In particular, the thickness of the solder layer is two times the thickness of the solder resist layer.
When it is twice or more, the width of the solder resist layer should be 0.5 mm or more. The solder resist layer is desirably provided in a frame shape in a plan view, and in this case, the width of the layer is desirably 0.1 mm or more and 2 mm or less. If the thickness is less than 0.1 mm, the flow of the solder may not be sufficiently prevented due to the thickness. If it exceeds 2 mm, the circuit configuration becomes unnecessarily large. Note that the most desirable width range is 0.5
mm or more and 2 mm or less.
【００１６】また、本発明においては、ソルダーレジス
ト層として、ＵＶ硬化性樹脂、熱硬化性樹脂または耐熱
性樹脂等が種々適用できる。この場合、耐熱性は２５０
℃程度で十分である。In the present invention, various materials such as a UV-curable resin, a thermosetting resin, and a heat-resistant resin can be used as the solder resist layer. In this case, the heat resistance is 250
C is enough.
【００１７】さらに本発明では、ソルダーレジスト層
が、ハンダ塗布面を囲む配置で設けられていることが望
ましい。これによりハンダの流動をあらゆる方向から防
止することが可能となる。Further, in the present invention, it is desirable that the solder resist layer is provided so as to surround the solder application surface. This makes it possible to prevent the flow of the solder from all directions.
【００１８】[0018]
【発明の実施の形態】以下、本発明に係るセラミックス
回路基板の実施形態について、図２を参照して説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a ceramic circuit board according to the present invention will be described below with reference to FIG.
【００１９】図２は、本実施形態によるセラミックス回
路基板の構成を示す図である。なお、説明を容易にする
ため、全体構成については図２に示した従来のものと同
様のものを適用する。したがって、従来の構成部分と同
一部分については、図１に図２と同符号を用いて説明す
る。FIG. 2 is a view showing the structure of the ceramic circuit board according to the present embodiment. For the sake of simplicity, the same configuration as the conventional configuration shown in FIG. 2 is applied. Therefore, the same parts as those of the related art will be described with reference to FIG.
【００２０】このセラミックス回路基板は、セラミック
ス基板１の両面に金属回路板２ａ，２ｂを接合した構成
とされている。セラミックス基板１としては、例えば窒
化アルミニウム、窒化珪素、アルミナ、ジルコニア等が
適用されている。金属回路板２ａ，２ｂとしては、銅、
アルミニウム、クラッド材等が適用されている。これら
は、上述したＤＢＣ法、ＤＢＡ法、活性金属法等によっ
て接合されている。The ceramic circuit board has a configuration in which metal circuit boards 2a and 2b are joined to both surfaces of a ceramic substrate 1. As the ceramic substrate 1, for example, aluminum nitride, silicon nitride, alumina, zirconia, or the like is applied. Copper is used as the metal circuit boards 2a and 2b.
Aluminum, clad material, etc. are applied. These are joined by the above-described DBC method, DBA method, active metal method, or the like.
【００２１】そして、一方の金属回路板２ａには例えば
Ｓｉペレット等の半導体ペレット３がハンダ４により接
合されている。また、他方の金属回路板２ｂには例えば
銅等からなるヒートシンク５がハンダ６により接合され
ている。A semiconductor pellet 3 such as a Si pellet is bonded to one of the metal circuit boards 2a by a solder 4. Further, a heat sink 5 made of, for example, copper or the like is joined to the other metal circuit board 2b by solder 6.
【００２２】このようなセラミックス回路基板におい
て、本実施形態では、一方の金属回路板２ａの半導体ペ
レット搭載面のうちハンダ６が塗布されない部位に、ソ
ルダーレジスト層７がハンダ塗布面を囲む配置で設けら
れている。In such a ceramic circuit board, in the present embodiment, a solder resist layer 7 is provided on the semiconductor pellet mounting surface of one of the metal circuit boards 2a where the solder 6 is not applied in such a manner as to surround the solder application surface. Have been.
【００２３】このソルダーレジスト層７は、例えばＵＶ
硬化性樹脂、熱硬化性樹脂または耐熱性樹脂により枠状
に構成されており、耐熱性は２５０℃程度のものとされ
ている。また、ソルダーレジスト層７の厚さは、５〜１
００μｍの範囲に設定され、ソルダーレジスト層７の幅
は０．１ｍｍ〜２ｍｍとされている。The solder resist layer 7 is made of, for example, UV
It is made of a curable resin, a thermosetting resin, or a heat-resistant resin in a frame shape, and has a heat resistance of about 250 ° C. The thickness of the solder resist layer 7 is 5 to 1
The width of the solder resist layer 7 is set to 0.1 mm to 2 mm.
【００２４】このような構成によると、半導体接合のた
めのハンダ４が金属回路板２ａ上に塗布された場合、そ
のハンダ４が金属回路板２ａの表面の一定範囲内に常時
保持された。したがって、図１に示すように、半導体ペ
レット３は定位置に安定して保持され、位置ずれが生じ
ることがなく、また図２に示したようなハンダブリッジ
が生じることもなかった。According to such a configuration, when the solder 4 for semiconductor bonding is applied on the metal circuit board 2a, the solder 4 is always held within a certain range on the surface of the metal circuit board 2a. Therefore, as shown in FIG. 1, the semiconductor pellet 3 was stably held at a fixed position, no displacement occurred, and no solder bridge as shown in FIG. 2 occurred.
【００２５】なお、ソルダーレジスト層７の形成方法は
特に限定されるものではないが、例えば下記のような方
法がある。金属回路板の所定の位置にレジストインク
（レジスト含有溶液）を塗布できるようマスク材を配置
しスクリーン印刷等の方法により印刷する。この後、例
えば、レジスト材がＵＶ硬化型インクであれば印刷直後
にＵＶ乾燥によりインクを乾燥させてソルダーレジスト
層を形成する。また、熱硬化型インクであれば、同様の
方法でインクを塗布した後、熱処理により乾燥させる方
法などが挙げられる。The method of forming the solder resist layer 7 is not particularly limited, but includes, for example, the following method. A mask material is arranged so that resist ink (resist-containing solution) can be applied to a predetermined position on the metal circuit board, and printing is performed by a method such as screen printing. Thereafter, for example, if the resist material is a UV-curable ink, the ink is dried by UV drying immediately after printing to form a solder resist layer. In the case of a thermosetting ink, a method in which the ink is applied by a similar method and then dried by heat treatment may be used.
【００２６】また、ソルダーレジスト層７の厚さおよび
幅と、ハンダ４の塗布厚さとの関係を示すと、下記の表
１に示すとおりであった。ソルダーレジスト層の形成形
態としては、いずれも金属回路板上の半導体ペレット搭
載面においてハンダが塗布されない部位に形成した。こ
の表１に示すように、本実施形態においては、上述した
従来のセラミックス回路基板における問題、すなわち金
属回路板２ａ上をハンダ４が流れたり、半導体ペレット
３が位置ずれを起こしたり、ハンダブリッジ４ａが生じ
て耐圧不良となる等の問題が解消できることが確認され
た。参考例として示したようにハンダ層の厚みがソルダ
ーレジスト層の２倍ある場合、ソルダーレジスト層の幅
が０．５ｍｍ未満であるとハンダ層の流出がおきること
が確認された。なお、ハンダ層の厚さがソルダーレジス
ト層の厚さに対して３倍以上ある場合はソルダーレジス
ト層の幅を１．０ｍｍ以上にすることにより対応可能で
あるが、できれば２倍以下になるようにソルダーレジス
ト層の厚さを制御した方がよい。さらに比較例１に示し
たようにソルダーレジスト層の厚さが５μｍ未満である
と、半導体ペレットの移動がおきてしまうことが分かっ
た。これは半導体ペレットをハンダ接合するためのハン
ダ量が多量に流出してしまうためにこのような現象がお
きてしまったものと推測される。The relationship between the thickness and width of the solder resist layer 7 and the thickness of the solder 4 is shown in Table 1 below. Regarding the formation form of the solder resist layer, the solder resist layer was formed at a portion where the solder was not applied on the semiconductor pellet mounting surface on the metal circuit board. As shown in Table 1, in the present embodiment, the above-described problems in the conventional ceramic circuit board, that is, the solder 4 flows on the metal circuit board 2a, the semiconductor pellet 3 is displaced, and the solder bridge 4a It was confirmed that problems such as the occurrence of poor pressure resistance and the like could be solved. As shown in the reference example, when the thickness of the solder layer was twice as large as that of the solder resist layer, it was confirmed that the solder layer flowed out when the width of the solder resist layer was less than 0.5 mm. In addition, when the thickness of the solder layer is three times or more the thickness of the solder resist layer, it can be dealt with by making the width of the solder resist layer 1.0 mm or more. It is better to control the thickness of the solder resist layer. Further, as shown in Comparative Example 1, it was found that when the thickness of the solder resist layer was less than 5 μm, the movement of the semiconductor pellet occurred. This is presumably because such a phenomenon occurred because a large amount of solder flowed out for soldering the semiconductor pellet.
【００２７】[0027]
【表１】 [Table 1]
【００２８】[0028]
【発明の効果】以上のように、本発明によれば、金属回
路板の半導体ペレット搭載面のうちハンダが塗布されな
い部位に、ソルダーレジスト層を設けたことにより、半
導体ペレットのハンダ付け時にハンダが流れて同ペレッ
トが位置ずれしたり、ハンダブリッジによる耐圧不良が
生じることを抑制することができ、良好なハンダ接合の
実施、ひいては製造効率向上および高品質化等が図れる
という効果が奏される。As described above, according to the present invention, the solder resist layer is provided on the portion of the metal circuit board on which the solder is not applied, on the semiconductor pellet mounting surface, so that the solder can be soldered when the semiconductor pellet is soldered. It is possible to suppress the flow of the pellet and the displacement of the pellet and the occurrence of a breakdown voltage failure due to the solder bridge, and to achieve an effect of performing good solder bonding, thereby improving manufacturing efficiency and improving quality.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明に係るセラミックス基板の実施形態を示
す構成図。FIG. 1 is a configuration diagram showing an embodiment of a ceramic substrate according to the present invention.
【図２】従来例を示す構成図。FIG. 2 is a configuration diagram showing a conventional example.
１ セラミックス基板 ２ａ，２ｂ 金属回路板 ３ 半導体ペレット ４，６ ハンダ ５ ヒートシンク ７ ハンダレジスト層 DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2a, 2b Metal circuit board 3 Semiconductor pellet 4,6 Solder 5 Heat sink 7 Solder resist layer
フロントページの続き (72)発明者 五代儀 靖 神奈川県横浜市鶴見区末広町二丁目４番地 株式会社東芝京浜事業所内 (72)発明者 那波 隆之 神奈川県横浜市鶴見区末広町二丁目４番地 株式会社東芝京浜事業所内 Ｆターム(参考） 5F036 AA01 BB01 BC06 BD13 5F047 AA19 BA06 BC40 Continuation of the front page (72) Inventor Yasushi Godai 2-4-4 Suehirocho, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture Inside the Keihin Works, Toshiba Corporation (72) Inventor Takayuki Nawa 2--4, Suehirocho, Tsurumi-ku, Yokohama-shi, Kanagawa F-term in Toshiba Keihin Works (reference) 5F036 AA01 BB01 BC06 BD13 5F047 AA19 BA06 BC40
Claims (4)
し、前記金属回路板に半導体ペレットをハンダ付けして
なるセラミックス回路基板において、前記金属回路板の
半導体ペレット搭載面のうちハンダが塗布されない部位
に、ソルダーレジスト層を設けたことを特徴とするセラ
ミックス回路基板。1. A portion of a ceramic circuit board obtained by joining a metal circuit board on a ceramic substrate and soldering a semiconductor pellet to the metal circuit board, on the semiconductor pellet mounting surface of the metal circuit board on which solder is not applied. A ceramic circuit board, further comprising a solder resist layer provided thereon.
おいて、ソルダーレジスト層の厚さは、５〜１００μｍ
であることを特徴とするセラミックス回路基板。2. The ceramic circuit board according to claim 1, wherein the thickness of the solder resist layer is 5 to 100 μm.
A ceramic circuit board, characterized in that:
路基板において、ソルダーレジスト層は、ＵＶ硬化性樹
脂、熱硬化性樹脂または耐熱性樹脂からなることを特徴
とするセラミックス回路基板。3. The ceramic circuit board according to claim 1, wherein the solder resist layer is made of a UV-curable resin, a thermosetting resin, or a heat-resistant resin.
セラミックス回路基板において、ソルダーレジスト層
は、ハンダ塗布面を囲む配置で設けられていることを特
徴とするセラミックス回路基板。4. The ceramic circuit board according to claim 1, wherein the solder resist layer is provided so as to surround a solder application surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36825099A JP2001185664A (en) | 1999-12-24 | 1999-12-24 | Ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36825099A JP2001185664A (en) | 1999-12-24 | 1999-12-24 | Ceramic circuit board |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005157913A Division JP4439432B2 (en) | 2005-05-30 | 2005-05-30 | Ceramic circuit board manufacturing method |
| JP2005358121A Division JP2006135347A (en) | 2005-12-12 | 2005-12-12 | Ceramics circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001185664A true JP2001185664A (en) | 2001-07-06 |
Family
ID=18491341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36825099A Pending JP2001185664A (en) | 1999-12-24 | 1999-12-24 | Ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001185664A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005520334A (en) * | 2002-03-13 | 2005-07-07 | スチュルス−ハーダー，ジャーヘン | Process for producing a metal-ceramic substrate, preferably a copper-ceramic substrate |
| WO2008123386A1 (en) * | 2007-03-22 | 2008-10-16 | Toyota Jidosha Kabushiki Kaisha | Power module and inverter for vehicle |
| JP2009099663A (en) * | 2007-10-15 | 2009-05-07 | Rohm Co Ltd | Power module |
| JP2010010574A (en) * | 2008-06-30 | 2010-01-14 | Nichicon Corp | Semiconductor device and its manufacturing method |
| US8342384B2 (en) | 2002-03-13 | 2013-01-01 | Curamik Electronics Gmbh | Method for the production of a metal-ceramic substrate, preferably a copper ceramic substrate |
| KR101255334B1 (en) | 2006-05-08 | 2013-04-16 | 페어차일드코리아반도체 주식회사 | Power module for low thermal resistance and method of fabricating of the same power module |
| CN103531582A (en) * | 2012-07-06 | 2014-01-22 | 株式会社丰田自动织机 | Semiconductor unit |
| DE102014211562A1 (en) * | 2014-06-17 | 2015-12-17 | Robert Bosch Gmbh | Semiconductor arrangement with a heat sink |
| CN109075136A (en) * | 2016-04-28 | 2018-12-21 | 电化株式会社 | Ceramic circuit board and its manufacturing method |
| WO2019097685A1 (en) * | 2017-11-17 | 2019-05-23 | 三菱電機株式会社 | Semiconductor module |
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1999
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005520334A (en) * | 2002-03-13 | 2005-07-07 | スチュルス−ハーダー，ジャーヘン | Process for producing a metal-ceramic substrate, preferably a copper-ceramic substrate |
| US8342384B2 (en) | 2002-03-13 | 2013-01-01 | Curamik Electronics Gmbh | Method for the production of a metal-ceramic substrate, preferably a copper ceramic substrate |
| KR101255334B1 (en) | 2006-05-08 | 2013-04-16 | 페어차일드코리아반도체 주식회사 | Power module for low thermal resistance and method of fabricating of the same power module |
| WO2008123386A1 (en) * | 2007-03-22 | 2008-10-16 | Toyota Jidosha Kabushiki Kaisha | Power module and inverter for vehicle |
| JP2009099663A (en) * | 2007-10-15 | 2009-05-07 | Rohm Co Ltd | Power module |
| JP2010010574A (en) * | 2008-06-30 | 2010-01-14 | Nichicon Corp | Semiconductor device and its manufacturing method |
| CN103531582A (en) * | 2012-07-06 | 2014-01-22 | 株式会社丰田自动织机 | Semiconductor unit |
| DE102014211562A1 (en) * | 2014-06-17 | 2015-12-17 | Robert Bosch Gmbh | Semiconductor arrangement with a heat sink |
| CN109075136A (en) * | 2016-04-28 | 2018-12-21 | 电化株式会社 | Ceramic circuit board and its manufacturing method |
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| CN109075136B (en) * | 2016-04-28 | 2022-08-02 | 电化株式会社 | Ceramic circuit board and method for manufacturing the same |
| WO2019097685A1 (en) * | 2017-11-17 | 2019-05-23 | 三菱電機株式会社 | Semiconductor module |
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