JP2001156652A - Peference amplitude level setting device and viterbi decoder - Google Patents

Peference amplitude level setting device and viterbi decoder

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Publication number
JP2001156652A
JP2001156652A JP34080799A JP34080799A JP2001156652A JP 2001156652 A JP2001156652 A JP 2001156652A JP 34080799 A JP34080799 A JP 34080799A JP 34080799 A JP34080799 A JP 34080799A JP 2001156652 A JP2001156652 A JP 2001156652A
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Japan
Prior art keywords
pa
amplitude level
reference amplitude
dc component
pr
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JP34080799A
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Japanese (ja)
Inventor
Masaaki Hara
雅明 原
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Sony Corp
ソニー株式会社
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Priority to JP34080799A priority Critical patent/JP2001156652A/en
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Abstract

PROBLEM TO BE SOLVED: To provide a reference amplitude level setting device that automatically calculates a reference amplitude level corresponding to equalization characteristic parameters. SOLUTION: A DC component calculation means 11 obtains a DC component of an equalization characteristic by using pa [0], pa [1],..., pa [n-1] received externally. A reference amplitude level setting means 12 applies a convolutional arithmetic operation between received recording data and the equalization characteristic and subtracts the DC component from the result of the convolutional arithmetic operation to set the reference amplitude level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference amplitude level setting device and a Viterbi decoding device, and more particularly to a reference amplitude level setting device having an intersymbol interference length of n.
Are equalized PR (pa [0], pa [1],...,
The present invention relates to a reference amplitude level setting device that sets a reference amplitude level and a Viterbi decoding device that receives a reproduced signal and a reference amplitude level and performs Viterbi decoding when performing Viterbi decoding using pa [n−1]). The reference amplitude level setting device and the Viterbi decoding device are applied to, for example, a video tape recorder and an optical disk device.

[0002]

2. Description of the Related Art In the field of digital mass storage such as digital VTRs, hard disks, and optical disks, a reproduction equalization / detection method called PRML has been actively studied in recent years.

[0003] This is the Partial Response Maximum Likliho
od, an abbreviation of od, which is a multi-valued partial response method that enables recording and playback in a narrow band, and a good error rate compared to identification for each bit by recursively calculating the likelihood of state transition Is combined with the maximum likelihood decoding method that can obtain A typical algorithm of the maximum likelihood decoding method is Viterbi decoding, and a decoder that realizes this is generally called a Viterbi decoder.

A recording modulation code for applying PRML is arbitrary, but in the following description, a case of a recording modulation code having a minimum inversion width of 2 or more, which is assumed in the present invention, will be described as an example.

The recording modulation code having the minimum inversion width of 2 includes Miller Square code, 8-14 conversion code, and RLL.
(Run Length Limited) (1,7) and NRZI (Non Ret
urnto Zero Inverted), which are often used in digital VTRs and optical disk drives.

FIG. 9 is a trellis diagram for Viterbi decoding with an intersymbol interference length of 3, FIG. 10 is a trellis diagram for Viterbi decoding with an intersymbol interference length of 4, and FIG. 11 is a trellis diagram for Viterbi decoding with an intersymbol interference length of 5. It is a figure which shows a diagram. In FIG. 9, for example, state S0
If the input is 1 at the time, the output is C01 and the state S
Transitions to 1. Others are the same. FIG. 12 shows a reference amplitude level for Viterbi decoding with an intersymbol interference length of 3, and FIG.
14 shows a reference amplitude level for Viterbi decoding with an intersymbol interference length of 4, and FIG. 14 shows a reference amplitude level for Viterbi decoding with an intersymbol interference length of 5.

The simplest Viterbi decoding is PR (1,
This is a 4-state Viterbi decoder using 1) and the like as equalization characteristics. The reference amplitude level is originally six values, but PR
If (1, 1), the value is reduced to three values, and if PR (1, 2, 1), the value is reduced to four values. When the delay operator D for one clock is used, PR (1,1) that can be expressed as 1 + D is further obtained by adding 1 + D to PR (1,2,1). , 3,3,1).

Further, PR (1,1) is changed to (1-D) (1+
D), PR (1,1, -1, -1) is obtained, and if this is further added by 1 + D, PR (1,2,0, -2, -1) is obtained.

The term "PR operation" in FIGS. 12 to 14 shows an arithmetic expression necessary to obtain a desired equalization characteristic from PR (1, 1) (A in the figures). ^ B is B of A
Indicates the power). In general, the bit identification performance of a Viterbi decoder is
It is improved by increasing the intersymbol interference length.

PR (1,1, -1, -1) is EPR4,
PR (1, 2, 0, -2, -1) is called EEPR4, and PRML using this equalization characteristic is a magnetic recording in which the transfer characteristic is a differential system, such as a digital VTR or a hard disk drive. It is well known that a reproduction system has strong discrimination performance.

[0011]

When an integrated circuit of a Viterbi decoder is considered, it is easily expected that there will be a demand for making it as versatile as possible so that it can be used for an optical disk and a digital VTR. In that case, since the effective equalization characteristics are different, the “PR calculation” to be performed is also different, and the reference amplitude level to be set is also different.
It is necessary to reset each.

However, it is very troublesome to input these values one by one. Therefore, FIGS.
Focusing on the one-to-one correspondence between the equalization characteristic and the reference amplitude level as in No. 4, number the equalization characteristics to be used and store the corresponding reference amplitude level in a register. However, this method has a problem that the use is limited because only the equalization characteristics set in advance can be used.

The present invention has been made in view of such a point, and a reference amplitude level setting device for automatically calculating a reference amplitude level and setting efficiently by simply inputting a parameter of an equalization characteristic. The purpose is to provide.

It is another object of the present invention to provide a Viterbi decoding device that performs Viterbi decoding with high accuracy in accordance with an arbitrary equalization characteristic.

[0015]

According to the present invention, in order to solve the above-mentioned problem, an equalization characteristic PR having an inter-symbol interference length of n is set.
When performing Viterbi decoding using (pa [0], pa [1],..., Pa [n-1]), a reference amplitude level setting device that sets a reference amplitude level uses pa [ 0], pa [1],..., Pa [n-1], a DC component calculating means for calculating a DC component of the equalization characteristic, and a convolution operation of the input recording data and the equalization characteristic, A reference amplitude level setting device for setting the reference amplitude level by subtracting the DC component from the result of the convolution operation.

Here, the DC component calculating means includes an externally supplied pa [0], pa [1],..., Pa [n-1]
From the DC component of the equalization characteristic. The reference amplitude level setting means performs a convolution operation of the input recording data and the equalization characteristic, subtracts a DC component from the result of the convolution operation, and sets a reference amplitude level.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of the reference amplitude level setting device of the present invention. Reference amplitude level setting device 10
Is any equalization characteristic PR (pa
When performing Viterbi decoding using [0], pa [1],..., Pa [n−1]), a reference amplitude level is set.

The DC component calculation means 11 obtains a DC component of the equalization characteristic from pa [0], pa [1],..., Pa [n-1] given from the outside. The reference amplitude level setting means 12 performs a convolution operation on the input recording data and the equalization characteristic, subtracts a DC component from the result of the convolution operation, and sets a reference amplitude level. The details will be described later.

Next, based on FIGS. 2 to 4 and FIGS. 5 to 7, a state transition diagram, a state number and a reference amplitude level defining method of the present invention will be described with reference to FIGS.
14 will be described in comparison with FIG.

FIG. 2 is a trellis diagram which is the basis of the present invention for Viterbi decoding with an intersymbol interference length of 3, and FIG.
FIG. 4 is a diagram showing a trellis diagram which is the basis of the present invention for the Viterbi decoding of the present invention, and FIG.

FIG. 5 shows a reference amplitude level on which Viterbi decoding with an intersymbol interference length of 3 is based on the present invention, and FIG. 6 shows a reference amplitude level on which Viterbi decoding with an intersymbol interference length of 4 is based on the present invention. FIG. 7 shows a reference amplitude level on which Viterbi decoding with an intersymbol interference length of 5 is based on the present invention.

9 to 11, the state numbers are S0 to S9.
Until it was continuously assigned. The rules for assigning numbers are arbitrary and are not explicitly specified. And
The reference amplitude level transitioning from the state Si to Sj has been defined by Cij. At this time, looking at FIGS.
It is impossible to easily know how the value of the reference amplitude level Cij is determined.

On the other hand, in the state transition diagram, the state number, and the reference amplitude level defining method which are the basis of the present invention, the recorded data at the times k-4, k-3, k-2, k-1, and k are used. Are i, j, k, l, and m, time k−4, k−
State Sijk determined by recording data of 3, k-2, k-1
The reference amplitude level when transitioning from 1 to the state Sjklm determined by the recording data at times k-3, k-2, k-1, and k is set to Cjklm.

The major difference from the prior art is that the number of the reference amplitude level indicates not only the previous state and the present state but also the recorded data of the intersymbol interference length + 1 between them is clearly indicated. . The reason why the numbers of the state and the reference amplitude level are discontinuous is that S0100, S1010, and the like do not exist because the code having the minimum inversion width of 2 is used as an example. When a code or the like is used, S0100, S1010, and the like also exist, resulting in 16 states.

The present invention focuses on the fact that, based on the definitions in FIGS. 2 to 4 and FIGS. 5 to 7, the reference amplitude level for an arbitrary equalization characteristic can be easily calculated as described below. It was conceived.

First, the equalization characteristic is calculated by PR (pa0, pa1,
pa2, pa3, pa4). PR (1,2,
0, -2, -1), pa0 = + 1, pa1 = +
2, pa2 = 0, pa3 = -2, pa4 = −1,
If PR (0, 1, 2, 1, 0), pa0 = 0, pa
1 = + 1, pa2 = + 2, pa3 = + 1, pa4 = 0. First, an average value avr is calculated to subtract the DC component of the equalization characteristic.

[0027]

Avr = (pa0 + pa1 + pa2 + pa3 + pa4) / 2 (1) In calculating each reference amplitude level, the DC component may be subtracted after convolving the input recording data with the equalization characteristic.

[0028]

## EQU00002 ## Cijklm = A * (i * pa4 + j * pa3 + k * pa2 + l * pa1 + m * pa0-avr) (2) where A is a constant determined by the number of bits of the AD converter, the operation accuracy of the Viterbi decoder, and the like. Then, for example, FIGS.
Is equivalent to the case where A / D conversion is performed with 6 bits. Since the dynamic range is ± 16, A = 16 is calculated.
In order to confirm that the results in FIGS. 5 to 7 and FIGS. 12 to 14 match, PR (1, 2, 0, -2,-
1) and PR (0, 1, 2, 1, 0) will be specifically calculated. First, calculation of PR (1, 2, 0, -2, -1) will be described.

[0029]

Avr = (− 1-2 + 0 + 2 + 1) / 2 = 0 (3)

[0030]

C0000 = 16 * (0 * (− 1)) + 0 * (− 2) + 0 * (0) + 0 * (2) + 0 * (1) − (0)) = 0 (4a) C00001 = 16 * (0 * (-1)) + 0 * (-2) + 0 * (0) + 0 * (2) + 1 * (1)-(0)) = + 16 (4b) C00011 = 16 * (0 * ( -1)) + 0 * (-2) + 0 * (0) + 1 * (2) + 1 * (1)-(0)) = + 48 (4c) C00110 = 16 * (0 * (-1)) + 0 * (-2) + 1 * (0) + 1 * (2) + 0 * (1)-(0)) = + 32 (4d) C00111 = 16 * (0 * (-1)) + 0 * (-2) + 1 * (0) + 1 * (2) + 1 * (1)-(0)) = + 48 (4e) C01100 = 16 * (0 * (-1)) + 1 * (-2) + 1 * (0) + 0 * ( 2) + 0 * 1)-(0)) =-32 (4f) C01110 = 16 * (0 * (-1)) + 1 * (-2) + 1 * (0) + 1 * (2) + 0 * (1)-(0) )) = 0 (4 g) C01111 = 16 * (0 * (-1)) + 1 * (-2) + 1 * (0) + 1 * (2) + 1 * (1)-(0)) = + 16 ( 4h) C10000 = 16 * (1 * (-1)) + 0 * (-2) + 0 * (0) + 0 * (2) + 0 * (1)-(0)) =-16 (4i) C10001 = 16 * (1 * (-1)) + 0 * (-2) + 0 * (0) +0 * (2) + 1 * (1)-(0)) = 0 (4j) C10011 = 16 * (1 * (-) 1)) + 0 * (-2) + 0 * (0) + 1 * (2) + 1 * (1)-(0)) = + 32 (4k) C11000 = 16 * (1 * (-1)) + 1 * ( −2) + 0 * (0 + 0 * (2) + 0 * (1)-(0)) =-48 (4l) C11001 = 16 * (1 * (-1)) + 1 * (-2) + 0 * (0) + 0 * (2) + 1 * (1)-(0)) =-32 (4m) C11100 = 16 * (1 * (-1)) + 1 * (-2) + 1 * (0) + 0 * (2) + 0 * (1) − (0)) = − 48 (4n) C11110 = 16 * (1 * (− 1)) + 1 * (− 2) + 1 * (0) + 1 * (2) + 0 * (1) − (0)) = -16 ... (4o) C11111 = 16 * (1 * (-1)) + 1 * (-2) + 1 * (0) + 1 * (2) + 1 * (1)-(0)) = 0 ... (4p Next, PR (0, 1, 2, 1, 0) will be described.

[0031]

Avr = (0 + 1 + 2 + 1 + 0) / 2 = 2 (5)

[0032]

C0000 = 16 * (0 * (0)) + 0 * (1) + 0 * (2) + 0 * (1) + 0 * (0) − (2)) = − 32 (6a) C00001 = 16 * (0 * (0)) + 0 * (1) + 0 * (2) +0 * (1) + 1 * (0)-(2)) = − 32 (6b) C00011 = 16 * (0 * (0) ) + 0 * (1) + 0 * (2) + 1 * (1) + 1 * (0)-(2)) = − 16 (6c) C00110 = 16 * (0 * (0)) + 0 * (1) +1 * (2) + 1 * (1) + 0 * (0)-(2)) = + 16 (6d) C00111 = 16 * (0 * (0)) + 0 * (1) + 1 * (2) + 1 * (1 ) + 1 * (0)-(2)) = + 16 (6e) C01100 = 16 * (0 * (0)) + 1 * (1) + 1 * (2) + 0 * (1) + 0 * (0)-( 2)) = + 6 ... (6f) C01110 = 16 * (0 * (0)) + 1 * (1) + 1 * (2) + 1 * (1) + 0 * (0)-(2)) = + 32 ... (6g) C01111 = 16 * (0 * (0)) + 1 * (1) + 1 * (2) + 1 * (1) + 1 * (0)-(2)) = + 32 (6h) C10000 = 16 * (1 * (0)) + 0 * (1) + 0 * (2) + 0 * (1) + 0 * (0)-(2)) = − 32 (6i) C10001 = 16 * (1 * (0)) + 0 * (1) + 0 * (2) + 0 * (1) + 1 * (0)-(2)) = − 32 (6j) C10011 = 16 * (1 * (0)) + 0 * (1) + 0 * (2) + 1 * (1 ) + 1 * (0)-(2)) =-16 (6k) C11000 = 16 * (1 * (0)) + 1 * (1) + 0 * (2) + 0 * (1) + 0 * (0)- (2)) = -16 ... (6l) C11001 = 16 * (1 * (0)) + 1 * (1) + 0 * (2) + 0 * (1) + 1 * (0)-(2)) =-16 ... (6m) C11100 = 16 * (1 * (0)) + 1 * (1) + 1 * (2) + 0 * (1) + 0 * (0)-(2)) = + 16 (6n) C11110 = 16 * (1 * ( 0)) + 1 * (1) + 1 * (2) + 1 * (1) + 0 * (0)-(2)) = + 32 (6o) C11111 = 16 * (1 * (0)) + 1 * (1) + 1 * (2) + 1 * (1) + 1 * (0)-(2)) = + 32 (6p) Next, FIG. 8 shows the configuration of a Viterbi decoding device to which the reference amplitude level setting device 10 of the present invention is applied. . The Viterbi decoding device 100 of the present invention includes a PRC (PR parameter Calculator) 1,
EQC (EQ parameter calculator) 2, RVC (Referen
ce Value Calculator) 3, BMC (Branch Metric Calculator)
lator) 4, ACS (Add, Compare & Select) 5, PMU (P
ath Memory Unit) 6.

In the present invention, the present invention can be applied irrespective of the recording modulation code and the equalization characteristics before AD conversion.
For simplicity, a recording modulation code with a minimum inversion width of 2 is used, and A
The equalization characteristic before D conversion is PR (1, 1) or PR
The case of (1, 2, 1) will be described.

Sph is a switch for selecting an equalization characteristic before AD conversion. When sph = 0, PR is used.
(1,1), PR (1,2,1) when sph = 1. pr = 0, pr = 1, pr = 2, pr = 3 is PR
This is a parameter of “PR calculation” for making (1,1) or PR (1,2,1) a desired equalization characteristic. The reproduced signal [k] after the AD conversion is input to the PRC 1 for performing the PR operation, and is calculated as follows to be converted into pb [k] having a desired equalization characteristic (reproduced signal calculating means of the present invention) Applicable).

[0035]

[Mathematical formula-see original document] pb [k] = z [k-3] * pr3 + z [k-2] * pr2 + z [k-1] * pr1 + z [k] * pr0 (7) With the calculated EQC2, pa0 to pa4 are calculated as follows from sph, pr0 to pr3.

First, when PR (1,1) sph = 0,

[0037]

Pa8 = 1 * pr0 (8a) pa1 = 1 * pr1 + 1 * pr0 (8b) pa2 = 1 * pr2 + 1 * pr1 (8c) pa3 = 1 * pr3 + 1 * pr2 (8d) pa4 = 1 * pr3 ... (8e) And, when PR (1,2,1) sph = 1,

[0038]

Pa0 = 1 * pr0 (9a) pa1 = 1 * pr1 + 2 * pr0 (9b) pa2 = 1 * pr2 + 2 * pr1 + 1 * pr0 (9c) pa3 = 2 * pr2 + 1 * pr1 (9d) pa4 = 1 * pr2 (9e) Finally, RVC3 obtains the reference amplitude level by using the above equations (1) and (2) using pa0 to pa4 obtained by EQC2.

Next, PRC1, EQC2, RV
The block configuration located after C3 will be described.
The first BMC4 is based on pb [k] and R obtained from PRC1.
Reference amplitude level C0000-C11 obtained by VC3
111 and the branch metric BM0 as follows:
This is a circuit for calculating 0000 to BM11111.

[0040]

BM00000 = (C00000-pb [k]) ^ 2 (10a) BM00001 = (C00001-pb [k]) ^ 2 (10b) BM00011 = (C00011-pb [k]) ^ 2 (( 10c) BM00110 = (C00110-pb [k]) ^ 2 (10d) BM00111 = (C00111-pb [k]) ^ 2 (10e) BM01100 = (C01100-pb [k]) ^ 2 (10f) BM01110 = (C01110-pb [k]) ^ 2 ... (10g) BM01111 = (C01111-pb [k]) ^ 2 ... (10h) BM10000 = (C10000-pb [k]) ^ 2 ... (10i) BM10001 = (C10001-pb [k]) 2 (10j) BM10011 = (C10011-pb [k] ^ 2 ... (10k) BM11000 = (C11000-pb [k]) ^ 2 ... (10l) BM11001 = (C11001-pb [k]) ^ 2 ... (10m) BM11100 = (C11100-pb [k]) ^ 2 … (10n) BM11110 = (C11110−pb [k]) ^ 2… (10o) BM11111 = (C11111−pb [k]) ^ 2… (10p) The next ACS5 is each state held internally. Path metrics MT0000 to MT1111 and branch metrics BM0000 to BM1 calculated by BMC4
1111 is added (Add) as follows.

[0041]

MM00000 = BM00000 + MT0000 (11a) MM00001 = BM00001 + MT0000 (11b) MM00011 = BM00011 + MT0001 (11c) MM00110 = BM00110 + MT0011 (11d) MM00111 = BM00111 + MT0011 (11B01) 01 (100) (11g) MM01111 = BM01111 + MT0111 (11h) MM10000 = BM10000 + MT1000 (11i) MM10001 = BM10001 + MT1000 (11j) MM10011 = BM10011 + MT1001 (11k) MM11000 = BM11 00 + MT1100 ... (11l) MM11001 = BM11001 + MT1100 ... (11m) MM11100 = BM11100 + MT1110 ... (11n) MM11110 = BM11110 + MT1111 ... (11o) MM11111 = BM11111 + MT1111 ... (11p) and, summed metric MM00000~MM1
1111 is compared (Compare) as follows.
The selection signals SEL0000 to SEL1111 are output to the PMU6.

[0042]

SEL0000 = MM0000> MM10000 (12a) SEL0001 = MM00001> MM10001 (12b) SEL0010 = 0 (12c) SEL0011 = MM00011> MM10011 (12d) SEL0100 = 0 (12e) SEL0101 = 0 (12a) 12f) SEL0110 = 0 ... (12g) SEL0111 = 0 ... (12h) SEL1000 = 1 ... (12i) SEL1001 = 1 ... (12j) SEL1010 = 0 ... (12k) SEL1011 = 0 ... (12l) SEL1100 = MM01100> MM11100 ... (12m) SEL1101 = 0 ... (12n) SEL1110 = MM01110> MM11110 ... (12o) SEL1111 = MM01111> MM11111 (12p) Further, a path metric is selected (Select) and the following update is performed.

[0043]

[0000] MT0000 = MM00000 *! SEL0000 + MM10000 * SEL0000 (13a) MT0001 = MM00001 *! SEL0001 + MM10001 * SEL0001 (13b) MT0011 = MM00011 *! SEL0011 + MM10011 * SEL0011 (13c) MT0110 = MM00110 (13d) MT0111 = MM00111 (13e) MT1000 = MM11000 (13f) MT1001 = MM11001 (13g) MT1100 = MM01100 *! SEL1100 + MM11100 * SEL1100 (13h) MT1110 = MM01110 *! SEL1110 + MM11110 * SEL1110 (13i) MT1111 = MM01111 *! SEL1111 + MM11111 * SEL1111 (13j) The last PMU6 is the selection signal SEL0000 to SEL1.
This is a circuit for updating the path memory as described below based on H.111.

[0044]

[0000] PM0000 [k] = PM0000 [k−1] *! SEL0000 + PM1000 [k-1] * SEL0000 (14a) PM0001 [k] = PM0000 [k-1] *! SEL0001 + PM1000 [k-1] * SEL0001 (14b) PM0011 [k] = PM0001 [k-1] *! SEL0011 + PM1001 [k-1] * SEL0011 (14c) PM0110 [k] = PM0011 [k-1] (14d) PM0111 [k] = PM0011 [k-1] (14e) PM1000 [k] = PM1100 [ k-1] (14f) PM1001 [k] = PM1100 [k-1] (14 g) PM1100 [k] = PM0110 [k-1] *! SEL1100 + PM1110 [k-1] * SEL1100 (14h) PM1110 [k] = PM0111 [k-1] *! SEL1110 + PM1111 [k-1] * SEL1110 (14i) PM0000 [k] = PM0111 [k-1] *! SEL1111 + PM1111 [k−1] * SEL1111 (14j) Note that the initial value PMjklm [0] of the path memory is m corresponding to the latest recording data in the definition of the state Sjklm.
Is 0 if 0 and 1 if 1.

[0045]

PM0000 [0] = 0 (15a) PM0001 [0] = 1 (15b) PM0011 [0] = 1 (15c) PM0110 [0] = 0 (15d) PM0111 [0] = 1 ... (15e) PM1000 [0] = 0 ... (15f) PM1001 [0] = 1 ... (15g) PM1100 [0] = 0 ... (15h) PM1110 [0] = 0 ... (15i) PM1111 [0] = 1 (15j) Here, NREG is defined as the number of stages of the path memory.

[0046]

(16) A sufficiently large number (for example, 32) is selected so that PM0000 [NREG-1] = PM0001 [NREG-1] =... = PM1111 [NREG-1] (16) Then, the oldest value of the path memory in any state is output as the output of the Viterbi decoding device,

[0047]

DET = PM0000 [NREG-1] (17)

As described above, according to the present invention, it is possible to easily realize a Viterbi decoder for an arbitrary equalization characteristic within the same range of the intersymbol interference length, and to provide an optimum Viterbi decoder according to the recording / reproducing system. The identification can be performed using the equalization characteristics, and it is possible to further contribute to the reduction of the error rate and the realization of the high density.

[0049]

As described above, according to the reference amplitude level setting device of the present invention, pa [0], p
a [1],..., pa [n−1], a DC component of the equalization characteristic is obtained, a convolution operation of the input recording data and the equalization characteristic is performed, and the DC component is subtracted from the result of the convolution operation. Thus, the configuration is such that the reference amplitude level is set. As a result, the reference amplitude level can be calculated efficiently only by inputting the parameters of the equalization characteristics, so that it is possible to identify using the optimum equalization characteristics for Viterbi decoding, thereby reducing the error rate. And high density can be realized.

Further, the Viterbi decoding device of the present invention is configured to perform Viterbi decoding based on a reproduced signal and a reference amplitude level corresponding to the input equalization characteristics. This allows
By simply inputting the parameters of the equalization characteristics, the reproduced signal and the reference amplitude level can be calculated efficiently, so that it is possible to identify using the optimum equalization characteristics, thereby reducing the error rate and increasing the density. It becomes possible to do.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a reference amplitude level setting device of the present invention.

FIG. 2 is a diagram showing a trellis diagram on which the present invention is based on Viterbi decoding with an intersymbol interference length of 3;

FIG. 3 is a diagram showing a trellis diagram on which the present invention is based on Viterbi decoding with an intersymbol interference length of 4;

FIG. 4 is a diagram showing a trellis diagram on which the present invention is based on Viterbi decoding with an intersymbol interference length of 5;

FIG. 5 is a diagram showing a reference amplitude level on which the present invention is based on Viterbi decoding with an intersymbol interference length of 3;

FIG. 6 is a diagram showing a reference amplitude level on which the present invention is based on Viterbi decoding with an intersymbol interference length of 4;

FIG. 7 is a diagram showing a reference amplitude level on which the present invention is based on Viterbi decoding with an intersymbol interference length of 5;

FIG. 8 is a diagram illustrating a configuration of a Viterbi decoding device.

FIG. 9 is a diagram showing a trellis diagram of Viterbi decoding with an intersymbol interference length of 3;

FIG. 10 is a diagram showing a trellis diagram of Viterbi decoding with an intersymbol interference length of 4;

FIG. 11 is a diagram showing a trellis diagram of Viterbi decoding with an intersymbol interference length of 5;

FIG. 12 is a diagram illustrating a reference amplitude level of Viterbi decoding with an intersymbol interference length of 3;

FIG. 13 is a diagram illustrating a reference amplitude level of Viterbi decoding with an intersymbol interference length of 4;

FIG. 14 is a diagram illustrating a reference amplitude level of Viterbi decoding with an intersymbol interference length of 5;

[Explanation of symbols]

10: Reference amplitude level setting device, 11: DC component calculation means, 12: Reference amplitude level setting means.

Claims (7)

[Claims]
1. An equalization characteristic PR having an intersymbol interference length of n
When performing Viterbi decoding using (pa [0], pa [1],..., Pa [n-1]), a reference amplitude level setting device that sets a reference amplitude level uses a pa [ 0], pa [1], ..., pa
DC component calculating means for obtaining a DC component of an equalization characteristic from [n-1]; performing a convolution operation on the input recording data and the equalization characteristic; and subtracting the DC component from the result of the convolution operation. And a reference amplitude level setting means for setting the reference amplitude level.
2. The DC component calculating means according to claim 1, wherein
The C component avr is defined as avr = (pa [0] + pa [1] +... + Pa [n−
2. The reference amplitude level setting device according to claim 1, wherein the DC component is obtained by calculation using an expression represented by the following expression: 1) / 2.
3. The method according to claim 2, wherein the reference amplitude level setting means includes a constant A
Based on the continuous recording data consisting of 0 or 1 ... state S ... ijk defined by ijklm
The reference amplitude level C ... iklkm of the state transition from l to the state S ... iklm is represented by: C ... iklk = A * (... + i * pa [4] + j * p
a [3] + k * pa [2] + l * pa [1] + m * pa
2. The reference amplitude level setting device according to claim 1, wherein the reference amplitude level is set by calculating using a formula represented by [0] -avr).
4. A Viterbi decoding device which receives a reproduced signal and a reference amplitude level and performs Viterbi decoding, wherein an equalization characteristic of the AD-converted reproduced signal z [k] is a PR ( eq [0], eq [1], ..., e
q [m-1]) and the equalization characteristics used for Viterbi decoding are PR (pa [0], pa [1],...,
pa [n-1]), the PR (eq
[0], eq [1],..., Eq [m-1])
(Pa [0], pa [1],..., Pa [n-1]).
.., pa [0], pa [1],..., pa [0], externally supplied pa [0], pa [1],.
DC component calculating means for obtaining a DC component of an equalization characteristic from [n-1]; performing a convolution operation on the input recording data and the equalization characteristic; and subtracting the DC component from the result of the convolution operation. And a reference amplitude level setting means for setting the reference amplitude level.
5. The reproduction signal calculation means according to claim 1, wherein
[K] is expressed as pb [k] = ... + z [k−2] * pr [2] + z [k−
5. The Viterbi decoding device according to claim 4, wherein the reproduction signal is obtained by calculation using an expression represented by the following formula: 1] * pr [1] + z [k] * pr [0].
6. The DC component calculating means according to claim 5, wherein
The C component avr is defined as avr = (pa [0] + pa [1] +... + Pa [n−
The Viterbi decoding device according to claim 4, wherein the DC component is obtained by calculation using an expression represented by 1)) / 2.
7. The method according to claim 1, wherein the reference amplitude level setting means includes a constant A
Based on the continuous recording data consisting of 0 or 1 ... state S ... ijk defined by ijklm
The reference amplitude level C of the state transition from l to the state S ... jklm, C ... iklkm, C ... iklk = A * (... + i * pa [4] + j * p
a [3] + k * pa [2] + l * pa [1] + m * pa
The Viterbi decoding device according to claim 4, wherein the reference amplitude level is set by calculating using an expression represented by [0] -avr).
JP34080799A 1999-11-30 1999-11-30 Peference amplitude level setting device and viterbi decoder Pending JP2001156652A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7852729B2 (en) 2004-10-21 2010-12-14 Hitachi, Ltd. Optical disc apparatus with adjustable constraint length PRML
CN104508743A (en) * 2012-09-25 2015-04-08 甲骨文国际公司 Matched pattern signal decoding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7852729B2 (en) 2004-10-21 2010-12-14 Hitachi, Ltd. Optical disc apparatus with adjustable constraint length PRML
CN104508743A (en) * 2012-09-25 2015-04-08 甲骨文国际公司 Matched pattern signal decoding
CN104508743B (en) * 2012-09-25 2017-09-05 甲骨文国际公司 Matched patterns signal is decoded

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