JP2001156637A - Analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an analog/digital converter where a voltage level is hardly deviated from an optimum value and the precision is hardly deteriorated in the case of processing an analog signal at analog/digital conversion. SOLUTION: The analog/digital converter consists of transistors(TRs) Mn8 (8) and Mn10 (10) connected in symmetry with TRs Mn7 (7) Mn9 (9), a TR Mn6 (6) connected to collectors of the TRs Mn7 (7), Mn8 (8), a resistor 35 connected to a collector of the TRs Mn7 (7), a resistor 31 connected to an emitter of the Mn9 (9), a resistor 37 connected to a collector of the Mn8 (8), a resistor 33 connected to an emitter of the Mn10 (10), a node 38 connected to the resistors 31, 33, and a switch 1 connected to resistors 35, 37.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an A / D converter (analog / digital converter, hereinafter referred to as an A / D converter),
In particular, the present invention relates to a subranging A / D converter using a folding and interpolation architecture.

[0002]

[Prior art]

A sub-ranging A / D converter performs A / D conversion in two stages, upper and lower. FIG. 3 is a block diagram of a conventional unified subranging A / D converter. Referring to FIG. 3, this A / D converter is a sub A / D converter sADC3 having a resolution of 5 + α bits.
A / D conversion of upper 5 bits and lower 5 bits is performed by repeatedly using 01. Here, the α bit is a redundant bit for error correction.

FIG. 4 is a timing chart of a conventional unified subranging type A / D converter. Referring to FIG. 4, the operation of the A / D converter is performed once by a total of three operations of sampling, upper comparison, and lower comparison in each of sampling period SA, upper comparison period CC, and lower comparison period FC. A / D conversion is performed. During the sampling period SA, the A / D converter captures an analog input signal and holds the value of the analog signal captured at the end of the sampling period SA.

In the upper comparison period CC, the held analog signal and the upper reference voltage Vrci (i = 1, 2,..., 2
電 圧 (5 + α) -1) is compared with the voltage level, and a digital code corresponding to the result is output. The bus switch 303 switches the sub A / D converter sA during the upper comparison period CC.
The output of DC 301 is connected to delay circuit 305. This code is a digital code in which the upper 5 bits include an α-bit redundant bit, but the redundant bit is ignored and only the upper 5 bits of the digital code are accumulated in the delay circuit 305.

In the lower comparison period FC, the held analog signal and the lower reference voltage Vrfj (i = 1, 2,..., 2
電 圧 (5 + α) -1) is compared with the voltage level, and a digital code corresponding to the result is output. The bus changeover switch 303 switches the sub A / D converter sA during the lower comparison period FC.
The output of the DC 301 is directly connected to the error correction circuit 307. This code includes an α-bit redundant bit for error correction in the lower 5 bits.

The error correction circuit 307 uses the α-bit redundant bit signal of the lower comparison result to generate a delay
The error correction is performed on the upper 5 bits of the digital code stored in the memory, and the result and the lower 5 bits of the digital code are output at the same timing. This output is a 10-bit digital code.

Next, FIG. 5 shows a sub A / D converter sADC30.
1 is a block diagram of a folding and interpolation architecture that is a specific example of FIG.

Referring to FIG. 5, this A / D converter has an A / D converter.
Since D conversion is performed in two stages, upper and lower, each A
The voltage range of the reference voltage used during the / D conversion is different. Therefore, a variable gain preamplifier is used.

FIG. 6 is a circuit diagram of a conventional variable gain preamplifier. Referring to FIGS. 6 and 5, the gain variable preamplifier switches the gain at the time of the upper and lower A / D conversion. As a result, the voltage amplitude transmitted to the folding amplifier group 501 and the interpolation circuit 503 at the subsequent stage at the time of comparison between the upper and lower parts has an optimum value, and analog signal processing is performed.

The operation of the variable gain preamplifier is shown in FIG.
SW1 controlled by the control signal Φcnt of
In (711), the gain is adjusted. Switch SW1 (7
11) is turned off when the control signal Φcnt is “H” and turned on when it is “L”.

Further, since the control signal Φcnt becomes “L” in the upper comparison period CC of the timing chart of FIG. 4, the switch SW1 (711) is turned on. Therefore, the gain of the variable gain preamplifier is
The transconductance gm of n2 (702) or Mn3 (703) and the resistances Rc731, 733 and Rf7
35,737 and the drain-source resistance Rdsp of the transistor Mp4 (704) or Mp5 (705).
With the resistance value R1 due to the parallel connection of

That is, the gain GC is as follows: GC = gm × R1 (1) R1 = 1 / (1 / Rc + 1 / Rf + 1 / Rdsp) (2)

In the lower comparison period FC, the control signal Φcnt becomes “H”, so that the switch SW1 (71
1) is in the OFF state. Therefore, the gain of the variable gain preamplifier is determined by the transconductance gm of the transistor Mn2 (702) or Mn3 (703), the resistance Rf735,737, and the transistor Mp4 (70).
4) or the product of the resistance Rdsp of the parallel connection of the drain-source resistance Rdsp of Mp5 (705).

That is, the gain GF is given by GC = gm × R2 (3) R2 = 1 / (1 / Rf + 1 / Rdsp) (4)

Therefore, the upper / lower A / D
At the time of conversion, a voltage amplitude is obtained by analog signal processing of the folding amplifier group 501 and the interpolation circuit 503.

In the variable gain preamplifier shown in FIG. 6, the common voltage level of the differential input signals Vinp and Vinn affects the output voltage amplitude. That is, when the differential input signal is expressed by Vinp = Vinn + ΔV (5), the common voltage level of the input signal is Vcmn.
Vcmn = (Vinp + Vinn) / 2 (6) The output voltage amplitude ΔVout of the variable gain preamplifier is ΔVout = ΔV × Gc + ΔVcmn × Ac (when comparing high order) = ΔV × GF + ΔVcmn × Ac (when comparing low order) due to the change ΔVcmn of (6). 7)

In the conventional variable gain preamplifier, when the common voltage level Vcmn of the input signal changes, the drain voltage level Vdn of the current source transistor Mn1 (701) of the variable gain preamplifier varies as follows: Vdn = Vcmn-Vthin-Vdsatin (8) . Here, Vthin and Vdsatin are respectively the transistors Mn2 (70) of the variable gain preamplifier.
2), Mn3 (703) threshold and saturation voltage.

In the current source transistor, the drain-source current Ids changes according to the change in the drain voltage.
The change in the current value causes the transistor Mp4 (70
4), a change occurs in the drain-source current of Mp5 (705), and as a result, the drain-source voltage changes. This change amount corresponds to ΔVcmn × Ac in equation (7). This affects the output voltage amplitude ΔVout.

For example, the common voltage level Vc of the input signal
When mn decreases by ΔVcmn, the drain voltage level Vdn of the current source transistor Mn1 (701) becomes ΔVc
mn, and the drain-source current Ids decreases by ΔIds = βn / 2 × (Vbn−Vthn) ＾ 2 × (ΔVcmn / Van) (9) βn is the current source transistor Mn1 (70
Vthn is a threshold value, Van is an early voltage, and Vbn is a bias voltage.

As a result, the transistor Mp4 (70
4), drain-source current Id of Mp5 (705)
sp also decreases, and the total decrease of the two drain-source currents becomes ΔIds of the drain-source current decrease of the current source transistor Mn1.

In response to the decrease in the drain-source current Idsp, the transistors Mp4 (704) and Mp5 (7
The drain-source voltage Vdsp of 05) also decreases. The current value between the drain and source at that time and the drain
The source-to-source voltage value is balanced so as to satisfy an approximate expression of Idsp = βp / 2 × (| Vbp−Vdd | − | Vthp |) ＾ 2 × (1 + Vdsp / Vap) (10) βp is a value determined by the shape of the gate electrodes of the transistors Mp4 (704) and Mp5 (705), Vthp is a threshold value, and Va
p is an early voltage, and Vbp is a bias voltage.

From equation (10), Vbp, Vdd, Vth
Since p and Vap are constant, the drain-source current I
With respect to the decrease Δdsp of dsp, the decrease ΔVdsp of the drain-source voltage Vdsp is as follows: ΔVdsp = ΔIdsp × Vap / (βp / 2 × (| Vbp−Vdd | − | Vthp |) ｐ2) (11) Becomes

That is, the voltage level difference between the differential input signals is ΔV
, The output voltage amplitude changes by ΔVcmn × Ac even if the common voltage level Vcmn changes.

[0025]

As described above, when analog signal processing is performed at the time of A / D conversion in the conventional folding and interpolation circuit, the voltage amplitude deviates from an optimum value, and the accuracy deteriorates. There is a problem that the accuracy of the entire / D converter is reduced.

[0026]

In the A / D converter according to the present invention, a terminal to which a first constant potential is applied is connected to a second current electrode, and a bias voltage is applied to a control electrode. A transistor, a second transistor having a second current electrode connected to a first current electrode of the first transistor, and a first differential input signal applied to a control electrode; and a first transistor of the first transistor. A second current electrode is connected to the current electrode of the third transistor, and a second differential input signal is applied to the control electrode; and a first transistor is connected to the first current electrode of the second transistor. An output terminal, a second output terminal connected to the first current electrode of the third transistor, a first resistor having one terminal connected to the first current electrode of the second transistor, One terminal is connected to the first current electrode of the third transistor A second resistor, a switch provided between the other terminal of the first resistor and the other terminal of the second resistor, and one terminal connected to one terminal of the first resistor A third resistor, a fourth resistor whose one terminal is connected to one terminal of the second resistor, and a fourth resistor connected to the other terminal of the third resistor and connected to the other terminal of the fourth resistor And a first current electrode connected to one terminal of a third resistor, a terminal to which a second constant potential is applied is connected to the second current electrode, and a control electrode is connected to the node. A fourth transistor, a first current electrode is connected to one terminal of a fourth resistor, a terminal to which a second constant potential is applied is connected to a second current electrode, and a control electrode is connected to a node. And a fifth variable transistor.

A terminal to which a first constant potential is applied is connected to the second current electrode, and a first transistor to which a bias voltage is applied to the control electrode and a first current electrode of the first transistor to the first transistor. A second transistor to which a second current electrode is connected and to which a first differential input signal is applied to a control electrode; and a second current electrode to which a first current electrode of the first transistor is connected to control a second current electrode. A third transistor having a second differential input signal applied to the electrode, a first output terminal connected to the first current electrode of the second transistor, and a first current electrode of the third transistor , A first resistor having one terminal connected to the first current electrode of the second transistor, and one terminal connected to the first current electrode of the third transistor. A second resistor connected;
A third terminal in which one terminal is connected to one terminal of the first resistor;
, A fourth resistor having one terminal connected to one terminal of the second resistor, and an open / close switch provided between the other terminal of the third resistor and the other terminal of the fourth resistor. A first node connected to one terminal of the third resistor, a second node connected to one terminal of the fourth resistor, and a first current electrode connected to the first node. Connected, a terminal to which a second constant potential is applied is connected to the second current electrode, and the control electrode is connected to the first current electrode.
A fourth transistor connected to the second node, a first current electrode connected to the second node, a terminal to which a second constant potential is applied connected to the second current electrode, and a control electrode connected to the second node. A fifth transistor connected to the second node, a first current electrode connected to the second node, and a second transistor connected to the second current electrode.
A transistor to which a terminal to which a constant potential is applied is connected, a control electrode is connected to a first node, a first current electrode is connected to a first node, and a second current electrode is connected to a second node. And a seventh transistor having a control electrode connected to the second node and a control electrode connected to the second node.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, the present invention will be described. FIG. 1 is a circuit diagram of a variable gain preamplifier of an A / D converter according to the first embodiment. Referring to FIG. 1, in variable gain preamplifier 100, a GND terminal is connected to an emitter, and a transistor Mn6 (6) to which a bias voltage Vbn is applied to a base, and an emitter is connected to a collector of transistor Mn6 (6). , A transistor Mn having a base to which a differential input signal Vinp is applied
7 (7), and a transistor Mn8 (8) having an emitter connected to the collector of the transistor Mn6 (6) and having a base to which the differential input signal Vinn is applied.

The output terminal OUT1 connected to the collector of the transistor Mn7 (7) and the transistor Mn7
8 (8), an output terminal OUT2 connected to the collector,
A resistor Rc35 having one terminal connected to the collector of the transistor Mn7 (7), a resistor Rc37 having one terminal connected to the collector of the transistor Mn8 (8), and the other terminal of the resistor Rc35 and the other of the resistor Rc37. A switch SW1 (1) provided between the terminal and a resistor Rf31 having one terminal connected to one terminal of the resistor Rc35.
And a resistor Rf33 having one terminal connected to one terminal of the resistor Rc37.

A node N connected to the other terminal of the resistor Rf31 and connected to the other terminal of the resistor Rf33.
And the collector is connected to one terminal of the resistor Rf31,
A transistor Mp9 (9) having an emitter connected to the Vdd terminal and a base connected to the node N, a collector connected to one terminal of the resistor Rf33, an emitter connected to the Vdd terminal, and a base connected to the node N. Transistor Mp10 (10).

The gain is adjusted by the switch SW1 (1) controlled by the control signal Φcnt. The switch SW1 (1) is turned off when the control signal φcnt is “H”.
It becomes the F state, and becomes the ON state when it is "L".

Further, since the control signal Φcnt becomes “L” in the upper comparison period CC in the timing chart of FIG. 4, the switch SW1 (1) is turned on. Therefore, the gain of the variable gain preamplifier 100 is determined by the transconductance gm of the transistor Mn7 (7) or Mn8 (8), the resistors Rc35, 37, Rf31, 33 and the transistor Mp9 (9) or Mp10 (10).
With the resistance value R11 of the parallel connection of the drain-source resistance Rdsp.

That is, the gain G1C is as follows: G1C = gm × R11 (12) R11 = 1 / (1 / Rc + 1 / Rf + 1 / Rdsp) (13)

In the lower comparison period FC, the control signal Φcnt becomes “H”, so that the switch SW1 (1) is turned off. Therefore, the variable gain preamplifier 10
The gain of 0 is determined by the transistor Mn7 (7) or Mn7
8 (8) and the resistance Rf3
1, 33 and the transistor Mp9 (9) or Mp1
It is expressed by the product of the resistance Rdsp of the parallel connection of the drain-source resistance Rdsp of 0 (10).

That is, the gain G1F is as follows: G1F = gm × R12 (14) R12 = 1 / (1 / Rf + 1 / Rdsp) (15)

In the variable gain preamplifier 100, the common voltage level Vcmn of the input signal changes, the drain voltage level Vd of the current source transistor Mn6 (6) of the variable gain preamplifier changes, and the drain-source current I
When ds changes, this change in the current value causes a change in the drain-source current of the transistors Mp9 (9) and Mp10 (10), but also changes the gate potential of the transistors. This change in gate potential acts to reduce the change in drain-source voltage caused by the change in drain-source current.

For example, the current source transistor Mn6 (6)
The drain-source current Ids of the transistors Mp9 (9) and Mp10 (10) also decreases. The drain-source voltage tends to decrease so as to balance this current decrease. At that time, since the potential of the node N38 rises, the transistor M
The potentials of the gate voltages of p9 (9) and Mp10 (10) increase. As a result, the drain-source current of the transistor decreases, so that the drain-source voltage does not further decrease.

At this time, the drain-source current value and the drain-source voltage value are as follows: Idsp = βp / 2 × (| VN−Vdd | − | Vthp |) ＾ 2 × (1 + Vdsp / Vap) (16) Are balanced so as to satisfy the approximation formula. βp is a value determined by the shapes of the gate electrodes of the transistors Mp9 (9) and Mp10 (10), Vthp is a threshold value, Vap is an early voltage, and VN is a voltage level of the node N38.

From the equation (16), the drain-source current I
The change of the value of VN with respect to the decrease ΔIdsp of dsp is 2
Since the power has an influence, the change in VN acts more greatly than the change in drain-source voltage Vdsp. Therefore,
The decrease ΔVdsp of the drain-source voltage Vdsp is smaller than that of the conventional circuit configuration.

As a result, the output voltage amplitude ΔVout of the variable gain preamplifier 1 caused by the change ΔVcmn of the common voltage level Vcmn of the input signal is as follows: ΔVout = ΔV × G1c + ΔVcmn × Ac (when comparing upper ranks) = ΔV × G1F + ΔVcmn × Ac (lower comparisons) (Time) Ac in the right term of (17) becomes smaller.

According to the first embodiment, even when the level difference between the differential input signals is ΔV and the common voltage level Vcmn changes, the amount of change in the output voltage amplitude is small. Therefore, A /
When analog signals are processed by the folding amplifier group and the interpolation circuit at the time of D conversion, the voltage amplitude is kept at an optimum value, and the deterioration of accuracy is improved.

Embodiment 2 FIG. 2 shows a second embodiment.
FIG. 2 is a circuit diagram of a variable gain preamplifier of an A / D converter according to the first embodiment. Referring to FIG. 2, variable gain preamplifier 11
0 is a transistor Mn11 (1) whose emitter is connected to the GND terminal and whose base is supplied with the bias voltage Vbn.
1), a transistor Mn12 (12) having an emitter connected to the collector of the transistor Mn11 (11) and a differential input signal Vinp applied to the base, and an emitter connected to the collector of the transistor Mn11 (11);
A transistor Mn13 (13) to which the differential input signal Vinn is applied is provided on the base.

The output terminal OUT1 connected to the collector of the transistor Mn12 (12) and the output terminal OU connected to the collector of the transistor Mn13 (13)
T2, a resistor Rf55 having one terminal connected to the collector of the transistor Mn12 (12),
A resistor Rf57 having one terminal connected to the collector of n13 (13), a resistor Rc51 having one terminal connected to one terminal of resistor Rf55, and a resistor Rf5 having one terminal connected to one terminal of resistor Rf55.
7 and a resistor Rc53 connected to one of the terminals.

Further, the other terminal of the resistor Rc51 and the resistor Rc
switch SW1 provided between the other terminal of c53
(71), a node N1 connected to one terminal of the resistor Rc51, and a node N2 connected to one terminal of the resistor Rc53.

A collector is connected to node N1,
A transistor Mp14 (14) whose emitter is connected to the Vdd terminal and whose base is connected to the node N1, and a transistor Mp14 whose collector is connected to the node N2, whose emitter is connected to the Vdd terminal and whose control electrode is connected to the node N2.
p15 (15), the collector is connected to node N2,
The Vdd terminal is connected to the emitter, and the control electrode is connected to the node N1.
And a transistor Mp17 (17) having a collector connected to the node N1, an emitter connected to the Vdd terminal, and a control electrode connected to the node N2.

The gain is adjusted by the switch SW1 (71) controlled by the control signal Φcnt. The switch SW1 (71) is turned off when the control signal Φcnt is “H”, and turned on when the control signal Φcnt is “L”.

Further, since the control signal Φcnt becomes “L” during the upper comparison period CC in the timing chart of FIG. 4, the switch SW1 (71) is turned on. Therefore, the gain of the variable gain preamplifier 110 depends on the transconductance gm of the transistor Mn12 (12) or Mn13 (13) and the resistances Rc51, 53, and Rf5.
5, 57 and the combined resistance of the drain-source resistance of the transistors Mp14 (14) and Mp17 (17) between the terminals N1 (58) and Vdd or the node N2 (5
2) a transistor Mp15 (15) between the Vdd terminal and
It is represented by the product of the resistance between the drain-source resistance of Mp16 (16) and the combined resistance Rdsp 'and the resistance value R21 by parallel connection.

That is, the gain G2C is as follows: G2C = gm × R21 (18) R21 = 1 / (1 / Rc + 1 / Rf + 1 / Rdsp ‘) (19)

Since the control signal .PHI.cnt becomes "H" in the lower comparison period FC, the switch SW1 (71)
Is turned off. Therefore, the variable gain preamplifier 1
The gain of 10 is determined by the transconductance gm of the transistor Mn12 (12) or Mn13 (13),
Transistors Mp14 (14) and Mp17 (1) between the resistors Rf55 and Rf57 and the node N1 (58) to the Vdd terminal.
7) The combined resistance of the drain-source resistance or the transistor Mp15 between the node N2 (52) and the Vdd terminal.
(15), expressed by the product of the resistance R22 of the parallel connection of the combined resistance Rdsp 'of the resistance between the drain and the source of Mp16 (16).

That is, the gain G2F is as follows: G2F = gm × R22 (20) R22 = 1 / (1 / Rf + 1 / Rdsp ‘) (21)

In the variable gain preamplifier 110, the common voltage level Vcmn of the input signal is changed, and the current source transistor Mn11 (1
When the drain voltage level Vd of 1) changes and the drain-source current Ids changes, the transistors Mp14 (14) and Mp15 (1)
5) Although the current between the drain and the source of Mp16 (16) and Mp17 (17) changes, the gate potential of each transistor also changes. This change in gate potential acts to reduce the change in drain-source voltage caused by the change in drain-source current.

For example, when the drain-source current Ids of the current source transistor Mn11 decreases, the transistors Mp14 (14), Mp15 (15), Mp16 (1
6), the drain-source current of Mp17 (17) also decreases. The drain-source voltage tends to decrease so as to balance this current decrease. Then node N1
(58), the potential of N2 (52) rises, the transistors Mp14 (14), Mp15 (15), Mp16
(16) The potential of the gate voltage of Mp17 (17) increases. As a result, the drain-source current of the transistor decreases, so that the drain-source voltage does not further decrease.

The current value between the drain and the source and the voltage value between the drain and the source at this time are Idsp = βp / 2 × (| VN1,2-Vdd | − | Vthp |) ｐ2 × (1 + Vdsp / Vap) ( 22) is balanced so as to satisfy the approximate expression. βp is the transistor Mp14 (14), Mp15 (15), M
The values determined by the shapes of the gate electrodes p16 (16) and Mp17 (17), Vthp is the threshold value, Vap is the early voltage, and VN1 and VN1 are the voltage levels of the nodes N1 (58) and N2 (52).

From equation (22), the drain-source current I
Since the square of the change in the value of VN1,2 affects the decrease ΔIdsp of dsp, the drain-source voltage Vd
The change in VN1,2 has a greater effect than the change in sp. Therefore, the decrease ΔVdsp of the drain-source voltage Vdsp is smaller than that of the conventional circuit configuration.

As a result, the output voltage amplitude ΔVout of the variable gain preamplifier 1 caused by the change ΔVcmn of the common voltage level Vcmn of the input signal is as follows: ΔVout = ΔV × G2c + ΔVcmn × Ac (when comparing upper ranks) = ΔV × G2F + ΔVcmn × Ac (lower comparisons) (Time) Ac in the right term of (23) becomes smaller.

In the variable gain preamplifier 110, the current flowing through each of the nodes N1 (58) and N2 (52) becomes substantially constant. That is, if the differential input signal is Vinp> Vi
nn, the transistor Mn12 (12)
And drain-source current Ids of Mn13 (13)
In12 and 13 are such that Idsin12> Idsin13.

As a result, the voltage level of node N1 (58) decreases by ΔVn, and the voltage level of node N2 (52) increases by ΔVn. As a result, the transistor Mp
14 (14), the drain-source current increases by ΔIdsp ′, and the transistor M
Since the gate voltage of p15 (15) increases, the drain
The source-to-source current decreases by ΔIdsp ″.

However, since the gate of the transistor Mp16 (16) is connected to the node N2 (52), the drain-source current is reduced by ΔIdsp ″, and the gate of the transistor Mp17 (17) is connected to the node N1 (58).
, The drain-source current is ΔId
increase by sp ′.

Therefore, nodes N1 (58) and N2 (5
The change in the value of the current flowing through 2) is ΔIdsp′−ΔId, respectively.
sp ″, ΔIdsp ″ −ΔIdsp ′. ΔI
Since dsp ′ and ΔIdsp ″ have substantially the same value, the change in the value of the current flowing through the nodes N1 (58) and N2 (52) is almost zero.

The nodes N1 (58) and N2 (5
The fact that the current does not change even if the voltage of 2) changes indicates that the transistor Mp14 between the node N1 (58) and the Vdd terminal.
(14), the combined resistance of the drain-source resistance of Mp17 (17) or the combined resistance Rdsp ′ of the drain-source resistance of the transistors Mp15 (15) and Mp16 (16) between the node N2 (52) and the Vdd terminal. It is equivalent to being quite large. That is, the combined resistance Rdsp 'has a larger value than Rc51, Rc53 and Rf55, 57.

Thus, the variable gain preamplifier 110
Approximately, the gain is G2C ′ = gm × R21 ′ (24) R21 ′ = 1 / (1 / Rc + 1 / Rf) (25) (At the time of lower-order comparison) G2F ′ = gm × Rf (26) Becomes

According to the second embodiment, the first embodiment
Even if the level difference between the differential input signals is ΔV and the common voltage level Vcmn changes, the amount of change in the output voltage amplitude is small. Therefore, when analog signal processing is performed by the folding amplifier group and the interpolation circuit at the time of A / D conversion, the voltage amplitude is maintained at an optimum value, and accuracy deterioration is improved.

The gain at the time of each of the upper and lower comparisons is represented by R
Since the control can be performed by the design values of c and Rf, the setting of the gain is easier than in the first embodiment.

[0064]

According to the A / D converter according to the present invention, a terminal to which a first constant potential is applied is connected to a second current electrode and a bias voltage is applied to a control electrode; A second current electrode is connected to a first current electrode of the one transistor, and a second transistor to which a first differential input signal is applied to a control electrode, and a second current electrode is connected to a first current electrode of the first transistor. A third transistor to which a second current electrode is connected and a second differential input signal is applied to a control electrode; a first output terminal connected to a first current electrode of the second transistor; A second output terminal connected to the first current electrode of the third transistor; a first resistor having one terminal connected to the first current electrode of the second transistor; A second resistor having one terminal connected to the first current electrode. When a switch provided between the first other resistor terminal and the other terminal of the second resistor,
A third terminal in which one terminal is connected to one terminal of the first resistor;
, One terminal connected to one terminal of the second resistor, a fourth resistor connected to the other terminal of the third resistor, and connected to the other terminal of the fourth resistor A node, a first current electrode connected to one terminal of a third resistor, a terminal to which a second constant potential is applied connected to a second current electrode,
A fourth transistor having a control electrode connected to the node;
A first current electrode is connected to one terminal of the fourth resistor;
Since the second current electrode is connected to the terminal to which the second constant potential is applied, and the control electrode is provided with a fifth transistor connected to the node, the level difference of the differential input signal is ΔV Therefore, even if the common voltage level Vcmn changes, the amount of change in the output voltage amplitude becomes small. Therefore, when analog signal processing is performed by the folding amplifier group and the interpolation circuit at the time of A / D conversion, the voltage amplitude is maintained at an optimum value, and accuracy deterioration is improved.

Further, a terminal to which a first constant potential is applied is connected to the second current electrode, and a first transistor to which a bias voltage is applied to a control electrode and a first current electrode of the first transistor are connected to a first transistor. A second transistor to which a second current electrode is connected and to which a first differential input signal is applied to a control electrode; and a second current electrode to which a first current electrode of the first transistor is connected to control a second current electrode. A third transistor having a second differential input signal applied to the electrode, a first output terminal connected to the first current electrode of the second transistor, and a first current electrode of the third transistor , A first resistor having one terminal connected to the first current electrode of the second transistor, and one terminal connected to the first current electrode of the third transistor. A second resistor connected;
A third terminal in which one terminal is connected to one terminal of the first resistor;
, A fourth resistor having one terminal connected to one terminal of the second resistor, and an open / close switch provided between the other terminal of the third resistor and the other terminal of the fourth resistor. A first node connected to one terminal of the third resistor, a second node connected to one terminal of the fourth resistor, and a first current electrode connected to the first node. Connected, a terminal to which a second constant potential is applied is connected to the second current electrode, and the control electrode is connected to the first current electrode.
A fourth transistor connected to the second node, a first current electrode connected to the second node, a terminal to which a second constant potential is applied connected to the second current electrode, and a control electrode connected to the second node. A fifth transistor connected to the second node, a first current electrode connected to the second node, and a second transistor connected to the second current electrode.
A sixth transistor having a terminal to which a constant potential is applied and a control electrode connected to the first node; a first current electrode connected to the first node; and a second transistor connected to the second current electrode. Is connected to a terminal to which a constant potential is applied, and a control electrode is provided with a seventh transistor connected to the second node. Therefore, the level difference of the differential input signal is ΔV and the common voltage level is ΔV. Even if Vcmn changes, the amount of change in the output voltage amplitude decreases. Therefore, when performing analog signal processing by the folding amplifier group and the interpolation circuit at the time of A / D conversion, the voltage amplitude is held at an optimum value, and the deterioration of accuracy is improved.

Also, the gain at the time of each of the upper / lower comparison is represented by R
Since the control can be performed by the design values of c and Rf, the setting of the gain is further facilitated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a variable gain preamplifier of an A / D converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a variable gain preamplifier of an A / D converter according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional microcomputer.

FIG. 4 shows a conventional unified subranging type A / D.
5 is a timing chart of the converter.

FIG. 5 is a block diagram of a conventional folding and interpolation architecture.

FIG. 6 is a circuit diagram of a conventional variable gain preamplifier.

[Explanation of symbols]

1 SW16 Mn67 Mn78 Mn89 Mp9 10 Mp1
0 11 Mn 11 12 Mn
12 13 Mn13 14 Mp14 15 Mp
15 16 Mp16 17 Mp
17 31 Rf 33 Rf 35 Rc 37 Rc 38 N 55 Rf 57 Rf 51 Rc 53 Rc 58 N1 52 N2 71 SW1

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takahiro Miki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term in Mitsubishi Electric Corporation (reference) 5J022 AA14 BA01 CA08 CB06 CC01 CD03 CE01 CF02 CF05 5J100 AA02 AA20 BA05 BB02 BB08 BB16 BC04 CA12 CA28 EA02

Claims (2)

[Claims] A first transistor to which a terminal to which a first constant potential is applied is connected to a second current electrode and a bias voltage is applied to a control electrode; and a first current electrode of the first transistor A second current electrode is connected to the control electrode, and a second transistor to which a first differential input signal is applied to the control electrode; and a second current electrode is connected to the first current electrode of the first transistor. A third transistor to which a second differential input signal is applied to the control electrode; a first output terminal connected to a first current electrode of the second transistor; and a third transistor of the third transistor. A second output terminal connected to the first current electrode; a first resistor having one terminal connected to the first current electrode of the second transistor; and a first current of the third transistor. A second resistor having one terminal connected to the electrode A switch provided between the other terminal of the first resistor and the other terminal of the second resistor; and a third switch having one terminal connected to one terminal of the first resistor. A fourth resistor having one terminal connected to one terminal of the second resistor; a fourth resistor connected to the other terminal of the third resistor, and a fourth terminal connected to the other terminal of the fourth resistor. A node to be connected, a first current electrode is connected to one terminal of the third resistor, a terminal to which a second constant potential is applied is connected to a second current electrode, and a control electrode is connected to the node. A fourth transistor to be connected, a first current electrode connected to one terminal of the fourth resistor, a terminal to which a second constant potential is applied connected to a second current electrode, and a control electrode connected A sub-range including a variable gain preamplifier having a fifth transistor connected to the node; Grayed-type A / D converter. 2. A first transistor to which a terminal to which a first constant potential is applied is connected to a second current electrode, and a bias voltage is applied to a control electrode; and a first current electrode of the first transistor. A second current electrode is connected to the control electrode, and a second transistor to which a first differential input signal is applied to the control electrode; and a second current electrode is connected to the first current electrode of the first transistor. A third transistor to which a second differential input signal is applied to the control electrode; a first output terminal connected to a first current electrode of the second transistor; and a third transistor of the third transistor. A second output terminal connected to the first current electrode; a first resistor having one terminal connected to the first current electrode of the second transistor; and a first current of the third transistor. A second resistor having one terminal connected to the electrode A third resistor having one terminal connected to one terminal of the first resistor; a fourth resistor having one terminal connected to one terminal of the second resistor; A switch provided between the other terminal of the third resistor and the other terminal of the fourth resistor; a first node connected to one terminal of the third resistor; A second node connected to one terminal of the resistor; a first current electrode connected to the first node; a terminal to which a second constant potential is applied connected to the second current electrode; A fourth transistor having an electrode connected to the first node; a first current electrode connected to the second node; and a second current electrode connected to a terminal to which a second constant potential is applied. A fifth transistor having a control electrode connected to the second node, and a first current electrode connected to the second node. A sixth transistor, which is connected to a second current electrode, a terminal to which a second constant potential is applied is connected to a second current electrode, and a control electrode is connected to the first node; A variable gain preamplifier having a seventh transistor connected to a first node, a terminal to which a second constant potential is applied to a second current electrode, and a control electrode connected to the second node. A subranging type A / D converter provided.