JP2001154930A - Lsi device, bus bridge device and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily perform debugging at the time of system development and factor analysis at the time of error generation, etc., without newly developing a dedicated analyzer. SOLUTION: A PCI-PCI bridge is constituted of two physically different controllers that are a primary PCI serial transfer controller 15 disposed on the side of a PC main body 100 and a secondary PCI serial transfer controller 35 disposed on the side of a docking station 200. Both controllers are provided with a damping function for a reception word and the damping function for a transmission word and information matched with a prescribed sampling condition in the information transmitted and received by serial transfer is automatically sampled and stored in registers inside the controllers. By providing the damping function in an LSI controller itself in such a manner, the debugging at the time of the system development and the factor analysis at the time of the error generation, etc., are easily realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI device, a bus bridge device, and a computer system, and more particularly to an LSI device and a bus improved so that debugging at the time of development and analysis of a factor at the time of occurrence of an error can be easily performed. The present invention relates to a bridge device and a computer system.

[0002]

2. Description of the Related Art In recent years, various notebook-type personal computers (hereinafter referred to as notebook PCs) which are easy to carry and can be operated by a battery have been developed.
Some notebook PCs are configured so that they can be attached to an expansion unit as needed to extend their functions. In order for the resources of the expansion unit to be effectively used from the notebook PC main body, it is important to connect the bus of the notebook PC main body to the bus in the expansion unit. With this bus connection, devices on the bus in the expansion unit can be handled in the same way as devices in the notebook PC main body.

In many personal computers, a PC
An I bus (Peripheral Component Interconnect Bus) is used. Therefore, the bus connection between the notebook PC body and the expansion unit is performed by providing docking connectors having a number of pins corresponding to the number of signal lines of the PCI bus on the notebook PC body side and the expansion unit side, respectively. This is usually done by physically connecting the two PCI buses via a connector.

However, this configuration requires a large area for mounting the docking connector.
This is disadvantageous in reducing the size and thickness of the C body. Further, since the connector mounting positions on the notebook PC main body side and the expansion unit side must be matched, the physical housing structure is restricted when developing a new product.

[0005]

Therefore, recently, a PCI bus on the notebook PC main body side and a PCI bus on the extension unit side have been recently developed.
A PCI-PCI bridge connecting to the bus is constituted by first and second physically different controllers;
A technique for transmitting and receiving information between the controllers by serial transfer has been proposed by the present applicant (Japanese Patent Application No. 11-183919). In this case, the first and second controllers are separately arranged on the notebook PC main body side and the extension unit side. Note PC
Data necessary for transmitting a transaction from the PCI bus on the main unit side to the PCI bus on the expansion unit side is converted from parallel data to serial data by the first controller, and then converted via a serial transmission line such as a cable. 2 controller. Then, in the second controller, conversion from serial data to parallel data is performed, and a transaction is developed on the PCI bus on the extension unit side. Thereby, note P
It is possible to connect the C body and the extension unit with a thin cable having a small number of signal lines.

By the way, as described above, a single PCI-PC
When the I-bridge is composed of two physically different first and second controller LSIs, it is necessary to reliably transfer data between these two controller LSIs in order to maintain the reliability of the system operation. Becomes Furthermore, since data transfer between two controller LSIs needs to be performed at high speed via a dedicated serial transmission line, the development of these controller LSIs requires the use of a serial transmission line for debugging. It is important to analyze how the transmission and reception are performed.

However, most of the conventional analyzers are used by connecting to a computer bus, and it is not possible to analyze how data is transmitted and received via a serial transmission line. Have difficulty. This is because even if the data on the bus is monitored, the actual state of data transmission / reception via the serial transmission line cannot be checked. For this reason, it is required to newly develop a dedicated analysis device, which leads to an increase in cost and time for system development.

The present invention has been made in view of the above circumstances, and enables debugging at the time of development and analysis of a factor at the time of occurrence of an error without easily developing a dedicated analysis device. It is an object of the present invention to provide an LSI device, a bus bridge device using the same, and a computer system.

[0009]

According to the present invention, there is provided an LSI device for transmitting and receiving data to and from an external device according to a predetermined protocol.
A storage device for storing trace information necessary for verifying the operation of the device, and monitoring transmission data or reception data of the LSI device, and transmitting predetermined transmission data or reception data matching the trace information collection condition to the trace information. And trace information collecting means for collecting the information and storing it in the storage means.

In this LSI device, a storage device and trace information collecting means are provided therein.
Predetermined transmission data or reception data that matches a condition for collecting trace information necessary for verifying the operation of the SI device is automatically collected as trace information and stored in the storage unit. By providing the trace information dump function in the LSI device as described above, the operation of the LSI device can be verified without newly developing a dedicated analysis device. Can be easily analyzed.

In particular, in an LSI device having serial transmission means for executing transmission and reception of data to and from the outside via a serial transmission line, transmission data to be serially transmitted to the outside by the serial transmission means, or serial transmission By using the received data received from the outside via the means as a monitoring target, it is possible to easily analyze how data is transmitted and received via the serial transmission line. Therefore, even in the bus bridge device including the first and second controllers which are physically different from each other, it is possible to easily verify the data transfer between the two controllers via the serial transmission line. And the development efficiency can be improved.

The conditions for collecting trace information are given by bit pattern information of transmission data or reception data to be collected, and transmission data or reception data that matches the bit pattern information is collected as trace information. By limiting the information to be collected in this way, it is possible to efficiently obtain information necessary for operation verification without providing a storage unit having a particularly large storage size. Further, in this case, by setting whether or not the trace information is valid as a condition for collecting the trace information for each bit pattern, it is possible to more efficiently collect only the information suitable for the purpose.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention. The computer system is a notebook-type personal computer (PC), and includes a PC body 100 and
A docking station 200 for function expansion that can be used by connecting a cable to the PC main body 100 is provided. The signal line in the cable is constituted by a serial transfer path 300 as shown. Serial transfer path 30
0 is LVDS (Low Voltage Differential Signal)
It comprises a line, an I ² C bus, and other serial control signal lines.

The LVDS line is connected to the PC in the PC body 100.
This is a serial transmission path used for serial connection between the I bus 2 and the PCI bus 4 in the docking station 200. By transmitting the high-speed bit serial signal through this serial transmission path, the PCI
Transfer of a bus transaction between the bus 2 and the PCI bus 4 in the docking station 200 is performed.

As shown in the figure, a PC main body 100 includes a processor bus 1, a PCI bus 2, an ISA bus 3, and a CPU 1
1, host-PCI bridge 12, main memory 13, display controller 14, primary PCI serial transfer controller 15, PCI-ISA bridge 16, I / O controller 17, various ISA devices 18, embedded controller (EC) 19, and others It is composed of various controllers 20 and the like.

The CPU 11 controls the operation of the entire PC system, and executes an operating system, a system BIOS, and various other programs loaded into the main memory 13. The host-PCI bridge 12 is a bridge device that bidirectionally connects the CPU bus 1 and the primary PCI bus 2, and includes a memory control logic for controlling access to the main memory 13 and a connection to the display controller 14. The control logic of the AGP used is also built-in. Host
The PCI bridge 12 can function as a bus master on the primary PCI bus 2. The main memory 13
It stores an operating system, an application program / utility to be processed, user data created by an application program, and the like.

The primary PCI serial transfer controller 15 logically constitutes one PCI-PCI bridge device in cooperation with the secondary PCI serial transfer controller 35 provided in the docking station 200. This PCI-PCI bridge device is for connecting bidirectionally between the PCI bus 2 in the PC body 100 and the PCI bus 4 in the docking station 200, and the device on the PCI bus 2
It allows accessing devices on the CI bus 4 and vice versa. The PCI bus 2 closer to the host as viewed from the PCI-PCI bridge device becomes the primary PCI bus of the PCI-PCI bridge device,
The CI bus 4 serves as a secondary PCI bus of the PCI-PCI bridge device. That is, in the present embodiment,
A PCI-PCI bridge device that connects the primary PCI bus 2 and the secondary PCI bus 4 may be physically different from each other.
A PCI serial interface is realized by dividing the controller into a plurality of controllers (a primary PCI serial transfer controller 15 and a secondary PCI serial transfer controller 35) and connecting them with LVDS lines. Serial transfer via LVDS line is P
Not only data for transmitting CI bus cycle,
It is also used for transmitting interrupt signals. Thus, PC
By serially transferring both the data for the I bus cycle and the interrupt signal via the same LVDS line, the number of signal lines required for the PCI serial interface can be greatly reduced.

The PCI-ISA bridge 16 is a bridge connecting the PCI bus 2 and the ISA bus 3, and is a PCI-ISA bridge.
It can operate as a bus master of the bus 2. IS
Various ISA devices 18 are connected to the A bus 3. The I / O controller 17 is a device that functions as a bus master or target on the PCI bus 2. Devices such as a PC card controller, an IDE controller, and a sound controller are connected as I / O controllers 17 on the PCI bus 2.

The embedded controller (EC) 19 is a PC
The power supply of the main body 100 is controlled, and the docking / docking sequence of the docking station 200 is controlled by communication with a docking station controller (DSC) 36 provided in the docking station 200.

The docking station 20 includes a PCI bus 4, a network interface controller 31, a PC card controller 32, an ID
An E controller 33, a PCI slot 34, a secondary PCI serial transfer controller 35, a docking station controller (DSC) 36, and other controllers 37 are provided.

The network interface controller 31 controls communication for connecting to a LAN, and functions as a bus master or a target on the PCI bus 4. The PC card controller 32
PCMCIA / CAR installed in PC card slot
It controls a DBUS specification PC card. This PC card controller 32 also functions as a bus master or target on the PCI bus 4. IDE controller 3
A PCI bus 4 controls an IDE device such as a hard disk drive or a CD-ROM drive provided in the docking station 20.
Act as upper bus master or target. PC
Various PCI expansion cards can be mounted in the I slot 34.

When the PC main body 100 is connected to the docking station 200, PCI devices such as the network interface controller 31, the PC card controller 32, the IDE controller 33, and the PCI expansion card in the PCI slot 34 are connected to the hardware inside the PC main body 100. It can be used as a wear resource.

(PCI-PCI Bridge) FIG. 2 shows the functional configuration of each of the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35.

As described above, the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35 are physically independent LSIs, but logically function as one PCI-PCI bridge. Therefore, the LVDS line connecting between the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35 is a PCI-P
It is only a local internal wiring in the CI bridge and is not recognized by software. This means that useless resources are not allocated to the serial transmission path. The same device identification information is assigned to the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35, so that the software recognizes them as one device. Of course, the two controllers of the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35 only need to be recognized as one device, so that only the primary PCI serial transfer controller 15 may have device identification information. .

Each of the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35 is composed of a PCI interface unit and a serial transfer interface unit.

In the primary PCI serial transfer controller 15, the PCI interface exchanges a bus transaction with the primary PCI bus 2. On the other hand, in the secondary PCI serial transfer controller 35, the PCI interface unit exchanges a bus transaction with the secondary PCI bus 4. The transfer of transactions between the PCI interface units is performed by serial data transfer between serial transfer interface units provided in the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35, respectively. This serial data transfer is executed according to a predetermined protocol.

The PCI bus is a parallel transmission line including a multi-bit address / data line and the like, and a bus transaction on the PCI bus is basically followed by an address phase for command and address output, followed by an address phase. 1
It comprises the above data transfer phase. Therefore, each PCI interface unit exchanges commands, addresses, and data with the corresponding PCI bus, and exchanges commands, addresses, and data between the PCI interface units by serial transfer between serial transfer interface units. Thereby, transmission of a transaction (PCI bus cycle) from the primary PCI bus 2 to the secondary PCI bus 4 and transmission of a transaction (PCI bus cycle) from the secondary PCI bus 4 to the primary PCI bus 2 become possible.

When transmitting a transaction from a bus master on the primary PCI bus 2 to a device on the secondary PCI bus 4, the primary PCI serial transfer controller 15 becomes a target of a transaction executed on the primary PCI bus 2, and The PCI serial transfer controller 35 becomes an initiator (bus master) of a transaction executed on the secondary PCI bus 4. On the other hand, the secondary PCI
When transmitting a transaction from a bus master on the bus 4 to a device on the primary PCI bus 2, the secondary PCI serial transfer controller 35 becomes a target of a transaction executed on the secondary PCI bus 4, and the primary PCI serial transfer controller 15. Is an initiator of a transaction executed on the primary PCI bus 2. If there is no bus master device on the secondary PCI bus 4, only the former case exists.

As shown, the PCI interfaces of the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35 have configuration registers 150 and 35 individually.
0 is provided. Configuration register 1
Each of the registers 50 and 350 is composed of a register group conforming to the PCI specification, in which the same environment setting information is set.

The environment setting information includes the above-described device identification information, device control information for designating hardware resources such as a memory address space and an I / O address space used by the device, and a current device state. And device status information indicating the status.

The device identification information is for identifying the type of the device, and includes a device ID, a vendor I
D, revision ID, header type, class code, and other information. The device identification information is read-only, and the configuration register 150,
The same device identification information is written in 350 in advance. Of course, the read-only device identification information may be prepared only on the primary PCI serial controller 15 side closer to the CPU 11,
There is no need to provide it on the secondary PCI serial controller 35 side. Only the primary PCI serial controller 15 is accessed in the configuration cycle by the CPU 11, and the primary PCI serial controller 15
By reading the device identification information from the serial controller 15, the PCI-P
This is because it is recognized that a CI bridge exists.

The configuration register is for holding environment setting information for defining the operating environment of the PCI device, and the PCI device is always provided with one configuration register. The primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35 are one PCI serial transfer controller.
Since the device operates as a device (PCI-PCI bridge), basically, as described above, one configuration register is connected to the controllers 15 and 35.
It can also be shared between. However, when the configuration register is provided in only one controller as described above, the controller without the configuration register is connected to the other controller via the serial transmission path every time the transaction processing is performed. The configuration register must be read, which causes a decrease in system performance. By separately mounting the configuration registers in the two controllers 15 and 35 as in the present embodiment, the two controllers 14 and 35 operate according to the environment setting information set in their own configuration registers. So you can
High-speed operation becomes possible. In this case, each of the two controllers 14 and 35 is provided with most of the other register groups (register groups for setting device control information, current registers, except for registers for setting read-only device identification information). Register group for setting device status information indicating the state of the device).

Configuration registers 150 and 3
The identity of the contents of 50 is realized by automatically executing the following copy operation between the primary PCI serial transfer controller 15 and the secondary PCI serial transfer controller 35. That is, when the CPU 11 executes a write transaction (configuration write cycle) for writing data to the configuration register 150, a copy operation from the configuration register 150 to the configuration register 350 is automatically performed, and thereafter, , A status indicating completion of writing is returned to the CPU 11. Thus, the contents of the configuration registers 150 and 350 can always be kept the same.

(Internal Structure of Two PCI Serial Transfer Controllers) Next, referring to FIG.
Serial transfer controller 15 and secondary PCI
The internal structure of each serial transfer controller 35 is
A description will be given focusing on a logical protocol hierarchical structure.

As shown in the figure, the primary PCI serial transfer controller 15
01, bus cycle controller 202, block transfer buffer 202, word buffer 204, serial / parallel converter 205, and LVDS transmitting / receiving unit 20
6 and so on.

The transaction buffer 201 and the bus cycle controller 202 correspond to the aforementioned PCI interface unit.
2. The word buffer 204, the serial / parallel converter 205, and the LVDS transmission / reception unit 206 correspond to the aforementioned serial interface unit.

Similarly, the secondary PCI serial transfer controller 35 receives signals from the transaction buffer 301, the bus cycle controller 302, the block transfer buffer 302, the word buffer 304, the serial / parallel converter 305, the LVDS transmission / reception unit 306, etc. It is configured. The transaction buffer 301 and the bus cycle controller 302 correspond to the aforementioned PCI interface unit, and the block transfer buffer 302, the word buffer 304, the serial / parallel converter 305, and the LVDS transmitting / receiving unit 306 correspond to the aforementioned serial interface unit.

The right end of FIG. 3 shows a protocol hierarchy for realizing the PCI serial interface of the present embodiment. The uppermost layer is a PCI bus transaction layer, and below it is a PCI bus cycle layer for controlling a bus cycle necessary for actually executing a transaction.

The part above the bus cycle layer, which is realized by integrating the left and right halves together, that is, the combination of the bus transaction buffers 202 and 301 and the bus cycle controllers 202 and 302 is a normal PCI- It is equivalent to a PCI bridge.

The lower half layer of FIG. 3 is the primary PC
This is a part for performing serial communication between the I serial transfer controller 15 and the secondary PCI serial transfer controller 35.

The upper half is designed according to the protocol of the PCI bus, while the lower half is designed to be optimal for faithfully transmitting data transferred on the PCI bus to the other party. It is not necessary to consider what the data to be transferred has on the PCI bus.
What is necessary is just to correctly assign and realize a transfer characteristic suitable for the meaning of having on the I bus. It can take a concept close to packet communication in the communication world.

In that sense, the word (WORD) in FIG.
Is a fixed-length packet, and is a block (BLOCK).
Is a transfer unit including a control word of 1 word and a data word of 0 to 10 words.

Transaction buffers 201 and 301
Is a buffer for managing a PCI bus cycle as a transaction, and is used to mediate between the PCI bus cycle and block transfer described later. The information that constitutes a transaction is slightly different depending on the type of transaction, but includes an address, a command, write data (a write transaction), a byte enable, a completion status, and read data (a read transaction). These information are stored in the transaction buffer 2
01, 301.

Block transfer buffer (BLOCK) 20
Reference numeral 4,304 designates variable-length data called a block as 2
This is a temporary information storage location for collectively transferring between the serial controllers 15 and 35. As described above, the block size is variable and basically includes information such as an address, data, a command, and a byte enable that constitute a certain transaction.

Word buffers (WORD) 204, 30
Reference numeral 4 denotes a temporary information storage location for transferring fixed-length data called a word (WORD) between the two serial controllers 15 and 35 one by one. Words include control words and data words. Substantial part of block (PCI transaction information: address,
Commands, data, byte enable, etc.) are passed as data words, and other various control information is passed as control words.

Serial / parallel converters 205 and 3
Reference numeral 05 performs parallel / serial conversion and serial / parallel conversion in word units. LVDS transceiver 2
06 and 306 perform actual serial data transfer via the LVDS line.

(Buffer Structure) Next, referring to FIG.
A specific buffer structure will be described.

There are the following two types of block buffers depending on the types of PCI transactions handled. -Express buffer (for posted memory write transactions)-BLOCK buffer (for other transactions) There are the following two types depending on the direction of data flow. Outgoing buffer (stores information of a block to be transmitted) Incoming buffer (stores information of a received block) There are a total of the following four types of buffers in combination with these. -Outgoing Express buffer (OEB)-Outgoing BLOCK buffer (OBB)-Incoming Express buffer (IEB)-Incoming BLOCK buffer (IBB) In the present embodiment, in order to secure the performance of the system, all of OBB, OEB, IBB, and IEB , Each 4
Prepared step by step. In that sense, four types of block buffer FIFOs, namely, OBB_FIFO and OEB_F
IFO, IBB_FIFO, and IEB_FIFO will be provided.

That is, as shown in FIG. 4, a four-stage Outgoing BLOCK buffer (OB
B) OBB_FIFO composed of 203a, OEB_FIFO composed of four-stage Outgoing Express buffer (OEB) 203b, four-stage Incoming BLOCK buffer (IBB) 203c, and four-stage Incoming Express
A buffer (IEB) 203d is provided. Similarly, the block buffer 303 also has a four-stage Outgoing BLO
OBB_ composed of a CK buffer (OBB) 303a
FIFO and 4-stage Outgoing Express buffer (OE
B) An OEB_FIFO composed of 303b, a four-stage incoming block buffer (IBB) 303c, and a four-stage incoming express buffer (IEB) 303d are provided.

As described above, a block is a group of words (WORD) having a structure. The block is composed of the following three parts. Both transmission and reception are processed in the following order in terms of time.

One control word A plurality of data words (zero to ten data words) One checksum word A word is a group of bits. It can be broadly classified into control words that carry control information and data words that carry data. Block buffers 203 and 20
In 3, each word constituting the block is represented by 17 as follows.
Handles bits as a unit.

The actual size of the information of each word constituting the block is 16 bits. The field for discriminating between the control word and the data word is 1 bit. The block buffers 203 and 303 have 17 bits between the lower processing layers. Data is transferred in units of bit words. The lower processing layers are the aforementioned word buffer and bit layer. The bit layer corresponds to the serial / parallel converters 205 and 305 and the LVDS transmission / reception units 206 and 306 in FIG. The following processing is performed in a lower processing hierarchy, and does not concern the block buffers 203 and 303.

Word buffer: 1-bit parity is added to each 17-bit word handled by the block buffer, and 18-bit data is created. Bit hierarchy: 18-bit data is converted from parallel data to serial data, and high-speed serial transfer is performed. Actually, since two LVDS lines for transmission and two LVDS lines for reception are provided in each of the controllers 15 and 35, 18-bit data is decomposed into 9-bit × 2 streams, and Are converted from parallel data to serial data and then serially transferred at the same time.

The receiving side performs the reverse process.

(Block Transfer) As described above, in this embodiment, serial transfer is performed in the lower hierarchy.
Data transfer (block transfer) is performed between the block buffers 203 and 303 in block units.
This block transfer is performed in the transaction buffer 20.
1,301 to service the request, and the information passed from the transaction buffer is
It is an object of the present invention to accurately and promptly send a message to a transaction buffer of a partner PCI serial transfer controller. In order to achieve this object, the block buffer layer adds the following information to the transmission target block.

Block ID for identifying the block
(Embedded in control word and transmitted) Checksum word (a type of control word) Block data to be transmitted and a block ID of a continuous value are added to it. Ideally, values from zero to infinity may be sequentially assigned as block IDs. However, in practice, there is a limit to the number of bits that can be used, so in this embodiment, a 3-bit block ID is prepared. , 0 to 7 are repeatedly assigned in this order.

(Internal Structure of Two PCI Serial Transfer Controllers) Next, referring to FIG.
Serial transfer controller 15 and secondary PCI
The internal configuration of each of the serial transfer controllers 35 will be described.

The configuration of the primary PCI serial transfer controller 15 and the configuration of the secondary PCI serial transfer controller 35 are basically the same. As shown, these controllers include a PCI bus control block (PCI_CTL) 401, a PCI bus arbitration block (ARBIT) 402, a cycle decode block (CYCDEC) 403, a configuration register block (CF_REG) 404, a transaction buffer & control block. (TBC)
405, block & word buffer block (BWB)
406, block transfer buffer block (BB) 40
7, a word buffer block (WB) 408, a bit layer block (BLB) 409, a Misc information update block (MIS) 410, and a serial interrupt synchronization block (SIS) 411.

The PCI control block (PCI_C
A TL) 401 controls a PCI bus interface as a PCI bus master and a target, and includes a master latency timer (MLT). The master latency timer (MLT) is for measuring the timing for causing the bus master executing the current cycle to stop the cycle.
During the target operation, the PCI bus control block (PCI_CTL) 401 operates using a hit signal from the cycle decode block (CYCDEC) 403 as a trigger. That is, when receiving the hit signal, the PCI bus control block (PCI_CTL) 401 starts a PCI bus cycle as a target in response to the PCI bus cycle performed by the current bus master on the PCI bus.

A PCI bus arbitration block (ARBIT) 402 is an arbiter for arbitrating a PCI bus master on the PCI bus.

The cycle decode block (CYCDE)
C) 403 performs a hit determination by decoding the PCI cycle type and address during the PCI bus target operation. The cycle decode block (CYCD)
The EC 403 includes a cycle start signal for the transaction buffer & control block (TBC) 405 and a PCI bus control block (PCI
(_CTL) 401 is generated.

The configuration register block (CF_REG) 404 is the aforementioned PCI configuration register.

A transaction buffer & control block (TBC) 405 is a buffer for managing a PCI bus cycle as a transaction, and transfers data between a block transfer buffer block (BB) 407 and a PCI bus control block (PCI_CTL) 401. Perform control.

Block & word buffer block (BW
B) 406 is a block transfer buffer block (B) composed of the aforementioned block buffer and its control logic.
B) 407 and a word buffer block (WB) 40 composed of the aforementioned word buffer and its control logic.
8 are combined into one for convenience. The block transfer buffer block (BB) 407 is
Transaction buffer & control block (T
(BC) 405 or word buffer block (WB) 4
08 is used to temporarily store data transmitted and received between the device and the device. Further, buffers for post-write (OEB / IEB) and for buffers other than post-write (OBB / IBB) are independently provided as buffers. OEB / OBB in the figure is a transmission buffer, IEB / IBB
Is a receiving buffer. The transmission and reception buffers are stored in the P layer in the bit layer block 409, respectively.
It operates with asynchronous transmission and reception clocks generated by the LL. Since the PCI clock is not used, the block is not synchronized with a block of a higher layer than the block transfer buffer block (BB) 407. The block & word buffer block (BWB) 406 also performs checksum generation, error checking on the serial bus, and control of retransmission processing. Further, the block & word buffer block (BWB) 406 collects predetermined transmission data or reception data that matches the collection condition of the trace information necessary for the operation verification of the controller from the data transmitted and received via the serial bus.・ A dump function for recording is provided. The information collected by this dump function is
11, the state of serial transmission executed via the serial bus can be easily analyzed by software.

Word buffer block (WB) 408
Is a buffer for temporarily storing the fixed-length data (BLOCK) from the block transfer buffer block (BB) 407 with the bit layer block (BLB) 409 one by one in WORD units. is there. In the figure, OWB denotes a transmission buffer, and IWB denotes a reception buffer.
B) It operates with asynchronous transmission and reception clocks generated by the PLL in 409.

Bit layer block (BLB) 409
Divides the fixed-length data (WORD) from the word buffer block (WB) 408 into two parts and performs serial communication as two systems of serial data. The transmitting side performs parallel-to-serial conversion and performs reception. The side performs serial-to-parallel conversion. The bit layer block (BLB) 409 has PLLs for transmission and reception, respectively, and the transmission PLL has a predetermined clock (PLL).
CLK) input and operate (multiply by 9) to receive PLL.
Operates based on the LVDS serial reception clock (LVDC_I) transmitted from the secondary PCI serial transfer controller 35 via the LVDS line. In addition,
The LVDS serial transmission clock (LVDC_O) is P
The output has the same frequency as the LCLK input.

Misc information update block (MIS) 41
0 is a PCI bus interrupt signal (INT [A: D]
#) Is treated as misc information. Serial interrupt synchronous block (SIS)
A block 411 processes a legacy interrupt signal from an ISA device or the like.

(Dump Function) Next, a configuration for realizing the above-described dump function will be described with reference to FIG.

Block & word buffer block (BW
B) 406 includes a dump function for the received word received by the word buffer 408, and a word buffer 408.
And a dump function for a transmission word transmitted via the. The dump function for the received word is realized by the received word dump register group 501, the received word dump control unit 502, and the dump condition register 503. The dump function for the transmitted word is the transmitted word dump register group 601, the transmitted word dump control unit 602. , And the dump condition register 603.

The received word dump register group 501 is a storage device for storing trace information necessary for verifying the operation of the controllers 15 and 35, and is configured to be read-accessible from the CPU 11 through the above-described configuration register. The received word dump register group 501 includes 64 word storage registers, and can store up to 64 received words at a time as trace information.

The received word dump control unit 502 monitors the received word from the receiving word buffer (IWB),
According to the dump condition of the received word set in the dump condition register 503, predetermined received words that match the trace information collecting condition (dump condition) are collected as trace information and sequentially stored in the registers of the received word dump register group 501. Store.

The dump condition register 503 is also configured to be accessible from the CPU 11 through the above-described configuration register, and an arbitrary dump condition relating to a received word can be set by software. The dump condition is given by bit pattern information of a received word to be collected, and a received word that matches the bit pattern information is collected as trace information. In this case, by setting the dump condition register 503, it is possible to specify, for each bit pattern, whether or not the bit pattern is valid as a trace information collection condition. The contents of each bit pattern can be set by the dump condition register 503, but may be fixedly set using internal wiring or the like.

Transmission word dump register group 601 Like the reception word dump register group 501, the controller 1
This is a storage device for storing trace information necessary for operation verification of the CPUs 5 and 35, and is configured to be read-accessible from the CPU 11 through the above-described configuration register. This transmission word dump register group 601
Contains 64 word storage registers, and can store up to 64 transmission words at a time as trace information.

The transmission word dump control unit 602 monitors transmission words transmitted via a transmission word buffer (OWB), and obtains trace information collection conditions in accordance with the transmission word dump conditions set in the dump condition register 603. A predetermined transmission word that matches (dump condition) is collected as trace information, and the transmission word dump register group 60 is collected.
1 in order.

The dump condition register 603 is configured to be accessible from the CPU 11 through the configuration register, similarly to the above-described dump condition register 503, and an arbitrary dump condition relating to a transmission word can be set by software. The dump condition is given by bit pattern information of a received word to be collected, and a transmission word that matches the bit pattern information is collected as trace information. In this case, by setting the dump condition register 603, it is possible to specify, for each bit pattern, whether or not the trace information is valid as a trace information collection condition. The content of each bit pattern can be set by the dump condition register 603, but may be fixedly set using internal wiring or the like.

(Dump Control Circuit) Next, specific circuit configurations of the received word dump control unit 502 and the transmitted word dump control unit 602 will be described. Since the reception word dump control unit 502 and the transmission word dump control unit 602 can be realized by basically the same configuration, the following description refers to FIG.
The circuit configuration of the received word dump control unit 502 will be described as a representative.

The 64 registers of the reception word control register 501 are commonly connected to the output of the IWB. A write control circuit including a comparator and an AND circuit is provided for each of these 64 registers.

That is, the comparator 601 and the AND circuit 60
1 controls writing to the register # 0, and the 6-bit counter value from the counter 708 indicates the register number “0” (= 00) corresponding to the register # 0.
0000) is detected by the comparator 601 and writing to the register # 0 is started on condition that a signal indicating that the current received word matches the dump condition is output from the OR circuit 707. The current received word is written to register # 0.

Similarly, writing to register # 1 is controlled by comparator 603 and AND circuit 604, and writing to register # 63 is performed by comparator 605 and A
It is controlled by the ND circuit 606.

The value of the counter 708 is a signal indicating that the current received word matches the dump condition.
It is counted up each time it is output from. Thus, the 64 registers # 0 to # 63 are sequentially selected as registers to be written.

The dump condition of the received word is given by a number of bit patterns from pattern A to pattern Z. For each of these patterns A to Z, dump conditions A to Z indicating the validity of the pattern are designated. Is done. A condition determination circuit including a comparator and an AND circuit is provided for each of the patterns A to Z.

For pattern A, comparators 701 and A
The ND circuit 702 determines whether or not the conditions match.
That is, when the comparator 701 detects that the bit pattern of the current received word matches the bit pattern of the pattern A, and when the pattern A is valid as the dump condition, the current received word becomes the dump condition of the pattern A. Is output from the AND circuit 702.

Similarly, for pattern B, comparator 70
3 and the AND circuit 704 determine whether or not the conditions match. For the pattern Z, the comparator 705 and the AND circuit 7
06, it is determined whether or not the conditions match.

When the received word matches one of the conditions of patterns A to Z, a signal indicating that the current received word matches the dump condition is output from OR circuit 707.

With the above configuration, the controllers 15, 3
5, it is possible to collect and store only the received word of the predetermined bit pattern necessary for the operation verification as trace information.

The transmission word dump control section 602 can be realized with the same circuit configuration, whereby only transmission words of a predetermined bit pattern necessary for operation verification of the controllers 15 and 35 are collected as trace information.・ It becomes possible to memorize.

As described above, in the present embodiment, by mounting the dump function inside the controllers 15 and 35, serial data transfer between the controllers 15 and 35 can be performed without newly developing a dedicated analyzer. Operation can be verified, and debugging at the time of development and analysis of a factor at the time of occurrence of an error can be easily performed. Note that this dump function is provided by the LS that constitutes the bus bridge device.
I, as well as other various L used in computers, etc.
It can also be applied to SI.

In the present embodiment, two controllers constituting a bridge are separately arranged in the PC main body 100 and the docking station 200. However, for example, a first extension unit is connected to the PC main body 100, and the first expansion unit is connected to the first main body. In the case where the second extension unit is further connected via the second extension unit, the computer main unit and the first extension unit function as a host device from the viewpoint of the second extension unit. In this case, the primary PC and the first PC are respectively assigned to the first PC and the second PC.
The I serial transfer controller 15 and the secondary PCI serial transfer controller 35 may be provided separately.

[0089]

As described above, according to the present invention,
By providing the dump function in the LSI itself, it is possible to easily perform debugging at the time of development or cause analysis at the time of occurrence of an error without newly developing a dedicated analysis device. In particular, in a bus bridge device composed of two physically different first and second controllers,
It is possible to easily verify how data is exchanged between the two controllers via the serial transmission line, and to improve the development efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary block diagram showing a configuration of a PCI-PCI bridge used in the embodiment.

FIG. 3 is an exemplary block diagram showing the internal structure of each of a primary PCI serial transfer controller and a secondary PCI serial transfer controller used in the embodiment;

FIG. 4 is an exemplary view showing a buffer structure in each of a primary PCI serial transfer controller and a secondary PCI serial transfer controller used in the embodiment;

FIG. 5 is an exemplary block diagram showing a specific hardware configuration of a primary PCI serial transfer controller and a secondary PCI serial transfer controller used in the embodiment;

FIG. 6 is an exemplary block diagram for explaining a dump function used in the embodiment;

FIG. 7 is a view showing a specific hardware configuration of a dump control unit used in the embodiment.

[Explanation of symbols]

 2 Primary PCI bus 4 Secondary PCI bus 11 CPU 15 Primary PCI serial transfer controller 35 Secondary PCI serial transfer controller 100 PC body 200 Docking station 501 Received word dump register 502 Received word dump control unit 503 Dump condition register 601: Transmission word dump register 602: Transmission word dump control unit 603: Dump condition register

Claims (7)

[Claims] 1. An LSI device for transmitting and receiving data to and from an external device according to a predetermined protocol, comprising: a storage device for storing trace information required for verifying the operation of the LSI device; An LSI device for monitoring data, collecting predetermined transmission data or reception data matching the conditions for collecting the trace information as the trace information, and storing the same in the storage unit. . 2. The trace information collection condition is bit pattern information of transmission data or reception data to be collected, and the trace information collection means includes: transmission data or reception data of the LSI device; 2. The LSI device according to claim 1, wherein the transmission data or the reception data that matches the bit pattern information is collected as the trace information. 3. The bit pattern information includes a plurality of bit patterns different from each other, and whether or not the trace information is effective as a sampling condition is set for each of the bit patterns. The LSI device according to claim 2, wherein 4. The LSI device according to claim 1, wherein said LSI device is a bus bridge device for connecting buses of a computer system. 5. The apparatus according to claim 1, further comprising a serial transmission unit for executing transmission and reception of data to and from the outside via a serial transmission line, wherein the trace information collection unit is to be serially transmitted to the outside by the serial transmission unit. 2. The LSI device according to claim 1, wherein transmission data or reception data received from outside via the serial transmission unit is monitored. 6. The first controller is composed of two physically different first and second controllers, and the first controller is connected by performing serial transmission of data between the first and second two controllers. A bus bridge device for connecting a first bus and a second bus to which the second controller is connected, wherein the first and second at least one controller operate the bus bridge device. A storage device for storing trace information required for verification, and monitoring transmission data or reception data between the first and second controllers, and predetermined transmission data or reception matching the trace information collection condition And a trace information collecting means for collecting data as the trace information and storing the data in the storage means. Equipment. 7. A host device-side bus and said expansion unit, comprising first and second physically different controllers provided separately in a host device and an expansion unit for expanding the function of the host device. A computer system having a bridge device for connecting to a bus on the side via a serial transmission line provided between the controllers, wherein the first and second controllers are at least one of: A storage device for storing trace information required for verifying the operation of the bus bridge device; and a transmission device for monitoring transmission data or reception data between the first and second controllers, and a predetermined device that satisfies a condition for collecting the trace information. Trace information collection means for collecting transmission data or reception data as the trace information and storing it in the storage means; A computer system comprising: