JP2001153927A - Inspection method for semiconductor integrated circuit, and transport device used in it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method reducing the test time by easily executing a self-diagnostic test simultaneously with a test other than the self-diagnostic test when testing a semiconductor integrated circuit with a self-diagnostic function. SOLUTION: When inspecting a semiconductor integrated circuit with a plurality of independent circuits, the circuits are divided into a plurality of blocks and then a plurality of inspections are sequentially executed and results are aggregated so that corresponding inspection process to every block to each circuit. Also, the semiconductor integrated circuit, which contains a self- diagnostic circuit, includes a self-diagnostic operating the self-diagnostic circuit to inspect a circuit function and an external inspection process operating an external diagnostic circuit to inspect the circuit function. Then, the integrated circuit can execute the self-diagnostic inspection process with the external inspection process simultaneously to another circuits in a plurality of the semiconductor integrated circuit devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for inspecting a semiconductor integrated circuit, and more particularly to a method for inspecting a semiconductor integrated circuit having a self-diagnosis circuit on a wafer and inspecting a packaged product. Related to inspection method.

[0002]

2. Description of the Related Art In sorting semiconductor integrated circuit chips,
Various inspection methods are used to improve the efficiency of the screening test and reduce the cost. Among them, an integrated circuit having a self-diagnosis function has an integrated circuit structure having a circuit with a self-diagnosis function (101) and a circuit without a self-diagnosis function (102) on one chip as shown in FIG. There are many. In performing such a test of the semiconductor integrated circuit chip, the self-diagnosis circuit (101) outputs a test result to an output (108) by inputting a test start signal only to the inputs (103, 104). The absence circuit (102) outputs a signal to the output (109, 110, 111) by inputting a signal from the LSI tester to the input (105, 106, 107) and compares it with the value of the expected value memory by the LSI tester. , To obtain test results.
For all terminals (103 to 111) of the present integrated circuit, DC test items, that is, DC items are measured by the LSI tester.

The test execution process is performed as shown in a timing chart of FIG. The horizontal axis represents the number of test executions, and the vertical axis represents the test execution time. Here, the semiconductor integrated circuits tested in the first test are DUT1, the semiconductor integrated circuits tested in the second and third tests are DUT2 and DUT3, and the next DUT is continued. Each DUT has a DC test (401, 404, 407) for checking DC items, an FC test (402, 405, 408) for a circuit without a self-diagnosis function, and a self-test (403, 406, 409) and the test is executed, and the test execution time when all are good products is the product of the sum of each test execution time and the number of DUTs.

[0004]

Therefore, various attempts have been made to reduce the time required for the test.
During the test of the circuit with the self-diagnosis function,
When measuring the C test items to reduce the test time per chip, the test between the circuit with self-diagnosis function and other functional circuits, the restriction of terminals, and the test conditions ensure the test of the semiconductor integrated circuit. However, there is a problem that it is difficult to actually reduce the time sufficiently.

The present invention has been made in view of the above circumstances, and has as its object to shorten the time required for inspection and to obtain a highly reliable semiconductor integrated circuit device. Another object of the present invention is to provide an inspection apparatus capable of performing a highly reliable inspection in a short time using a conventional inspection apparatus.

[0006]

According to the inspection method of the present invention, when inspecting a semiconductor integrated circuit device having a plurality of independent circuits, the circuit is divided into a plurality of blocks.
It is characterized in that a plurality of inspections are sequentially executed simultaneously and the results are totaled so that an inspection step corresponding to each block is executed for each circuit.

According to the method of the present invention, there is provided a method of testing a plurality of semiconductor integrated circuit devices, wherein the semiconductor integrated circuit is an integrated circuit having a self-diagnosis circuit therein, and the self-diagnosis circuit is operated to A self-inspection step of inspecting the function and an external inspection step of operating an external diagnostic circuit to inspect the function of the circuit, wherein the self-inspection step and the external inspection step are performed by a plurality of semiconductor integrated circuit devices. The present invention is characterized in that the processing can be performed simultaneously on different circuit blocks.

That is, a self-diagnosis test is performed on one of the plurality of semiconductor integrated circuit chips (TEST1), and a self-diagnosis test is performed on the other semiconductor integrated circuit chip at the same time. Full test (TEST2) other than is performed.

This makes it possible to test each semiconductor integrated circuit completely independently only by increasing the number of pins and the number of power supplies required for the self-diagnosis test. If the self-diagnosis test time is shorter than the time of the other full test, the self-diagnosis test time is substantially eliminated. The test time of the semiconductor integrated circuit can be easily reduced significantly.

That is, as a solution from the carrier device side, for example, for each of two semiconductor integrated circuits,
Having a judgment result, TES is carried along with transport of one semiconductor integrated circuit.
The judgment result on the T1 side is shifted to the TEST2 side, and the final test judgment of the corresponding semiconductor integrated circuit is performed at the end of TEST2.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to inspecting a semiconductor integrated circuit device having a plurality of independent circuits, dividing the circuit into a plurality of blocks, A plurality of inspections are sequentially executed simultaneously so that an inspection process corresponding to each block is executed, and the results are totalized.

According to this configuration, since the blocks are divided so that a plurality of inspections are performed at the same time, the inspection is performed simultaneously on a plurality of circuit blocks, so that the inspection time can be easily reduced. It becomes possible.

According to a second aspect of the present invention, there is provided an inspection method of a plurality of semiconductor integrated circuit devices, wherein the semiconductor integrated circuit is an integrated circuit having a self-diagnosis circuit therein. A self-inspection step of operating and inspecting the function of the circuit, and an external inspection step of operating an external diagnostic circuit and inspecting the function of the circuit, wherein the self-inspection step and the external inspection step include a plurality of steps. The present invention is characterized in that the processing can be simultaneously performed on another circuit block of the semiconductor integrated circuit device.

According to this configuration, in a test of a chip having a plurality of independent circuits in which an integrated circuit having a self-diagnosis circuit is formed, two chips are tested in one test. The self-test for operating the self-diagnosis circuit is performed for the chip of U. For the other one, the DC test and function test other than the self-test are performed to overlap the test time related to the test of the self-diagnosis circuit with the test time other than the self-diagnosis, so that the total cost per chip is The test time can be shortened, whereby the test time of the semiconductor integrated circuit can be easily reduced.

According to a third aspect of the present invention, in the inspection method according to the second aspect, the semiconductor integrated circuit is an integrated circuit having a plurality of self-diagnosis circuits. The self-diagnosis circuit is characterized in that the self-diagnosis circuit inherits the diagnosis result of the previous diagnosis circuit, and the output of the last self-diagnosis circuit adds up the output results of all the self-diagnosis circuits.

According to this configuration, the output of the last self-diagnosis circuit is configured to add up the output results of all the self-diagnosis circuits, so that diagnosis can be easily performed immediately.

According to a fourth aspect of the present invention, there is provided a transporting device for simultaneously performing a needle-contact test on a plurality of chips constituting a semiconductor integrated circuit device, transporting the chips one by one after the test, and storing a test result on one side. And a counting means for superimposing the test result on the chip which is to be conveyed and executed next to obtain the test result of the chip.

According to this configuration, it is possible to simultaneously execute the inspection at the chip level using the conventional apparatus, and it is possible to perform a highly reliable inspection in a short time.

Further, in the transfer device according to claim 5 of the present invention, when inspecting a packaged product, a test is performed on a plurality of packaged semiconductor chips at the same time with a needle, and after the test, a transfer means for transferring one package at a time; And a counting means for storing the test result of the semiconductor chip, and superimposing the test result on the next transported and executed test result.

According to such a configuration, it is possible to simultaneously execute the inspection at the package level using the conventional apparatus, and it is possible to perform the inspection with high reliability in a short time.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described in detail with reference to FIGS.

(Embodiment 1) FIG. 1 is an explanatory view showing a semiconductor integrated circuit device inspection apparatus according to the present invention. As shown in FIG. 2, two circuit chips DUT1 and DUT with a self-diagnosis function circuit as shown in FIG.
The UT 2 includes an external test step of operating a self-diagnosis circuit, testing the function of the circuit with the self-diagnosis circuit, operating an external diagnosis circuit, and testing the function of the circuit externally. The external inspection step is simultaneously performed on another circuit block of a plurality of semiconductor integrated circuit devices, and the results are totaled to perform a reliable inspection in a short time.

Here, as shown in FIG.
And an LSI tester (301) for simultaneously testing other circuit blocks of a plurality of semiconductor integrated circuit devices, and summing up the results using the processing circuit 30 mounted in the carrier device 10. It is like that. DUT1
For (201), only the terminal for the self-diagnosis function circuit (202) is connected to the LSI tester (301) (2).
04, 205, and 206), and the circuit (203) without the self-diagnosis function is not connected to the LSI tester (301). At this time, for the DUT2 (207), the self-test of the circuit with the self-diagnosis function has been completed immediately before, and all terminals are connected to the LSI tester (210 to 218).

Here, as shown in FIG. 1, the DUT 1 (30
8) and DUT2 (307) are inspected by the LSI tester (301), and the self-test result (302) of DUT1 and DUT2
DC test / FC test result (303) is stored.
In (300), the self test result of the DUT 2 executed immediately before is stored. Immediately before the self-test result (30
0) and the result of the DC test / FC test result (303), the total test result is determined (304), and the result of the determination is used to select DUT2 in the selection process. Simultaneously with the selection processing of DUT2, DUT1 is transferred to the position of DUT2, and the self-test result of DUT1 is also moved to the position of the self-test result immediately before DUT2, and the untested DUT (309) is transferred to the position of DUT1. Once again, run the test again.

At the same time as the start of the test, the self test for the DUT 1 is started by the inputs (204, 205) of the self diagnostic function circuit of the DUT 1. Next, for DUT2, DC test of all terminals and function test (F
C test). As soon as the tests of both DUT1 and DUT2 are completed, the LSI tester sends the respective test results to the carrier device 10 of the semiconductor integrated circuit. The transport device 10 determines the quality of the DUT2 from the total test result of the DUT2,
Shift the semiconductor integrated circuit of DUT1 and the test result of DUT1 to the position of DUT2, and move the untested semiconductor integrated circuit to DUT1.
To the position.

FIG. 3 is a timing chart of the test execution time. The horizontal axis represents the number of test executions and the vertical axis represents the test execution time. The semiconductor integrated circuits to be inspected in the first test are DUT1, the semiconductor integrated circuits to be inspected in the second and third tests are DUT2 and DUT3, and thereafter the next DUT is continued.
Also, each DUT has a DC test (502, 5) for checking DC items.
05, 508), FC test for circuits without self-diagnosis function (50
3, 506, 509) and a self-test (501, 504, 507, 510) of a circuit having a self-diagnosis function. In the first test, only the self test of the DUT 1 is executed. In the second and subsequent tests, the self test of DUT2 and the DC test and FC test of DUT1 can be executed in parallel, and the actual test execution time compares the self test time with the other DC test and FC test time. Then, almost all of the semiconductor integrated circuits can be tested within the longer test time.

In this way, the inspection process is performed extremely efficiently, and the inspection time can be reduced. In addition, by adding only the transport device 10, it is possible to perform the inspection using the conventional inspection device as it is.

(Embodiment 2) FIG. 4 shows a semiconductor chip having three circuits with a self-diagnosis function. In testing such a semiconductor chip, an input of one of the first circuits with a self-diagnosis function (602) receives a signal from a terminal (606, 607) of the semiconductor integrated circuit and starts a self-test. . The output of the determination result is received at the input of the second circuit with self-diagnosis function 2 (603), and the self-test of the second circuit with self-diagnosis function is started. Similarly, the third circuit with a self-diagnosis function (604) also performs a self-test based on the result of determination by the second circuit with a self-diagnosis function, and outputs the result of the determination to an output (611). The circuit without self-diagnosis function (601) is composed of inputs (608, 609, 610) and outputs (612, 613, 614).

As described above, even when there are a plurality of circuits with a self-diagnosis function, the same test as in the first embodiment can be executed in an extremely short time.

In the above-described embodiment, the inspection process of the semiconductor chip has been described. However, the present invention is not limited to this, and it is also applicable to the inspection process after mounting, that is, in the state of the semiconductor package. Not even.

In the case of a high-density integrated circuit or the like, a plurality of inspection steps may be simultaneously performed on the same semiconductor chip.

[0032]

As described above, according to the present invention, the test time of a semiconductor integrated circuit having a self-diagnosis function can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a carrier device of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a semiconductor integrated circuit device used in the first embodiment of the present invention;

FIG. 3 is a timing chart showing test execution in the semiconductor integrated circuit device inspection method of the present invention.

FIG. 4 is a diagram showing a method for testing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 5 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 6 is a timing chart showing test execution in a conventional semiconductor integrated circuit device inspection method.

[Brief description of reference numerals]

 10 Conveyor 30 Processing circuit 101 Circuit with self-diagnosis function 102 Circuit without self-diagnosis function 103 Input terminal of self-diagnosis circuit 104 Input terminal of self-diagnosis circuit 105 Input terminal of circuit without self-diagnosis function 106 Input terminal of circuit without self-diagnosis function 107 Input terminal of circuit without self-diagnosis function 108 Output terminal of self-diagnosis circuit 109 Output terminal of circuit without self-diagnosis function 110 Output terminal of circuit without self-diagnosis function 111 Output terminal of circuit without self-diagnosis function 201 Semiconductor integrated circuit DUT1 202 DUT1 Circuit with self-diagnosis function of 203 Circuit with no self-diagnosis function of DUT1 204 Input terminal of DUT1 205 Input terminal of DUT1 206 Output terminal of DUT1 207 Semiconductor integrated circuit DUT2 208 Circuit with self-diagnosis function of DUT2 209 Circuit with self-diagnosis function of DUT2 210 DUT2 input terminal 211 DUT2 input terminal 212 DUT2 input terminal 213 DUT2 input terminal 214 DUT2 input terminal 215 DUT2 output terminal 216 DUT2 output Child 217 DUT2 output terminal 218 DUT2 output terminal 300 Self test result immediately before 301 LSI tester 302 DUT1 self test result 303 DUT2 test result 304 Total test result 306 Sorting process 307 DUT2 308 DUT1 309 Untested DUT 401 DC of DUT1 Test 402 DUT1 FC test 403 DUT1 self test 404 DUT2 DC test 405 DUT2 FC test 406 DUT2 self test 407 DUT3 DC test 408 DUT3 FC test 409 DUT3 self test 501 DUT1 self test 502 DUT1 DC Test 503 DUT1 FC test 504 DUT2 self test 505 DUT2 DC test 506 DUT2 FC test 507 DUT3 self test 508 DUT3 DC test 509 DUT3 FC test 510 Next DUT self test 601 Circuit without self-diagnosis function 602 Circuit with first self-diagnosis function 603 Circuit with second self-diagnosis function 604 Circuit with third self-diagnosis function 606 Input terminal of circuit 1 with self-diagnosis function 607 Input terminal of circuit 1 with self-diagnosis function 608 Self Input terminal of circuit without disconnection function 609 Input terminal of circuit without self-diagnosis function 610 Input terminal of circuit without self-diagnosis function 611 Output terminal of circuit 1 with self-diagnosis function 612 Output terminal of circuit without self-diagnosis function 613 Circuit without self-diagnosis function Output terminal of 614 Output terminal of circuit without self-diagnosis function

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822

Claims (5)

[Claims] An inspection method for a semiconductor integrated circuit device having a plurality of independent circuits, wherein the circuit is divided into a plurality of blocks, and an inspection step corresponding to each block is performed on each circuit. A test method for a semiconductor integrated circuit device, wherein a plurality of tests are sequentially executed simultaneously and the results are totaled. 2. A method for testing a plurality of semiconductor integrated circuit devices, wherein said semiconductor integrated circuit is an integrated circuit having a self-diagnosis circuit therein, wherein said semiconductor integrated circuit operates a self-diagnosis circuit and tests a function of the circuit. A self-inspection step, wherein the self-inspection step and the external inspection step are performed in different circuit blocks of a plurality of semiconductor integrated circuit devices. 2. The method for testing a semiconductor integrated circuit device according to claim 1, wherein the inspection is performed simultaneously. 3. The semiconductor integrated circuit is an integrated circuit having a plurality of self-diagnosis circuits, each self-diagnosis circuit being connected, each self-diagnosis circuit inheriting a diagnosis result of a previous diagnosis circuit, and 3. The method for testing a semiconductor integrated circuit device according to claim 2, wherein the output of the self-diagnosis circuit is summed up with the output results of all the self-diagnosis circuits. 4. A wafer inspection apparatus for performing the method for inspecting a semiconductor integrated circuit device according to claim 1, wherein a test is performed on a plurality of chips constituting the semiconductor integrated circuit device at the same time, and after the test, one chip at a time. A wafer inspection device, comprising: a transport unit for transporting, and a counting unit for storing a test result of one side, superimposing the test result on the next transport and performing the test result of the chip. Transport device. 5. In a packaged product inspection for carrying out the method for inspecting a semiconductor integrated circuit device according to claim 1, a plurality of packaged semiconductor chips are simultaneously subjected to a needle contact test, and transported one package at a time after the test. When,
A transfer device for semiconductor inspection, comprising: a test means for storing a test result of a semiconductor chip on one side, and superimposing the test result on the next transported and executed test result.