JP2001127159A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To oxidize the surface of Cu to increase resistance by forming an insulation film coating a Cu wiring and also diffuse Cu onto the insulation film, so that insulation effects are lowered to easily generate a leak in a semiconductor device using Cu as a wiring layer. SOLUTION: A first insulation film 104a is formed on a semiconductor substrate 101, and metal wirings 106a, 107a, 106b structured by a conductive film of a single layer or a plurality of layers in which a main conductive layer is composed of Cu or a Cu alloy are formed on this first insulation film, and this wiring is coated with a second insulation film 108a. Impurities such as P, B, As, Pb, N, or the like are led into this second insulation film, whereby a region where Cu of a wiring is exposed can be set to be in a state of coming into contact with the insulation film having high diffusion preventing capacity of Cu, and in the peripheries of the wiring, oxidation prevention of Cu, diffusion prevention of Cu, and improvements in electro-migration resistance and stress migration resistance of Cu are possible, and a third insulation film 110a is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a method for manufacturing a semiconductor device having a structure in which copper wiring is covered with an insulating film.

[0002]

2. Description of the Related Art A Cu (copper) wiring is used as a wiring layer of a semiconductor device.
When an insulating film is formed on a wiring, there is a problem that the surface of Cu is oxidized, or Cu diffuses into the insulating film to cause an increase in wiring resistance and a wiring leak. As a technique for solving such a problem associated with Cu wiring, Takewaki et al.
A structure for improving the oxidation resistance around the wiring and a manufacturing method thereof are proposed. (1995 IEICE Electronics Society Conference Proceedings 2, Lecture No. C-41
8, ppl 15-116). This technique is shown in the process sectional view of FIG. First, as shown in FIG.
01, a Si oxide film 104a is formed thereon,
The wiring formed at 07a is formed. Subsequently, FIG.
As shown in (b), the Si substrate 101 is exposed to a monosilane (SiH ₄ ) gas 109c while heating, so that Cu and S
The SiH in the iH ₄ gas is reacted, and CuxS
iy layer (x and y are integers, hereinafter, Cu silicide layer) 10
7c, and the Cu silicide layer 107c forms C
The oxidation of the u film 107a is prevented.

On the other hand, Miyazaki et al. Have proposed a method of preventing oxidation of Cu when an interlayer insulating film is formed on a Cu wiring (1).
Proceedings of the IEICE Electronics Society Conference 995, Lecture No. C-419, ppl17
-118). This technique is shown in the process sectional view of FIG. First, as shown in FIG. 4A, a tungsten (W) film 1 is formed on a BPSG film 104c formed on a Si substrate 101.
06d, a Cu film 107a, and a W film 106e are sequentially formed,
A high-temperature reactive ion etching method at 250 ° C. using an insulating film (not shown) as an etching mask and a mixed gas of silicon tetrachloride (SiCl ₄ ) + nitrogen (N ₂ ) + oxygen (O ₂ ) as an etching gas is used. The three conductive layers are sequentially etched to form a W film 106e, a Cu film 107a, and a W film 106d.
Is formed. further,
As shown in FIG. 4B, tetraethoxysilane (Te
tra Ethoxy Silane, hereinafter TEO
A plasma TEOS oxide film (PE-TEOS oxide film) 108d, which is a Si oxide film, is formed on a Cu wiring by a plasma CVD method using a mixed gas of S) + O ₂ . In this high temperature reactive ion etching step, C
A silicon oxide film-based side wall protective film (not shown) is formed on the side wall of the u wiring, and Cu oxidation is very slow in the presence of TEOS. It does not become.

In Japanese Patent Application Laid-Open No. 3-289156, Miyazaki also proposes a technique in which an insulating film itself formed on Cu has a capability of preventing Cu from diffusing. In this technique, as shown in FIG.
First, as shown in FIG. 5A, after a field oxide film 102 is formed on a p-type Si substrate 101 by a selective oxidation method, an n-type diffusion layer 103 is formed by an ion implantation method.
On top of this, a B concentration of 1.0 mol% and a P concentration of 300 nm
A 4.0 mol% boron-phosphorus glass film (BPS)
G film) 104c, and then formed at 850 ° C., 20
Heat treatment for a minute. Subsequently, after an interlayer connection hole 105b is opened in the BPSG film 104c, as shown in FIG. 5B, a TiN film 106a having a thickness of 100 nm and a
m Cu film 107a is formed by sputtering,
_A dry etching is performed with _three gases to form Cu / TiN wiring. Further, as shown in FIG.
A PSG film 108b having a P concentration of 1.2 mol% is formed by a CVD method, and an interlayer connection hole 105c is opened. continue,
As shown in FIG. 5D, a TiN film 106c having a thickness of 100 nm is formed.
And a Cu film 107b having a thickness of 500 nm are formed by sputtering, and dry-etched with BCl ₃ gas to form Cu / T
A PSG film 108c having a thickness of 1000 nm and a P concentration of 1.2 mol% is formed thereon as an iN wiring.

An n-type diffusion layer formed by this method and Si
When the leakage current of the pn junction formed with the substrate was measured, characteristics equivalent to those of the Al-Si electrode were obtained. Also,
In this approach, SiO _2, S deposited with SiO ₂ or a plasma CVD method and the PSG film is deposited by Subatta method
This indicates that P ions may be implanted into iN or SiON or annealing may be performed in a POCl ₃ atmosphere, or a laminated structure of a silicon resin containing 4 mol% of P and a SiO ₂ film containing no P may be used.

Japanese Patent Application Laid-Open No. 7-176612 proposes a semiconductor device for preventing oxidation of the Cu wiring surface, suppressing an increase in connection resistance, and increasing the speed of circuit operation, and a method of manufacturing the same. Have been. FIG. 6 is a sectional view of the process. First, as shown in FIG.
An Si oxide film 104a having a thickness of about 500 nm is formed on the O.01, and a 50 nm thick Ti film 10
6f, a 100 nm thick TiN film 106a, a thickness of about 80
A Cu film 107a having a thickness of 0 nm is sequentially formed by a sputtering method, and the Cu film, the TiN film, and the Ti film are etched by a conventional method to form wiring. Further, as shown in FIG. 6B, a fluorine (F) -containing Si
The oxide film 108e is made of triethoxyfluorosilane (FSi
Plasma CVD using (OC ₂ H ₅ ) ₃ )) and O ₂ as source
The pressure is 10 Torr and the substrate temperature is 50 ° C., and then a silanol solution is applied. Then, the vapor of triethoxyfluorosilane is diffused to a thickness of about 30 μm.
A 0 nm fluorine-containing spin-on-glass film 110c is formed. Subsequently, as shown in FIG.
After the formation of the second F-containing Si oxide film 110d, an interlayer connection hole is opened, and the Ti film 106g, the TiN film 106c, and the Cu film 107 on the second layer are formed by using the same technique as the first layer.
A Cu wiring composed of b is formed.

According to the technique disclosed in this publication, the formation of the insulating film on the Cu wiring is performed at a temperature lower than the oxidation temperature of Cu, and the relative dielectric constant of the insulating film is lower than that of the conventional Si oxide film.
High yield and good electrical characteristics can be obtained. Further, the publication discloses a technique for forming a sidewall of a Ti-containing tungsten film (hereinafter, Ti-W film) on a side wall of a Cu wiring to protect the Cu wiring, and using a supersaturated aqueous hydrofluoric acid solution. There is also described a method of selectively forming an F-containing Si oxide film having a thickness of about 900 nm only in a gap between Cu wirings at a temperature lower than the Cu oxidation temperature of 35 ° C. by a liquid phase growth method.

On the other hand, in Japanese Patent Application Laid-Open No. 63-299250, Hoshino proposed a surface protection method for Cu wiring. FIG. 7 is a sectional view of the process. First, as shown in FIG. 7A, a Ti film 106f, a TiN film 106a, and a Cu film 10 are formed on the Si oxide film 104a on the Si substrate 101.
7a are sequentially formed, and the Cu film 107a is first patterned thereon, and T
The iN film 106a and the Ti film 106f are patterned to form C
A u wiring is formed. Subsequently, as shown in FIG.
One Si film 109d is formed on the Si oxide film 104a including the wiring.
Accumulate to a thickness of 0 to 50 nm. Further, as shown in FIG. 7C, when heat treatment is performed at 800 ° C. to 1000 ° C. in an O ₂ atmosphere, a portion of the Si film 109d in contact with Cu diffuses into Cu to become a Cu—Si alloy. In addition, the Cu-Si alloy incorporates O ₂ by O ₂ in the atmosphere to form SiO _2.
As a result, Cu-SiO ₂ alloy 107d is formed, and SiO ₂ enters the crystal grain boundaries of Cu to prevent oxidation of Cu. At this time, the Si film in the region not in contact with Cu is O ₂
To form an Si oxide film.

[0009]

Among the various conventional techniques described above, the method of Takewaki et al. Shown in FIG. 3 forms Cu silicide around the wiring, so that the oxidation resistance, corrosion resistance, There is an effect of improving the electromigration resistance, and there is no need to use a Si nitride film for the interlayer insulating film, so that the interlayer capacitance does not increase. However, the wiring resistance depends on the specific surface area of the high-resistance Cu silicide layer with respect to the surface area of the entire wiring, so that the ratio of the surface area to the volume of the wiring increases as the wiring becomes finer. Therefore, the finer the wiring, the higher the rate of increase in the wiring resistance, and the characteristics of the semiconductor device deteriorate. In this case, there is no merit of using Cu having a low resistance for the main conductive layer of the wiring. Also,
Since the reaction between Cu and SiH ₄ is relatively fast, its control is not easy. Therefore, it is difficult to control the thickness of the silicide,
There is also a problem that it is difficult to obtain a uniform wiring resistance in a wafer surface or a lot, and it is difficult to obtain a semiconductor device having stable electric characteristics.

The method of Miyazaki et al. Shown in FIG.
Since a Si oxide film-based protective film is formed on the side wall of the wiring at the time of wiring etching, and a Si oxide film is formed on the Cu wiring using a TEOS source, Cu oxidation during the formation of the insulating film can be suppressed and the wiring resistance can be reduced. Hardly increases. In addition, there is no delay due to an increase in interlayer capacitance. However, the protective film on the side wall of the Cu wiring has low thermal stability formed under a non-equilibrium state during plasma etching of the conductive film,
It does not have high Cu diffusion preventing ability. Furthermore, TE
The Si oxide film formed by the plasma CVD method of the OS source does not have a high barrier property against Cu, and diffusion and oxidation of Cu progress due to multiple heat treatments performed when the wiring is multilayered. There is a possibility that a current leak failure and an increase in wiring resistance may occur, and there is a problem that it is difficult to obtain a high production yield and long-term reliability.

Although the diffusion of Cu by an insulating film containing P such as a PSG film as shown in FIG. 5 is effective, the PSG film formed by the CVD method has a step coverage (step coverage). ) Is poor, and application to a fine wiring space is impossible. Further, Cu by P ion implantation or POCl ₃ atmosphere annealing to such Si oxide film
The formation of the diffusion prevention insulating film has a serious problem in the manufacturing process. For example, it takes a very long implantation time and cost to implanting P ions at a concentration close to the mol Order, also requires heat treatment at high temperatures in P introduced from POC1 ₃ atmosphere, the influence of the transistors and wiring Is concerned.
Even when forming a laminated structure of a silicone resin containing 4 mol% of P and a SiO ₂ film containing no P, the silicone resin is compared with an inorganic insulating film in terms of heat resistance, fine workability, moisture resistance, and the like. Therefore, there arises a problem in a wiring multi-layering process and a long-term reliability of the semiconductor device.

Further, the method of Honma shown in FIG. 6 uses triethoxyfluorosilane (FSi (OC ₂ H ₅ ) ₃ ) and O ₂
In order to form an insulating film having a low dielectric constant below the oxidation temperature of Cu using a plasma CVD method or diffusion of triethoxyfluorosilane vapor with a source of, the insulating film can be formed without oxidizing Cu, The insulating film itself has C
There is no barrier property to u, and since it is formed at a low temperature, the stability is poor. For this reason, there is a concern that diffusion of Cu due to heat treatment performed during the manufacturing process after the formation of the insulating film, deterioration in characteristics of the semiconductor device due to moisture absorption, and deterioration in long-term reliability may occur. In this case, a method of covering the wiring side wall with a Ti-W film by anisotropic etch-back after depositing a metal (Ti-W alloy) film and then forming an insulating film is a method capable of solving the above-mentioned problem, In a space between wirings, a short circuit between wirings due to the remaining Ti-W film may occur, and it is difficult to obtain a high manufacturing yield.

Also, as in the Hoshino method shown in FIG.
The method of depositing a Si film on Cu and performing heat treatment to form a reaction layer cannot be applied in the wiring process because the heat treatment temperature is as high as 800 ° C. to 1000 ° C. Also, Cu-SiO
_{Since the two} alloys are formed, there is a problem that the resistance of the wiring increases as in the method of Takewaki et al., And the merit of using Cu having a small electric resistance as the wiring material is lost.

An object of the present invention is to improve the oxidation resistance of a Cu wiring and prevent diffusion of Cu into an insulating film while preventing an increase in the electrical resistance of the Cu wiring, thereby improving the long-term reliability of a semiconductor device. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can improve a manufacturing yield.

[0015]

According to the present invention, there is provided a process for forming a first insulating film on a semiconductor substrate, and forming a metal wiring comprising a single layer or a plurality of conductive films on the first insulating film. And forming a second insulating film on the first insulating film and the metal wiring at a temperature lower than an oxidation temperature of the metal wiring, and the second insulating film has an ability to prevent diffusion of the metal. Introducing an impurity by a plasma doping method. Further, as the metal wiring, it is possible to adopt a technique of forming a wiring forming groove on the first insulating film and forming a metal wiring composed of a single layer or a plurality of conductive films in the wiring forming groove. Further, the method is characterized in that a step of forming a third insulating film on the second insulating film is provided.

Here, the metal wiring preferably has a main conductive layer made of copper or an alloy containing copper as a main component. The second insulating film is formed of a silicon oxide film or a fluorine-containing silicon oxide film; the deposition of the second insulating film is performed at a temperature lower than the oxidation temperature of copper;
Preferably, the insulating film is deposited by chemical vapor deposition using high-density plasma, and the second insulating film is deposited by plasma chemical vapor deposition using tetraethoxysilane or triethoxyfluorosilane as a source. .
In this case, the impurity introduced into the second insulating film is composed of one or more of phosphorus (P), boron (B), arsenic (As), lead (Pb), and nitrogen (N). Preferably, the impurity is introduced into the second insulating film by a plasma doping method. Further, it is preferable that the third insulating film is composed of a silicon oxide film, a fluorine-containing silicon oxide film, an organic compound or carbon.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, a Si substrate 101 is formed on a Si substrate 101 as a first insulating film.
The oxide film 104a is formed to a thickness of about 500 nm by, for example, a thermal oxidation method or a plasma CVD method using SiH ₄ and nitrous oxide (N ₂ O) or TEOS and O ₂ . The first insulating film 104a is not limited to the Si oxide film, and other than this, phosphorus (P) or polon (B)
Or a PSG film or a BPSG film, or an organic film such as polyimide. Further, the forming method is not limited to the thermal oxidation method or the plasma CVD, and a coating method or the like may be used.

Subsequently, as a metal film, a titanium nitride film (hereinafter, referred to as TiN film) 106a is formed by a reactive sputtering method using a titanium (Ti) target to a power of 2.5 to 2.5.
5.0 KW, 25 to 5 under conditions of pressure 2 to 10 mTorr
It is formed to a thickness of 0 nm. Further, a Cu film 107a is formed on the TiN film 106a by sputtering to a power of 2.0 to
Under conditions of 5.0 KW and pressure of 2 to 10 mTorr, 25
It is formed to a thickness of 0 to 500 nm. Then, the Cu film 10
7A, a TiN film 106b is formed to a thickness of 25 to 50 nm under the same conditions as for the TiN film 106a. Thus, a laminated film of the Cu film and the TiN film is formed.

Here, the TiN film 10 as the metal film is used.
6a and 106b are Cu films 107a which are main conductive layers of wirings
This embodiment is formed for the purpose of preventing oxidation of Cu and diffusion of Cu into the insulating film, and ensuring adhesion between the insulating film and the underlying insulating film. Is not limited to TiN film such as
i), vanadium (∨), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), and silicides and borides thereof , Nitrides, carbides, and alloys containing these can be used.
Also, the Cu film 107a may be made of a Cu alloy containing Cu as a main component to which other elements are added for the purpose of improving characteristics. Then, the TiN film 106b and the Cu film 1 are formed by a conventional method.
07a and the TiN film 106b are etched to form a wiring pattern.

Next, as shown in FIG. 1B, TEO is formed on the Si oxide film 104a and the wiring having the above-mentioned laminated structure.
By a plasma CVD method using S as a source, an approximately 20 to 50 nm thick Si oxide film 104b as a second insulating film is deposited. In this step, the oxidation rate of Cu is extremely slow due to the presence of TEOS. However, it is desirable that the deposition be performed at least at a temperature lower than the oxidation temperature of Cu. In addition, electron cyclotron resonance (elct) is used as a plasma source.
A high-density plasma generated by ron cyclotron resonance or the like may be used, SiH ₄ and O ₂ may be used as a CVD source, and the Si oxide film 104b may be deposited at a temperature lower than the oxidation temperature of Cu. The formation of a glass film is also possible. Further, the type of the film to be deposited is not limited to the Si oxide film.
An i-oxide film may be used.

Subsequently, the Si substrate 101 is exposed to a phosphine (PH ₃ ) gas plasma in a vacuum apparatus (not shown). When the PH ₃ plasma treatment is performed, for example, by single-wafer treatment, the PH ₃ gas flow rate is 20 to 50 sccm,
The process is performed under the conditions of a temperature of 150 to 400 ° C., a pressure of 0.1 to 10 Torr, a power of 0.2 to 1.0 kW, and a processing time of 1 to 5 minutes. Thereby, as shown in FIG. 1C, phosphorus (P) of 10 ¹⁹ to 10 ²¹ atoms / cm ³ is introduced into the Si oxide film 104b. Next, heat treatment is performed in an inert atmosphere such as nitrogen gas at 300 to 400 ° C. for about 10 to 30 minutes. Then, although depending on the PH ₃ plasma processing conditions, the P atoms introduced into the Si oxide film 104b are stabilized, and the Si oxide film 104b has the impurity-containing Si oxide film 108 having the same or similar characteristics as the PSG film.
a. Therefore, this impurity-containing Si oxide film 108
a has the ability to prevent the diffusion of Cu atoms. Thereby, Cu
A structure is obtained in which the exposed portion of Cu of the wiring having the main conductive layer is in contact with an insulating film having a Cu diffusion preventing ability. Here, P is used as an impurity element for performing plasma doping.
However, the present invention is not limited to this, and one or more of boron (B), arsenic (As), lead (Pb), and nitrogen (N) may be used. .

Subsequently, as shown in FIG. 1D, for example, plasma CVD is performed on the impurity-containing Si oxide film 108a.
The silicon oxide film 110a as the third insulating film is
It is formed to a thickness of 0 to 1000 nm. This third insulating film is not limited to the Si oxide film either, and has a small relative dielectric constant and is effective for suppressing circuit delay.
An i-oxide film, an organic compound film, or a carbon film may be used, and the deposition method is not limited to the plasma CVD method. Since the semiconductor device formed in this manner has a structure in which the Cu exposed portion of the wiring is in contact with the insulating film having the ability to prevent Cu diffusion, diffusion and oxidation of Cu can be prevented. Also, the manufacturing method is very easy. (Second Embodiment) FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG.
Thickness 1000-1 as a first insulating film on a Si substrate 101
A 500 nm Si oxide film 104a is formed by a plasma CVD method, and subsequently, a width of 250 to 1 is formed using a conventional photolithography technique and a reactive ion etching technique.
000 nm, depth 250-500 nm wiring groove 105a
To form Here, the first insulating film is not limited to the Si oxide film, and may be a PSG film or BPSG film in which phosphorus (P) or polon (B) is contained in the Si oxide film.
It may be a membrane. Also, the forming method is not limited to the thermal oxidation method or the plasma CVD method.

Further, as shown in FIG.
Using a titanium target as the TiN film 106a
By the reactive sputtering method, a power of 2.5 to 5.0 KW,
10-30 nm thickness under pressure 2-10 mTorr
Formed. This TiN film 106a is also an embodiment of the first invention.
Other materials can be used as in the embodiment. Then
Cu (HFA) (TMVS) on the TiN film 106a
(Copper Hexa Fluoro Ayet
hylacetonate Tri-Methyl V
inyl Silane Cu (C_FiveHF₆O_Two) (C_FiveH
₁₂Organic source Cu-CVD method using Si)) as a raw material
To form a Cu film 107a having a thickness of 500 to 1000 nm.
Then, the wiring groove 105a is formed by the TiN film 106a and the Cu film 107.
a. Cu-CVD is a raw material source
20-50 sccm, carrier H _TwoGas 50-200s
ccm, temperature 150-250 ° C, pressure 5-20Pa
In this case, the Cu film 1 has a smooth and high step coverage.
07a can be formed.

Then, as shown in FIG. 2C, a chemical mechanical polishing method (Chemi) using a slurry containing alumina (Al ₂ O ₃ ) fine powder and hydrogen peroxide (H ₂ O ₂ ) as main components.
cal Mechanical Polishing,
Hereinafter, the Cu film and the TiN film exposed in portions other than the wiring grooves are polished and removed by a CMP method to form a Cu wiring having a groove filling structure composed of the TiN film 106a and the Cu film 107a. Subsequently, as shown in FIG. 2D, a second insulating film having a thickness of about 20 is formed on the Si oxide film 104a and the Cu wiring by plasma CVD using TEOS as a source.
An Si oxide film 104b of about 50 nm is deposited. In this step, the oxidation rate of Cu in the exposed portion becomes extremely slow due to the presence of TEOS, but it is desirable to deposit at least a temperature lower than the oxidation temperature of Cu. In addition, electron cyclotron resonance (select) is used as a plasma source.
Using a high-density plasma generated by ron cyclotron resonance, etc., using SiH ₄ and O ₂ as a CVD source, the Si oxide film 104b may be deposited at a temperature lower than the oxidation temperature of Cu, or by a coating method. It is also possible to form a spin-on-glass film. Furthermore, the type of film to be deposited is not limited to the Si oxide film,
In addition, a Si oxide film containing fluorine (F) and having a small relative dielectric constant may be used.

Further, as shown in FIG. 2E, the Si substrate 101 is exposed to plasma of arsine (AsH ₃ ) gas in a vacuum apparatus (not shown). When the AsH ₃ plasma processing is performed by, for example, single-wafer processing, the AsH ₃ gas flow rate is 20 to 50 sccm, the temperature is 150 to 400 ° C., the pressure is 0.1 to 10 Torr, the power is 0.2 to 1.0 KW,
The processing is performed under the conditions of a processing time of 1 minute to 5 minutes. Then, critical atoms (As) of 10 ¹⁹ to 10 ²¹ atoms / cm ³ are introduced into the Si oxide film 104b. Next, when a heat treatment is performed in an inert atmosphere such as nitrogen gas at 300 to 400 ° C. for about 10 to 30 minutes, As atoms introduced into the Si oxide film 104b depend on AsH3 plasma processing conditions. After the rearrangement and stabilization, the Si oxide film 104b becomes a critical glass (ASG: Arsen Silicate Glass).
s) An impurity-containing Si oxide film 108a having the same or similar characteristics as the film is obtained, and has the ability to prevent diffusion of Cu atoms. As a result, a structure is obtained in which the exposed region of Cu existing on the surface of the trench wiring having Cu as the main conductive layer is in contact with the insulating film having the ability to prevent Cu diffusion.

Subsequently, as shown in FIG. 2F, for example, plasma CVD is performed on the impurity-containing Si oxide film 108a.
The silicon oxide film 110a as the third insulating film is
It is formed with a thickness of 0 to 1000 nm. This insulating film is also Si
It is not limited to an oxide film, but has a small relative dielectric constant,
Si containing fluorine (F), effective for suppressing circuit delay
An oxide film, an organic compound film, or a carbon film may be used, and the deposition method is not limited to plasma CVD injection.
Since the semiconductor device formed in this manner has a structure in which the Cu exposed portion of the wiring is in contact with the insulating film having the ability to prevent Cu diffusion, diffusion and oxidation of Cu can be prevented. Also,
As in the first embodiment of the present invention, the manufacturing method is extremely easy.

Here, the method of manufacturing the semiconductor device shown in each of the first and second embodiments can be applied to any type of semiconductor device such as a MOS type or a bipolar type.

[0028]

As described above, the method of manufacturing a semiconductor device according to the present invention comprises introducing an impurity having a capability of preventing Cu diffusion into an insulating film covering a wiring containing Cu as a main conductive material. The region where the Cu of the wiring is exposed is Cu.
A structure that comes into contact with an insulating film with high diffusion prevention ability can be formed.
Highly controllable, high controllability of Cu wiring with a structure in which the periphery of the wiring is covered with a barrier film and Cu silicide effective for preventing Cu oxidation, preventing Cu diffusion, improving Cu electromigration resistance and stress migration resistance. It can be formed with uniformity and high reproducibility. Thereby, even when an insulating film such as a Si oxide film having a lower relative dielectric constant than the Si nitride film but having a possibility of oxidizing Cu is formed on the Cu wiring, Cu is not oxidized, and C
The long-term reliability of the u wiring is improved. Furthermore, even when heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability can be manufactured with high yield.

[Brief description of the drawings]

FIG. 1 is a vertical cross-sectional view showing steps of a first embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing a process according to a second embodiment of the present invention.

FIG. 3 is a longitudinal sectional view showing a step of the first conventional technique.

FIG. 4 is a longitudinal sectional view showing a process of the second conventional technique.

FIG. 5 is a longitudinal sectional view showing a step of the third conventional technique.

FIG. 6 is a longitudinal sectional view showing a process of a fourth conventional technique.

FIG. 7 is a longitudinal sectional view showing a step of the fifth conventional technique.

[Explanation of symbols]

 101 Si substrate 104a Si oxide film 106a, 106b Ti film 107a Cu film 108a Impurity-containing Si oxide film 110a Si oxide film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/316 H01L 21/90 J 21/3205 21/88 M

Claims (10)

[Claims] A step of forming a first insulating film on a semiconductor substrate; a step of forming a metal wiring composed of a single layer or a plurality of conductive films on the first insulating film; Forming a second insulating film on the film and the metal wiring at a temperature lower than an oxidation temperature of the metal wiring;
Introducing an impurity capable of preventing metal diffusion of the metal wiring into the insulating film by a plasma doping method. 2. A step of forming a first insulating film on a semiconductor substrate, a step of opening a wiring forming groove on the first insulating film, and a step of forming a single or a plurality of conductive films in the wiring forming groove. Forming a metal wiring to be formed, forming a second insulating film on the first insulating film and the metal wiring at a temperature lower than an oxidation temperature of the metal wiring, and forming the second insulating film on the second insulating film. Introducing an impurity capable of preventing metal diffusion of the metal wiring by a plasma doping method. 3. The method according to claim 1, further comprising the step of forming a third insulating film on the second insulating film. 4. The method according to claim 1, wherein the main conductive layer of the metal wiring is made of copper or an alloy containing copper as a main component. 5. The method according to claim 1, wherein the second insulating film is formed of a silicon oxide film or a fluorine-containing silicon oxide film. 6. The method according to claim 5, wherein the deposition of the second insulating film is performed at a temperature lower than the oxidation temperature of copper. 7. The method according to claim 6, wherein the deposition of the second insulating film is performed by chemical vapor deposition using high-density plasma. 8. The method according to claim 7, wherein the deposition of the second insulating film is performed by plasma-enhanced chemical vapor deposition using tetraethoxysilane or triethoxyfluorosilane as a source. 9. The method according to claim 1, wherein the impurity introduced into the second insulating film comprises one or more of phosphorus (P), boron (B), arsenic (As), lead (Pb), and nitrogen (N). 9. The method of manufacturing a semiconductor device according to claim 5, wherein the method comprises: 10. The method of manufacturing a semiconductor device according to claim 3, wherein said third insulating film is made of a silicon oxide film, a fluorine-containing silicon oxide film, an organic compound or carbon.