JP2001102456A - Semiconductor storage element - Google Patents

Semiconductor storage element

Info

Publication number
JP2001102456A
JP2001102456A JP27340499A JP27340499A JP2001102456A JP 2001102456 A JP2001102456 A JP 2001102456A JP 27340499 A JP27340499 A JP 27340499A JP 27340499 A JP27340499 A JP 27340499A JP 2001102456 A JP2001102456 A JP 2001102456A
Authority
JP
Japan
Prior art keywords
well
gate
drain
semiconductor memory
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27340499A
Other languages
Japanese (ja)
Other versions
JP3275893B2 (en
Inventor
Tomohiro Tsuchiya
智裕 土屋
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP27340499A priority Critical patent/JP3275893B2/en
Publication of JP2001102456A publication Critical patent/JP2001102456A/en
Application granted granted Critical
Publication of JP3275893B2 publication Critical patent/JP3275893B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell

Abstract

PROBLEM TO BE SOLVED: To provide a reliable semiconductor storage element wherein a data can be written by preventing the effect to other circuits with no increase in chip area of a memory LSI. SOLUTION: An n-type substrate 1 is grounded with an n-type well 2 formed on its surface. The well 2 is connected to a power source terminal Vcc, at a position not shown in the Fig. by an n-type diffusion layer 7 formed on the surface, with a p-type well 3 which is shallower than the well 2 formed on the surface. On the surface of well 3, a p-type diffusion layer 6 as well as a source 4 and a drain 5 of the n-type diffusion layer are formed. A gate insulating film 8 is formed on the surface of well 3. A gate electrode 11 is formed on the surface of the gate insulating film 8. An interlayer insulating film 9 is formed on the surfaces of the well 3, diffusion layer 6, gate electrode 11, source 4, and drain 5. A wiring 10 of a conductor film is formed on the surface of interlayer insulating film 9, and the wiring 10 forms a short circuit at the source 4, drain 5, and diffusion layer 6 through a contact C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a MOS (metal oxide semiconductor) transistor as an antifuse.

[0002]

2. Description of the Related Art Generally, a fuse element is in a conductive state in an initial stage, and becomes non-conductive by performing some processing. On the other hand, the anti-use element is in a non-conductive state in an initial stage, and is made conductive by performing some processing.

[0003] Conventionally, in order to replace a failed memory element at the time of manufacturing a large-capacity memory LSI (large-scale integrated circuit), redundancy for replacing a failed memory element with a spare memory element is provided. Circuit is ready. In this redundancy circuit, a fuse is used to replace the memory element, that is, to change the address data between the area of the failed memory element and the element area to be replaced.

As the fuse, a polycrystalline silicon resistor or the like is used. By cutting the polycrystalline silicon with a laser, data of an address indicating the area of the failed memory element and the element area to be replaced can be changed. However, in polycrystalline silicon, a certain area is required to obtain a predetermined resistance value, so that the chip area of the memory LSI increases. In the case of performing a cutting process by using a laser, it is necessary to secure a sufficient space around the polycrystalline silicon in order to prevent an influence on other circuits and transistors.
This is an element that increases the chip area of I.

[0005] The fuse is usually set in a non-conductive state by destroying a fuse forming region with a laser or the like. For this reason, the fuse cutting operation can be performed at the stage when the memory element is formed on the wafer, but cannot be performed after the memory element is incorporated in a package or the like. In order to solve such a problem, even after incorporating the semiconductor device into the package,
A structure for electrically cutting a fuse element or an anti-fuse element is known.

For example, the setup time of a semiconductor device may not be able to capture input data even if it has a variation of about several ns as its operating speed becomes as high as several OO MHz. In order to prevent such a problem, usually, the setup time is adjusted so as to be within the standard range at the stage of the shipping inspection. The set-up time cannot be inspected by the die sort test at the wafer stage because the output impedance changes from the wafer state by being incorporated in the package. Therefore, a setup time is measured after sealing the semiconductor device in a package, and a desired setup time is set by cutting / connecting a fuse / anti-fuse formed in the semiconductor device in advance.

As another application, a programmable logic array (PLA) is known. PLA
Are provided to a user by sealing a package of antifuse elements arranged in a matrix. The user electrically writes an anti-fuse element in the PLA so as to obtain a predetermined output pattern with respect to a predetermined input pattern, thereby realizing a desired function (program).

Therefore, it is conceivable to use a MOS transistor as an antifuse instead of a polycrystalline silicon resistor. MO instead of resistors such as polycrystalline silicon
By forming the anti-fuse by the S transistor, the formation area of the anti-fuse is reduced, and the memory LS
It is possible to reduce the chip area of I. Here, data writing is performed by cutting the antifuse formed by the resistance of the polycrystalline silicon.
The anti-fuse formed by the OS transistor destroys a gate insulating film and data is written by increasing a leak current between a gate and a channel or between a gate and a source (or a drain).

FIG. 3 shows a configuration of a first MOS transistor (first conventional example) serving as an antifuse. FIG. 3 is a sectional view of the first MOS transistor. In this figure, reference numeral 100 denotes an n-type substrate, and a source 101 and a drain 102 are formed on the surface by a p-type diffusion layer. A gate insulating film 103 is formed on the surface of the substrate 100, the source 101 and the drain 102.
Is provided. On the surface of the gate insulating film 103, a gate electrode 105 is provided by a conductor such as a metal film.

The gate insulating film 103 is formed on the drain 1
In the upper region 104 of the semiconductor device 02, the thickness is reduced (anti-fuse region). By applying a predetermined voltage between the gate electrode 105 and the drain 102, a high electric field is generated in the thin portion of the region 104 to destroy the gate insulating film 103, and thereby the gate electrode 105 and the drain 102 are broken. Are written and data is written (Japanese Patent Application No. 7-294481).

Also, a second MOS serving as an antifuse is provided.
FIG. 4 shows a configuration of a transistor (second conventional example). FIG. 4 is a sectional view of the second MOS transistor. In this figure, 200 is a p-type substrate, and n
A mold well 201 is formed on the surface. On the surface of the well 201, a source 202 and a drain 203 are formed on the surface by an n + type (higher n-type impurity concentration than the well 201) diffusion layer. A gate insulating film 204 is provided on the surface of the substrate 200, the source 202, and the drain 203. On the surface of the gate insulating film 204, a gate electrode 205 is provided by a conductor such as a metal film. Then, data is written by melting the gate electrode 205 and the well 201 by the heat of laser irradiation and connecting the gate insulating film 204 by breaking the gate insulating film 204 (Japanese Patent Application Laid-Open No. 11-50206).
8).

[0012]

However, in the first MOS transistor described above, the gate insulating film 103 in the region 104 above the drain 102 needs to be formed thinner than the other regions. Therefore, a special process is required to change the thickness of the gate oxide film 103, and a high-precision process such as forming the gate oxide film 103 separately from the region 104 and other regions is added to the manufacturing process. There is a problem that the manufacturing cost increases.

In the first MOS transistor, since the thickness of the gate oxide film 103 is partially changed,
There is also a disadvantage that the reliability of the film quality is reduced and the gate electrode 105 and the drain 102 are connected from the time of manufacture.

Here, an antifuse using a MOS transistor needs to satisfy the following conditions. a. The write voltage of the MOS transistor of the antifuse is in a predetermined range. The antifuse must not be destroyed by a normal power supply voltage, nor should it be destroyed by applying a predetermined program (write) voltage. . Therefore, the thickness of the gate oxide film must be controllable so that the gate oxide film can be destroyed within a predetermined write voltage range.

B. Other transistors are not destroyed when writing to the anti-fuse MOS transistor. A writing circuit for controlling writing and a reading circuit for detecting a writing state are connected to the antifuse. During the writing process, a high program voltage may be applied to these circuits. For this reason, if the program voltage becomes too high, the breakdown voltage of the elements constituting these circuits is increased, and a protection circuit or the like is required, resulting in an increase in chip size. Therefore, it is desirable that the program voltage for the antifuse is as low as possible.

C. It is possible to read information written in the MOS transistor. When the gate oxide film is destroyed and the leak current is below the detection limit, it does not become an antifuse. Conversely, when the gate oxide film is not destroyed, it does not become an antifuse even if the leak current is higher than the detection limit. Therefore, the anti-fuse before the writing process has a small leak current to confirm that the anti-fuse is in a non-conductive state, and the anti-fuse after the writing process has such a leak current that it can be confirmed to be in a connected state. It is necessary to flow.

D. Does not affect circuits other than the anti-fuse at the time of writing. During the writing process, the program voltage affects the bias potential of the substrate, or noise generated at the time of writing affects other circuits in the semiconductor device. Not be. For example, when a plurality of antifuses X and Y are formed in one semiconductor device, a writing circuit for writing the antifuses X is formed. The write circuit applies a predetermined bias voltage to the other end of the antifuse before applying the program voltage to one end of the antifuse, and determines whether to connect the antifuse.

Whether or not to connect an anti-fuse is determined based on information externally input to a register or the like. When writing the antifuse X, if the write information of the antifuse X itself is rewritten and not written, or if the write information of the antifuse Y is rewritten and written to the antifuse Y, No. Such a phenomenon becomes a serious problem when the semiconductor device is miniaturized and the anti-fuse element region and another circuit region are arranged close to each other.

Therefore, the first conventional example shown in FIG.
In the MOS transistor described above, further miniaturization and lowering of the voltage have progressed, and when the thickness of the gate insulating film 1O3 is reduced, the gate insulating film 1O3 may be broken by the voltage applied to the normal gate, and the above conditions a. And the design of the write circuit and the read circuit becomes difficult. Further, if the undesired antifuse is destroyed, it becomes impossible to know which antifuse has destroyed the gate insulating film of the MOS transistor and written data, and as a result, the condition shown in the above c is satisfied. However, the condition that the written information can be read cannot be satisfied.

Next, the second MO shown in the second conventional example will be described.
In the S transistor, the gate insulating film 204 is melted by a laser, the gate electrode 205 and the well 201 are electrically connected to each other, and data is written. Therefore, the gate electrode needs to be formed to have a size that can be irradiated with the laser. However, there is a disadvantage that the formation area cannot be reduced so much.

Further, the second MOS transistor irradiates the laser to the gate insulating film 204 via the gate electrode 205 and melts it, so that the gate electrode 205 of the other transistor is irradiated with the laser. The splash of material flies due to the energy at the time of melting, short-circuits with the signal line,
There is a problem that the reliability of other circuits is reduced.

Furthermore, since the second MOS transistor cannot electrically perform writing, the second MOS transistor must satisfy the condition a described above, that is, the condition that the writing voltage is within a predetermined range. Therefore, the condition that destruction (writing) of the antifuse cannot be performed after sealing in a package cannot be satisfied. In the first conventional example and the second conventional example, the condition d. That is, there is no disclosure of the effect on other circuits during the writing process.

The present invention has been made under such a background, and it is possible to electrically write data with high reliability without increasing the chip area of the memory LSI and without affecting other circuits. It is to provide a possible semiconductor storage element.

[0024]

According to the first aspect of the present invention,
In a semiconductor memory device having a MOS structure used as an antifuse, a semiconductor substrate (for example, substrate 1 of one embodiment), a well formed on the surface of the semiconductor substrate (for example, well 3 of one embodiment), and this well A MOS transistor (for example, a semiconductor element S of one embodiment) formed therein, and the well;
A source and a drain of the MOS transistor are electrically short-circuited to form a first electrode, and a gate of the MOS transistor is formed to a second electrode.

According to a second aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein a conductive property opposite to that of the well is provided between the well (for example, well 3 in one embodiment) and the semiconductor substrate. It is characterized by having a second well (for example, well 2 of one embodiment).

According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the gate of the MOS transistor (for example, the semiconductor element S in one embodiment) and the well (for example, one Well 3),
Applying a high electric field between the source and the drain,
Data is written by destroying a gate oxide film of the MOS transistor and short-circuiting the gate and any of the well, the source, and the drain.

According to a fourth aspect of the present invention, in the semiconductor memory device according to any one of the first to third aspects, the wiring is set to a ground potential, and writing is performed by applying a high voltage to the gate. It is characterized by the following.

According to a fifth aspect of the present invention, in the semiconductor memory device according to any one of the first to third aspects, the gates of the plurality of antifuses are connected in common, the wiring is set to a ground potential, and Writing is performed by applying a high voltage to the wiring, the wiring is set to a power supply potential or a writing potential, and writing is not performed by applying a high voltage to the gate.

According to a sixth aspect of the present invention, in the semiconductor memory device according to any one of the first to third aspects, a predetermined potential is applied to the wiring, and the potential of the wiring is detected after a lapse of a predetermined time. Thereby, the stored information of the antifuse is read.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a semiconductor storage element S according to one embodiment of the present invention. In this figure, a p-type substrate 1 is grounded,
An n-type well 2 is formed on the surface. Well 2 is an n + type diffusion layer 7 (well contact) formed on the surface.
At a position (not shown), the program voltage Vp
It is connected to the wiring of p or the power supply voltage Vcc. Also,
On the surface of the well 2, a p-type well 3 whose depth is smaller than that of the well 2
Are formed.

On the surface of the well 3, a p + type diffusion layer 6 is formed.
(Well contact), and a source 4 and a drain 5 as n + type diffusion layers. Source 4
A gate insulating film 8 is formed on the surface of the well 3 between the gate and the drain 5. A gate electrode 11 is formed on the surface of the gate insulating film 8. An interlayer insulating film 9 is formed on the surfaces of the well 3, the diffusion layer 6, the diffusion layer 7, the gate electrode 11, the source 4 and the drain 5. On the surface of the interlayer insulating film 9, a wiring 10 of a conductor film is formed. The wiring 10 electrically short-circuits the source 4, the drain 5, and the diffusion layer 6 (that is, the well 3) via the contact C. The gate electrode 11 is connected to a wiring for connecting to an external terminal at a position (not shown).

Here, the gate insulating film 8 is a silicon oxide film obtained by oxidizing the substrate 1, a silicon oxide film deposited by a method such as CVD (chemical vapor deposition) or sputtering,
It is formed of an insulating film such as a silicon nitride film formed by CVD or sputtering. The gate electrode 11 is made of polycrystalline silicon, refractory metal (molybdenum, titanium, tantalum,
And a material such as silicide or polycide of silicon and a high melting point metal.

Here, the length of the gate electrode 11 is about 0.2.
μm, the width is 10 μm, and the thickness of the gate insulating film 8 is about 5 nm
It was set to 10 nm. Well 3 has 1 × 10 17 atom / cm 3
A p-type impurity, for example, boron is introduced at a concentration of about 1 × 10 18 atom / cm 3 . Well 2 is 1 × 10 17 at
om / cm 3 -1 × 10 18 , atom / cm 3 concentration of n-type impurity,
For example, phosphorus has been introduced. Further, the source 4, the drain 5, and the well contact 6 are ion-implanted with n-type impurities, for example, phosphorus or abrasive at an energy of 50 keV and at a dose of 1 × 10 15 / cm 2 to 5 × 10 15 / cm 2. The well contact 7 is ion-implanted with a p-type impurity, for example, boron at a dose of 1 × 10 15 / cm 2 to 5 × 10 15 / cm 2 .

The wiring 10 is made of a material such as aluminum, high melting point metal (molybdenum, titanium, tantalum, tungsten, etc.), silicide or polycide of silicon and high melting point metal.

Next, an example of the operation of the embodiment will be described with reference to FIGS. FIG. 2 is a conceptual diagram of a circuit that performs writing and reading of the semiconductor storage element S of FIG. FIG.
, The n-channel MOS transistor 24
When the "H" level control signal S3 is input to the terminal T3, the "H" level voltage is applied to the gate, the transistor T is turned on, and the drain 5, source 4 and well 3 of the semiconductor memory element S are grounded. Potential. Further, when the control signal S3 at the “L” level is input to the terminal T3, the voltage at the “L” level is applied to the gate of the MOS transistor 24,
It turns off.

A p-channel type MOS transistor 25
When an "L" level control signal S2 is input to the terminal T2, an "L" level voltage is applied to the gate and the transistor T is turned on, and the drain 5, source 4 and well 3 of the semiconductor memory element S are powered. Potential. When the "H" level control signal S2 is input to the terminal T2, the "H" level voltage is applied to the gate of the MOS transistor 25, and the MOS transistor 25 is turned off, and the drain 5, the source 4 and the The well 3 is electrically disconnected from the terminal T5.

The transfer gate 21 is formed by connecting an n-channel MOS transistor 21n and a p-channel transistor 21p in parallel. When the "L" level control signal S4 is input to the terminal T4, an "L" level voltage is applied to the gate of the n-channel type MOS transistor 21n, so that the n-channel type MOS transistor 21n is turned off. The gate is inverted by the inverter 20 and applied with the “H” level voltage, so that the gate is turned off, and the transfer gate 21 is turned off.

On the other hand, when the "H" level control signal S4 is input to the terminal T4, the "H" level voltage is applied to the gate of the n-channel type MOS transistor 21n, so that the transistor is turned on, and the p-channel type MOS transistor 21n is turned on. The MOS transistor 21p is turned on because a voltage of "L" level inverted by the inverter 20 is applied to the gate of the MOS transistor 21p.
The transfer gate 21 is turned on.

The inverter 22 and the inverter 23 form a latch LT. When the transfer gate 21 is in the ON state, the latch LT is supplied with data to be held from the transfer gate. Then, when the transfer gate 21 is in the off state, the latch LT holds and outputs the data supplied from the transfer gate. At this time, the data output from the latch LT is data at an inverted level of the data supplied from the transfer gate LT. Control signal S1 to control signal S4 described above
Are supplied from a control circuit (not shown).

Next, an operation for writing data to the semiconductor memory element S, that is, an operation for breaking the gate insulating film will be described with reference to FIG. At this time, the "H" level control signal S2 is input to the terminal T2,
The transistor 25 is off. Also, an “L” level control signal S4 is input to the terminal T4,
The transfer gate 21 is off.

A control circuit (not shown) outputs a signal to terminal T3.
The control signal S3 at "H" level is input to the MOS transistor 24 to turn it on. As a result, the drain 5, source 4 and well 3 of the semiconductor memory element S are set to the ground potential. Then, a predetermined write voltage Vpp is supplied as a pulse of a predetermined width from a control circuit or an external terminal (not shown) to the terminal T1. Thereby, in the semiconductor memory element S, the gate electrode 11, the drain 5, the source 4
A high electric field is generated between the gate electrode 11 and the well 3, and the gate insulating film 8 is destroyed, so that the gate electrode 11 is electrically short-circuited with any one of the drain 5, the source 4 and the well 3. Here, for example, the power supply voltage Vcc was 3 V to 5 V, and the write voltage Vpp was 9 V to 15 V.

As a result, data has been written to the semiconductor memory element S. When the write pulse is supplied and the semiconductor memory element S is in the write state, even if the potential of the well 3 fluctuates due to the write, the well 2 is stable unless the potential of the well 3 exceeds the potential of the well 2. The potential (power supply potential: power supply voltage Vcc) serves as a barrier layer, and the potential of the substrate 1 does not change. For this reason, it is possible to prevent adverse effects on operation, such as giving noise to other circuits depending on the potential of the substrate 1.

The semiconductor memory element S shown in FIG.
Even if the drain 5 is not formed, the diffusion layer 6 serving as a well contact can function as an antifuse. However, the p-type well 3 has a low impurity concentration and a high resistivity.
When a current starts to flow due to dielectric breakdown, a voltage drop occurs in the well 3 and energy required for dielectric breakdown of the gate insulating film 8 may not be obtained.

On the other hand, as shown in FIG. 1, a source 4 and a drain 5 are formed in the semiconductor memory element S, and a write voltage Vpp is applied to the gate electrode 11 so that a channel is formed on the substrate surface of the well 3. Is formed, so that voltage does not drop in the well 3 even if a current flows due to dielectric breakdown.
Therefore, the energy required to cause the dielectric breakdown of the gate insulating film 8 can be obtained, and the dielectric breakdown can be reliably performed.

In the second conventional example, since an n + -type source and a drain are formed in an n-type well and a channel is not formed, energy necessary for dielectric breakdown of a gate insulating film is obtained as described above. May not be possible. For this reason, the gate is broken using a laser. Also,
Since the source 4, the drain 5, and the well 3 are connected to the wiring 10, the location of the dielectric breakdown is the gate 11 and the source 4.
1, between the gate 11 and the drain 5, or between the gate 11 and the well 3.
The leak current can be detected through 0.

When the substrate 1 is at the ground potential as in the above-described example, it is desirable to apply a positive high write voltage Vpp to the gate electrode 11 side. Even if the gate insulating eye 8 breaks down and the well 3 momentarily becomes high voltage,
Since the capacitance between the well 3 and the well 2 is sufficiently larger than the capacitance between the gate electrode 11 and the well 3,
The potential difference between well 3 and well 2 is not as large as between gate electrode 11 and well 3. For this reason, no junction breakdown occurs between the well 3 and the well 2.

Also, the gate insulating film 8 can be broken down by applying the write voltage Vpp to the electrode 10 and grounding the gate electrode 11. In this case, if the substrate 1 is at the ground potential, a junction breakdown may occur between the well 3 and the substrate 1. Therefore, it is desirable to apply the present invention to a semiconductor device having a configuration in which the substrate 1 is biased to a power supply potential or the like.

Next, the plurality of semiconductor storage elements S are connected to the terminal T1.
An operation in a case where the other semiconductor storage elements S (not shown) are connected in common and are not desired to be destroyed as shown in FIG. 2 will be described. At this time, the "L" level control signal S2 is input to the terminal T2 and the MOS
The transistor 25 is on. Also, an “L” level control signal S4 is input to the terminal T4,
The transfer gate 21 is off.

A control circuit (not shown) supplies a control signal S
3 is set to the “L” level, or the external terminal is grounded, so that the control signal S3 of the “L” level is supplied to the terminal T3.
To turn off the MOS transistor 24. As a result, the drain 5, source 4, and well 3 of the semiconductor memory element S, that is, the wiring 10 is connected to the power supply potential Vcc.
It is said.

Then, a predetermined write voltage Vpp is supplied as a pulse having a predetermined width to terminal T1 from a control circuit or an external terminal (not shown) to write data to semiconductor memory element S (not shown). At this time, when the semiconductor memory device is formed, the terminal T1 is commonly connected to the plurality of semiconductor memory elements S, so that the write voltage Vpp is also supplied to the semiconductor memory element S shown in FIG. As a result, in the semiconductor memory element S, a potential difference of “Vpp−Vcc” occurs in the gate insulating film 8 between the gate electrode 11 and the drain 5, the source 4 and the well 3.

However, this potential difference “Vpp−Vc”
Since “c” is smaller than the breakdown voltage “Vpp−ground potential”, that is, the write voltage “Vpp”, the gate insulating film 6 is not broken down. Therefore, the gate insulating film 8 in the semiconductor memory element S shown in FIG. 2 other than the object to be written is not broken, and the gate electrode 11 remains electrically insulated from any of the drain 5, the source 4 and the well 3. (A state in which data is not written). Here, for example, the power supply voltage Vcc is 3V to 5V, and the write voltage Vpp is 9V to 15V.
V.

As described above, the plurality of semiconductor storage elements S
On the other hand, a control circuit (not shown)
By supplying the control signal T4, writing / non-writing can be executed at the same time. That is, the semiconductor memory element S to be written is set to a predetermined write state in which a high electric field is applied to the insulating film, and the semiconductor memory element S not to be written is set to a non-write state in which a high electric field is not applied to the insulating film. By setting the state, data can be written only to a specific semiconductor storage element S.

Next, the operation of reading data from the semiconductor memory element S will be described with reference to FIG. At this time, a control circuit (not shown) grounds the terminal T1 or grounds the external terminal to ground the terminal T1. This control circuit outputs an "L" level control signal S3 to the terminal T3, The transistor 24 is turned off. Also,
The control circuit (not shown) outputs an “L” level control signal S4 to the terminal T4 to turn off the transfer gate 21.

A control circuit (not shown) is connected to a terminal T2.
To output the control signal S2 at the “L” level to turn on the MOS transistor 25. Thereby, the terminal T5
(Power supply voltage Vcc), the drain 5 of the semiconductor storage element S,
Source 4 and well 3 are electrically connected via MOS transistor 25, and wiring 10 is precharged to power supply potential Vcc. After that, an “H” level control signal S2 is output to the terminal T2, and the MOS transistor 25 is turned off.

At this time, when data is written in the semiconductor memory element S, any one of the drain 5, the source 4 and the well 3 and the gate electrode 11 are in a dielectric breakdown state, so that the wiring 10 is precharged. The electric charge is discharged through the semiconductor memory element S, and the potential of the wiring 10, that is, the potential of the point A drops to the “L” level (ground potential).

In general, even if the gate insulation 8 is broken down,
The leak current flowing therethrough is very small. When the potential at the point A is detected by utilizing the voltage drop due to the on-resistance of the MOS transistor 25, the size of the MOS transistor 25 is reduced and the drive current smaller than the leak current is reduced. It is necessary to If the leakage current is small, it takes time until the potential at the point A is determined.
There is no problem if it is used for applications that only perform once.

On the other hand, when data is not written in the semiconductor memory element S, leakage to the semiconductor memory element S occurs because all of the drain 5, the source 4 and the well 3 are electrically insulated from the gate electrode 11. Since no current flows and the electric charge precharged to the wiring 10 is not discharged through the semiconductor memory element S, the potential of the wiring 10, that is, A
The potential at the point maintains the “H” level (power supply voltage Vcc).

Then, the control circuit (not shown) outputs an "H" level control signal S4 to the terminal T4 at the timing when the potential at the point A is stabilized, and
Is turned on. Thus, when data is written to the semiconductor memory element S, “L” level data is supplied from the transfer gate 21 to the latch LT.
From the terminal TO, “H” level data inverted by the inverter 22 is output. The “H” level data inverted by the inverter 22 is
The signal is inverted by the inverter 23 and fed back to the input terminal of the inverter 22.

On the other hand, when data is written in the semiconductor memory element S, "H" level data is supplied from the transfer gate 21 to the latch LT. Then, from the terminal TO, “L” level data inverted by the inverter 22 is output. The “L” level data inverted by the inverter 22 is output to the inverter 2
3 and is fed back to the input terminal of the inverter 22.

The control circuit (not shown) includes a latch L
At T, at the timing when data is input and output stably between the inverter 23 and the inverter 24,
An "L" level control signal S4 is output to the terminal T4. As a result, the transfer gate 21 is turned off,
The supply of the data held in the latch LT is lost, but the data supplied from the egg gate 21 is held because the potential of the input terminal of the inverter 22 is stabilized by the output of the inverter 23.

That is, when data is written to the semiconductor memory element S, the latch LT latches the data at the “L” level, outputs an “H” level output signal from the terminal TO, and When data is not written to the terminal TO, the data of “H” level is latched and the terminal TO is latched.
Output an "L" level output signal.

With the circuit configuration described above, the semiconductor device
At the stage of the shipment inspection, the setup time including the parasitic capacitance of the lead frame is measured in a state where the anti-fuse is incorporated in the package, and the antifuse is written / unwritten by the tester so as to have a predetermined setup time. When the user uses the semiconductor device, the semiconductor device operates in a predetermined setup time by reading the write information of the antifuse. The antifuse can also be used for setting the information written in the semiconductor storage device to be prohibited from being rewritten or read by the user.

The semiconductor memory device of the present invention is used not only for the redundancy circuit of the LSI memory as described above, but also for an FPGA (Field Programmable Gate).
It can also be used as an antifuse for writing circuit data such as an Array) and a PLD (Programmable Logic Device).

According to the semiconductor memory device of one embodiment, when data is written, the drain 5, the source 4, and the well 3 of the semiconductor memory device S are short-circuited by the wiring 10. Well 3
Is short-circuited with the gate electrode 11,
To ensure that the point A drops to the ground potential, the potential at the point A drops due to the pn junction at the junction of the diffusion layer (consisting of the well 3 and either the source 4 or the drain 5). It is possible to prevent undesired phenomena and to stably read stored data.

Further, according to the semiconductor memory device according to one embodiment, since there is the well 2 to which the power supply voltage Vcc is applied, at the time of writing data to the semiconductor memory device S,
By the supplied write pulse, the semiconductor memory element S
Therefore, even if the potential of the well 3 fluctuates due to writing, the well 2 has a stable potential (the power supply voltage Vcc), and thus acts as a barrier layer, causing noise to be present in other peripheral circuits. Can be prevented from adversely affecting the operation.

Further, according to the semiconductor memory element of one embodiment, since data can be written electrically, unlike the case where data is written by melting using thermal energy by a laser, material droplets fly. It is possible to prevent a decrease in the reliability of peripheral circuits and transistors due to short-circuiting of wiring due to droplets, and it is not necessary to provide an extra space because droplets do not fly. There is no increase in chip area.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention. For example, in FIG. 1, the well and the diffusion layer may have a structure in which the electric polarities are opposite to each other.

That is, the substrate 1 is of n-type, the well 2 is of p-type, the well 3 is of n-type, the diffusion layer 7 is of p + type, the diffusion layer 6 is of n + type, and the source 4 and the drain 5 A structure in which the diffusion layer is of p + type may be used. At this time, the substrate 1
Is applied with a power supply voltage Vcc, and the diffusion layer 7 is grounded. The processes at the time of writing and at the time of reading are the same as those in the embodiment, and thus the description thereof is omitted.

[0069]

According to the present invention, when data is written, the drain, the source, and the well are short-circuited by the wiring. Therefore, even if any of the drain, the source, and the well is short-circuited with the gate electrode, the diffusion is prevented. The pn junction at the junction of the layers prevents the voltage from dropping and prevents data from being read out stably, and enables data to be read stably. In addition, since data can be written electrically, thermal energy by laser Unlike data writing, the use of melting does not cause splashing of the material, unlike the writing of data, and can prevent a decrease in the reliability of peripheral circuits and transistors due to short-circuiting of wiring due to the splashing, and In addition, since there is no need to provide an extra space since the splash does not fly, the chip area does not increase.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating data write and data read operations of the semiconductor memory element shown in FIG.

FIG. 3 is a sectional view showing a structure of a semiconductor memory element according to a first conventional example.

FIG. 4 is a sectional view showing a structure of a semiconductor memory element according to a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2, 3 well 4 Source 5 Drain 6, 7 Diffusion layer 8 Gate insulating film 9 Interlayer insulating film 10 Wiring 11 Gate electrode S Semiconductor memory element 20, 22, 23 Inverter 21 Transfer gate 21n, 21p, 24, 25 MOS transistor S semiconductor memory element LT latch T1, T2, T3, T4, T5, TO terminal

Claims (6)

[Claims]
1. A MOS used as an antifuse
A semiconductor memory device having a structure, comprising: a semiconductor substrate; a well formed on a surface of the semiconductor substrate; and a MOS transistor formed in the well, wherein the well and a source and a drain of the MOS transistor are electrically connected. To the first electrode, and the MO
A semiconductor memory element, wherein a gate of an S transistor is used as a second electrode.
2. The method according to claim 1, further comprising: a step between the well and the semiconductor substrate.
2. The semiconductor memory device according to claim 1, further comprising a second well having a conductivity opposite to that of said well.
3. A high electric field is applied between the gate of the MOS transistor and the well, the source and the drain to destroy a gate oxide film of the MOS transistor, and the gate, the well and the source 3. The semiconductor memory device according to claim 1, wherein data is written by short-circuiting one of said drain and said drain.
4. The semiconductor memory device according to claim 1, wherein said wiring is set to a ground potential, and writing is performed by applying a high voltage to said gate.
5. The gate of a plurality of antifuses is connected in common, writing is performed by setting the wiring to a ground potential and applying a high voltage to the gate, and setting the wiring to a power supply potential or a writing potential. 4. The semiconductor memory device according to claim 1, wherein writing is not performed by applying a high voltage to the gate.
6. The anti-fuse storage information is read by applying a predetermined potential to the wiring and detecting the potential of the wiring after a lapse of a predetermined time. 3. The semiconductor storage element according to any one of 3.
JP27340499A 1999-09-27 1999-09-27 Semiconductor storage element Expired - Fee Related JP3275893B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27340499A JP3275893B2 (en) 1999-09-27 1999-09-27 Semiconductor storage element

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP27340499A JP3275893B2 (en) 1999-09-27 1999-09-27 Semiconductor storage element
KR10-2000-0056483A KR100384259B1 (en) 1999-09-27 2000-09-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2001102456A true JP2001102456A (en) 2001-04-13
JP3275893B2 JP3275893B2 (en) 2002-04-22

Family

ID=17527430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27340499A Expired - Fee Related JP3275893B2 (en) 1999-09-27 1999-09-27 Semiconductor storage element

Country Status (2)

Country Link
JP (1) JP3275893B2 (en)
KR (1) KR100384259B1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2843482A1 (en) * 2002-08-12 2004-02-13 St Microelectronics Sa Method and circuit for programming an anti-fuse transistor for use in electronic circuits, the transistor has drain, source and bulk connected together and gate as other electrode
JP2007116045A (en) * 2005-10-24 2007-05-10 Elpida Memory Inc Semiconductor device
JP2007294861A (en) * 2006-04-20 2007-11-08 Ememory Technology Inc Operation method of single layer polysilicon nonvolatile memory cell
JP2007305947A (en) * 2006-05-08 2007-11-22 Seiko Npc Corp Semiconductor memory
KR100866960B1 (en) 2007-02-16 2008-11-05 삼성전자주식회사 Semiconductor integrated circuit
JP2009004578A (en) * 2007-06-21 2009-01-08 Toshiba Corp Nonvolatile semiconductor memory device
US8729642B2 (en) 2008-01-30 2014-05-20 Eiji Kitamura Semiconductor device comprising a gate electrode having an opening
KR20140086166A (en) * 2012-12-28 2014-07-08 에스케이하이닉스 주식회사 Anti fuse arrary of semiconductor device and method for fabricating the same
JP2016510509A (en) * 2013-02-05 2016-04-07 クアルコム,インコーポレイテッド System and method for programming a memory cell

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003324151A (en) 2002-04-26 2003-11-14 Toshiba Corp Semiconductor integrated circuit device, mounting substrate device and wiring cutting method of the mounting substrate device
US8735297B2 (en) 2004-05-06 2014-05-27 Sidense Corporation Reverse optical proximity correction method
US7755162B2 (en) 2004-05-06 2010-07-13 Sidense Corp. Anti-fuse memory cell
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
WO2005109516A1 (en) 2004-05-06 2005-11-17 Sidense Corp. Split-channel antifuse array architecture
KR20180085120A (en) 2017-01-17 2018-07-26 삼성전자주식회사 Semiconductor memory device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1389782A1 (en) * 2002-08-12 2004-02-18 STMicroelectronics S.A. Programming method of anti-fuse and associated programming circuit
US6928021B2 (en) 2002-08-12 2005-08-09 Stmicroelectronics Sa Method for the programming of an anti-fuse, and associated programming circuit
FR2843482A1 (en) * 2002-08-12 2004-02-13 St Microelectronics Sa Method and circuit for programming an anti-fuse transistor for use in electronic circuits, the transistor has drain, source and bulk connected together and gate as other electrode
JP2007116045A (en) * 2005-10-24 2007-05-10 Elpida Memory Inc Semiconductor device
JP2007294861A (en) * 2006-04-20 2007-11-08 Ememory Technology Inc Operation method of single layer polysilicon nonvolatile memory cell
JP2007305947A (en) * 2006-05-08 2007-11-22 Seiko Npc Corp Semiconductor memory
KR100866960B1 (en) 2007-02-16 2008-11-05 삼성전자주식회사 Semiconductor integrated circuit
US7796460B2 (en) 2007-06-21 2010-09-14 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JP4510057B2 (en) * 2007-06-21 2010-07-21 株式会社東芝 Nonvolatile semiconductor memory device
JP2009004578A (en) * 2007-06-21 2009-01-08 Toshiba Corp Nonvolatile semiconductor memory device
US8729642B2 (en) 2008-01-30 2014-05-20 Eiji Kitamura Semiconductor device comprising a gate electrode having an opening
KR20140086166A (en) * 2012-12-28 2014-07-08 에스케이하이닉스 주식회사 Anti fuse arrary of semiconductor device and method for fabricating the same
KR101966278B1 (en) * 2012-12-28 2019-04-08 에스케이하이닉스 주식회사 Anti fuse arrary of semiconductor device and method for fabricating the same
JP2016510509A (en) * 2013-02-05 2016-04-07 クアルコム,インコーポレイテッド System and method for programming a memory cell
US9373412B2 (en) 2013-02-05 2016-06-21 Qualcomm Incorporated System and method of programming a memory cell

Also Published As

Publication number Publication date
KR100384259B1 (en) 2003-05-16
JP3275893B2 (en) 2002-04-22
KR20010030493A (en) 2001-04-16

Similar Documents

Publication Publication Date Title
JP5738380B2 (en) Mask programmable antifuse structure
JP5325317B2 (en) Semiconductor integrated circuit device
US8629481B2 (en) Semiconductor integrated circuit device
JP5714328B2 (en) Antifuse memory cell
US6233194B1 (en) Method of anti-fuse repair
US4899205A (en) Electrically-programmable low-impedance anti-fuse element
EP2195811B1 (en) Anti-fuse element
US6909635B2 (en) Programmable memory cell using charge trapping in a gate oxide
US7772591B1 (en) Electrically-programmable transistor antifuses
US7746696B1 (en) CMOS twin cell non-volatile random access memory
KR100500579B1 (en) 3-Transistor OTP ROM using CMOS Gate Oxide Antifuse
US6337507B1 (en) Silicide agglomeration fuse device with notches to enhance programmability
US5847441A (en) Semiconductor junction antifuse circuit
TWI269345B (en) Programmable device programmed by varying resistant using phase transition
US6960819B2 (en) System and method for one-time programmed memory through direct-tunneling oxide breakdown
US7312109B2 (en) Methods for fabricating fuse programmable three dimensional integrated circuits
US5412244A (en) Electrically-programmable low-impedance anti-fuse element
US6266269B1 (en) Three terminal non-volatile memory element
CA1147818A (en) Semiconductor integrated circuit device having control signal generating circuits
CA2692887C (en) Low power antifuse sensing scheme with improved reliability
US5774011A (en) Antifuse circuit using standard MOSFET devices
EP0663669B1 (en) Improvements in or relating to fuse and antifuse link structures for integrated circuits
US5976943A (en) Method for bi-layer programmable resistor
EP0405586B1 (en) Semiconductor device and method of burning in the same
DE60009181T2 (en) Anti-fuse circuit for DRAM repair after packaging in the housing

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20020108

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080208

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090208

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100208

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110208

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110208

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120208

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120208

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130208

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140208

Year of fee payment: 12

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees