JP2001100249A - Liquid crystal display panel and its manufacturing method - Google Patents

Liquid crystal display panel and its manufacturing method

Info

Publication number
JP2001100249A
JP2001100249A JP27348999A JP27348999A JP2001100249A JP 2001100249 A JP2001100249 A JP 2001100249A JP 27348999 A JP27348999 A JP 27348999A JP 27348999 A JP27348999 A JP 27348999A JP 2001100249 A JP2001100249 A JP 2001100249A
Authority
JP
Japan
Prior art keywords
pattern
wiring
liquid crystal
scanning signal
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27348999A
Other languages
Japanese (ja)
Inventor
Hidetsugu Yamamoto
英嗣 山元
Tatsuya Wakimoto
竜也 脇本
Atsushi Mansei
敦士 満生
Takeshi Nakagawa
毅 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP27348999A priority Critical patent/JP2001100249A/en
Publication of JP2001100249A publication Critical patent/JP2001100249A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display panel high in manufacturing yield and display quality by improving the display quality by relieving defective pixels resulting from a pattern abnormality or the like on the manufacture of a liquid crystal display panel. SOLUTION: In this liquid crystal panel, a common capacity pattern 7 forming a capacity across a common electrode wiring 6, and a pattern connected to a drain electrode of a thin film transistor 3 arranged at a part intersecting gate wiring are connected to a pixel electrode via individually independent pattern wiring 11, 12 and the same contact 8. Also a superposing pattern 9 flatly superimposed on a gate electrode directly connected to the common capacity pattern 7 is formed, and it is the respective patterns 7, 9 can be cut from each other, be connected to the gate wiring and combined with each other, so that a luminescence defective pixel can be made in to a dark pixel to improve the display quality and the manufacturing yield.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、液晶表示パネルと
その製造方法に関する。
The present invention relates to a liquid crystal display panel and a method for manufacturing the same.

【0002】[0002]

【従来の技術】薄膜トランジスタ(TFT)を用いた液
晶表示パネルの一つ一つの画素は、図4に示すように、
複数の走査信号配線1と、この走査信号配線1と交差す
る複数の映像信号配線2と、前記複数の走査信号配線1
と並行に配線された共通電極配線6と、前記複数の走査
信号配線1と前記複数の映像信号配線2とが交差する部
分に設けた薄膜トランジスタ3と、この薄膜トランジス
タ3のドレイン電極に接続した画素電極5と、この画素
電極5と接続し共通電極配線6と容量を形成する共通容
量パターン7とを備えている。前記走査信号配線1は薄
膜トランジスタ3のゲート電極を形成している。
2. Description of the Related Art Each pixel of a liquid crystal display panel using a thin film transistor (TFT) is, as shown in FIG.
A plurality of scanning signal lines 1; a plurality of video signal lines 2 intersecting with the scanning signal lines 1;
A plurality of scanning signal lines 1 and a plurality of video signal lines 2, and a pixel electrode connected to a drain electrode of the thin film transistor 3. 5 and a common capacitance pattern 7 connected to the pixel electrode 5 and forming a capacitance with the common electrode wiring 6. The scanning signal wiring 1 forms a gate electrode of the thin film transistor 3.

【0003】[0003]

【発明が解決しようとする課題】通常、上記の共通電極
配線6は、薄膜トランジスタ3を形成するアレイ基板と
対面するカラーフィルター基板の対向電極と接続するた
め、液晶表示パネルの作成上に生じた欠陥などで、共通
容量パターン7と共通電極配線6とが電気的にショート
した場合、画素の電位は共通電極と同電位となり、通常
のノーマリーホワイトの液晶表示パネルでは輝点不良と
なる。
Usually, the above-mentioned common electrode wiring 6 is connected to the counter electrode of the color filter substrate facing the array substrate on which the thin film transistor 3 is formed. If, for example, the common capacitance pattern 7 and the common electrode wiring 6 are electrically short-circuited, the potential of the pixel becomes the same as that of the common electrode, and a normal normally white liquid crystal display panel has a bright spot defect.

【0004】また、走査信号配線1、薄膜トランジスタ
3および共通容量パターン7は、同一層の導電材料配線
で形成されるため、液晶表示パネル作成上に生じた欠陥
などで電気的にショートしやすく、この場合も上記と同
様に通常のノーマリーホワイトの液晶表示パネルでは輝
点不良となる。本発明は、このような従来の課題を解決
するものであり、液晶表示パネル作成上に生じた欠陥な
どで発生する輝点不良を救済できる液晶表示パネルおよ
びその製造方法を提供することを目的とする。
Further, since the scanning signal wiring 1, the thin film transistor 3 and the common capacitance pattern 7 are formed of the same layer of conductive material wiring, they are liable to be short-circuited due to a defect or the like generated in the production of the liquid crystal display panel. In this case, as in the above case, a normal normally white liquid crystal display panel has a defective bright spot. An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a liquid crystal display panel capable of relieving a luminescent spot defect generated by a defect or the like generated on a liquid crystal display panel and a method of manufacturing the same. I do.

【0005】[0005]

【課題を解決するための手段】上記課題を解決する本発
明は、共通電極配線と容量を形成する共通容量パターン
と、ゲート配線と交差する部分に設けた薄膜トランジス
タ(TFT)のドレイン電極に接続するパターンが、そ
れぞれ独立したパターン配線でかつ同一のコンタクトを
介して画素電極と接続した構造を持ち、かつ共通容量パ
ターンと直接接続するゲート電極と平面的に重なったパ
ターンを形成し、それぞれのパターンを切り離したり、
ゲート配線と接続することを組み合わせ画素電極をゲー
ト電極配線と接続することで、輝点となっている画素を
黒点化し、表示品位を向上、歩留まりを改善するもので
ある。
According to the present invention to solve the above-mentioned problems, a common capacitance pattern for forming a capacitor with a common electrode wiring is connected to a drain electrode of a thin film transistor (TFT) provided at a portion intersecting a gate wiring. The pattern has a structure in which each pattern wiring is independent pattern wiring and is connected to the pixel electrode via the same contact, and a pattern is formed which overlaps with the gate electrode directly connected to the common capacitance pattern, and each pattern is formed. Disconnecting,
By connecting the pixel electrode to the gate electrode wiring in combination with the connection to the gate wiring, the pixel which is a bright spot is turned into a black dot, the display quality is improved, and the yield is improved.

【0006】本発明の液晶表示パネルは、一対のガラス
基板間に液晶が封入され、前記ガラス基板の一方に対向
電極基板を備え、前記ガラス基板の他方に、複数の走査
信号配線と、この走査信号配線と交差する複数の映像信
号配線と、前記複数の走査信号配線と並行に配線された
共通電極配線と、前記複数の走査信号配線と前記複数の
映像信号配線が交差する部分に設けた薄膜トランジスタ
と、この薄膜トランジスタのドレイン電極にコンタクト
を介して接続した画素電極と、この画素電極と接続し共
通電極配線と容量を形成する共通容量パターンとを備え
て各画素を形成した液晶表示パネルにおいて、共通容量
パターンは、前記ドレイン電極と画素電極を接続する第
1のパターン配線とは別の第2のパターン配線を介して
前記画素電極と接続され、同じ画素の画素電極に接続し
た薄膜トランジスタのゲート電極を形成する走査信号配
線と層間絶縁膜を介して部分的に重なる重ねパターンを
設けたことを特徴とする。
In the liquid crystal display panel of the present invention, liquid crystal is sealed between a pair of glass substrates, one of the glass substrates is provided with a counter electrode substrate, and the other of the glass substrates is provided with a plurality of scanning signal wirings and the scanning signal wiring. A plurality of video signal wirings intersecting with the signal wirings, a common electrode wiring wired in parallel with the plurality of scanning signal wirings, and a thin film transistor provided at a portion where the plurality of scanning signal wirings and the plurality of video signal wirings intersect And a pixel electrode connected to the drain electrode of the thin film transistor via a contact, and a common capacitance pattern forming a capacitance with a common electrode line connected to the pixel electrode. The capacitor pattern is connected to the pixel electrode via a second pattern wiring different from the first pattern wiring connecting the drain electrode and the pixel electrode. Is characterized in that a scan signal wiring and superimposed patterns overlap each other via the interlayer insulating film to form a gate electrode of the thin film transistor connected to the pixel electrode of the same pixel.

【0007】また、前記重ねパターンは、共通容量パタ
ーンから走査信号配線の側に平面的に突き出し走査信号
配線と交差したことを特徴とする。また、前記重ねパタ
ーンの走査信号配線との間の静電容量が、このパターン
の接続する薄膜トランジスタとゲート配線間に形成され
る寄生容量以下であることを特徴とする。
Further, the superposed pattern projects from the common capacitance pattern to the side of the scanning signal wiring in a plane, and intersects with the scanning signal wiring. Further, a capacitance between the scanning signal wiring of the overlapping pattern and a parasitic capacitance formed between the thin film transistor connected to the pattern and the gate wiring is not more than the capacitance.

【0008】また、前記重ねパターンの走査信号配線と
の間の静電容量が、このパターンの接続する共通容量パ
ターンと共通電極配線との間に形成される蓄積容量の1
0分の1以下であることを特徴とする。さらに、本発明
の液晶表示パネルの製造方法は、上記の何れかの液晶表
示パネルにおける欠陥画素の第1のパターン配線を切断
するとともに、走査信号配線と層間絶縁膜を介して部分
的に重なる重ねパターンとを層間絶縁膜を破壊し電気的
に接続して前記欠陥画素の表示を黒点化して認識しにく
くすることを特徴とする。
Further, the capacitance between the scanning signal wiring of the overlapping pattern and one of the storage capacitors formed between the common capacitance pattern connected to this pattern and the common electrode wiring is one.
It is characterized by being 1/0 or less. Further, according to the method of manufacturing a liquid crystal display panel of the present invention, the first pattern wiring of the defective pixel in any one of the above liquid crystal display panels is cut and overlapped with the scanning signal wiring via an interlayer insulating film. It is characterized in that the pattern and the interlayer insulating film are destroyed and electrically connected to each other to make the display of the defective pixel black and difficult to recognize.

【0009】また、本発明の液晶表示パネルの製造方法
は、上記の何れかの液晶表示パネルにおける欠陥画素の
第2のパターン配線を切断するとともに、走査信号配線
と層間絶縁膜を介して部分的に重なる重ねパターンとを
層間絶縁膜を破壊し電気的に接続して前記欠陥画素を黒
点化して認識しにくくすることを特徴とする。
Further, according to the method of manufacturing a liquid crystal display panel of the present invention, the second pattern wiring of the defective pixel in any one of the above liquid crystal display panels is cut, and at the same time, the partial pattern wiring is partially interposed via the scanning signal wiring and the interlayer insulating film. The defective pattern is blackened to make it difficult to recognize the defective pixel by breaking the interlayer insulating film and electrically connecting the overlapping pattern with the overlapping pattern.

【0010】[0010]

【発明の実施の形態】以下、本発明の液晶表示パネルの
製造方法を具体的な実施の形態に基づいて説明する。 (実施の形態1)図1〜図3は(実施の形態1)を示
す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a liquid crystal display panel according to the present invention will be described based on specific embodiments. (Embodiment 1) FIGS. 1 to 3 show (Embodiment 1).

【0011】なお、従来例を示す図4と同一の構成部分
には同一番号を付けて説明する。また、以下においては
液晶表示パネルはノーマリーホワイトモードとして説明
する。本発明の液晶表示パネルは、一対のガラス基板間
に液晶が封入され、前記ガラス基板の一方に対向電極基
板を備え、前記ガラス基板の他方に、複数の走査信号配
線1と、この走査信号配線1と交差する複数の映像信号
配線2と、前記複数の走査信号配線1と並行に配線され
た共通電極配線6と、前記複数の走査信号配線1と前記
複数の映像信号配線2が交差する部分に設けた薄膜トラ
ンジスタ3と、この薄膜トランジスタ3のドレイン電極
にコンタクトを介して接続した画素電極5と、この画素
電極5と接続し共通電極配線6と容量を形成する共通容
量パターン7とを備えて各画素を形成して構成されてい
る。
The same components as those of the prior art shown in FIG. 4 will be described with the same reference numerals. Hereinafter, the liquid crystal display panel will be described as a normally white mode. The liquid crystal display panel of the present invention includes a liquid crystal sealed between a pair of glass substrates, a counter electrode substrate provided on one of the glass substrates, and a plurality of scanning signal wirings 1 provided on the other of the glass substrates. 1, a plurality of video signal wirings 2, a common electrode wiring 6 wired in parallel with the plurality of scanning signal wirings 1, and a portion where the plurality of scanning signal wirings 1 and the plurality of video signal wirings 2 intersect. , A pixel electrode 5 connected to a drain electrode of the thin film transistor 3 via a contact, and a common capacitance pattern 7 connected to the pixel electrode 5 and forming a capacitance with a common electrode wiring 6. It is configured by forming pixels.

【0012】図1にさらに示すように、薄膜トランジス
タ3のドレイン電極4と画素電極5とは第1のパターン
配線11とコンタクト8を介して接続されており、共通
電極配線6と容量を形成する共通容量パターン7は、第
2のパターン配線12とコンタクト8を介して画素電極
5に接続されている。なお、重ねパターン9の走査信号
配線1との間の静電容量は、突き抜け影響を抑えるため
に、このパターンの接続する薄膜トランジスタ3とゲー
ト配線との間に形成される寄生容量以下である。
As further shown in FIG. 1, the drain electrode 4 and the pixel electrode 5 of the thin film transistor 3 are connected to each other via a first pattern wiring 11 and a contact 8, and form a common electrode forming a capacitor with the common electrode wiring 6. The capacitance pattern 7 is connected to the pixel electrode 5 via the second pattern wiring 12 and the contact 8. The capacitance between the overlapping pattern 9 and the scanning signal wiring 1 is equal to or smaller than the parasitic capacitance formed between the thin film transistor 3 connected to this pattern and the gate wiring in order to suppress the penetration effect.

【0013】また、重ねパターン9の走査信号配線1と
の間の静電容量は、TFTのオフ時の突き抜け電圧の影
響の抑制のために、このパターンの接続する共通容量パ
ターン7と共通電極配線6との間に形成される蓄積容量
の10分の1以下である。この画素において、欠陥があ
った場合の一例を図2と図3に示す。具体的には、図2
は薄膜トランジスタ3のドレイン電極4と映像信号配線
2との間にパターン異常Aが発生した場合に、この欠陥
画素を目立たなくするためのパターン形状の変更を示し
ている。
The capacitance between the overlapping pattern 9 and the scanning signal line 1 is reduced by the common capacitance pattern 7 connected to the pattern and the common electrode line in order to suppress the influence of the penetration voltage when the TFT is off. 6 is less than or equal to one-tenth of the storage capacity formed. FIGS. 2 and 3 show an example of a case where there is a defect in this pixel. Specifically, FIG.
Indicates a change in pattern shape for making the defective pixel inconspicuous when a pattern abnormality A occurs between the drain electrode 4 of the thin film transistor 3 and the video signal wiring 2.

【0014】パターン異常Aが発生した場合には、画素
電極5と映像信号配線2とは電気的にショートし、この
画素は輝点となる。そこで、本発明ではレーザー光の照
射などにより画素電極5とドレイン電極4とをつなぐ第
1のパターン配線11をB部で切断し、かつ共通容量パ
ターン7に接続した重ねパターン9の部分と走査信号配
線1との層間絶縁を破壊して電気的に共通容量パターン
7、即ち画素電極5を走査信号配線1と接続すること
で、通常画素電位に比べ十分低い電位である走査信号配
線に接続する。これによって画素は黒点となり、画像表
示上欠陥としての認識がしにくくなり、表示品位の改
善、歩留まり向上が可能となる。
When a pattern abnormality A occurs, the pixel electrode 5 and the video signal wiring 2 are electrically short-circuited, and this pixel becomes a bright spot. Therefore, in the present invention, the first pattern wiring 11 connecting the pixel electrode 5 and the drain electrode 4 is cut at the portion B by irradiating a laser beam or the like, and the portion of the overlapping pattern 9 connected to the common capacitance pattern 7 is scanned with the scanning signal. By electrically connecting the common capacitance pattern 7, that is, the pixel electrode 5 to the scanning signal line 1 by breaking the interlayer insulation with the line 1, the pixel electrode 5 is connected to the scanning signal line having a sufficiently lower potential than the normal pixel potential. As a result, the pixel becomes a black point, and it is difficult to recognize the defect as a defect on the image display, and it is possible to improve the display quality and the yield.

【0015】図3はパターン異常が共通容量パターン7
において発生した場合を示している。この場合には、第
2のパターン配線12をC部で切断し、薄膜トランジス
タ3のドレイン電極4の部分と走査信号配線1との層間
絶縁を破壊し、電気的にドレイン電極4、即ち画素電極
5を走査信号配線1と接続する。これによって画素は黒
点となり、画像表示上欠陥としての認識がしにくくな
り、表示品位の改善、歩留まり向上が可能となる。
FIG. 3 shows that the pattern abnormality is the common capacitance pattern 7.
Shows the case where this occurred. In this case, the second pattern wiring 12 is cut at the portion C, the interlayer insulation between the drain electrode 4 of the thin film transistor 3 and the scanning signal wiring 1 is broken, and the drain electrode 4, that is, the pixel electrode 5 is electrically disconnected. Are connected to the scanning signal wiring 1. As a result, the pixel becomes a black point, and it is difficult to recognize the defect as a defect on the image display, and it is possible to improve the display quality and the yield.

【0016】なお、画素欠陥の原因はパターン異常だけ
でなく層間絶縁等の各種画素欠陥においても同様の処置
により同様の効果が得られる。
The same effect can be obtained by the same treatment not only for the pattern abnormality but also for various pixel defects such as interlayer insulation.

【0017】[0017]

【発明の効果】以上のように本発明によれば、液晶表示
パネルの製造工程で生じるパターン異常や層間絶縁の破
壊等による不具合を共通容量パターンと画素電極、薄膜
トランジスタのドレイン電極と画素電極に接続するパタ
ーン配線をそれぞれ独立に形成することで、画素の表示
を黒点とし、画像表示上欠陥としての認識をしにくくす
ることで、表示品位の改善、歩留まりを向上することが
できる。
As described above, according to the present invention, defects caused by pattern abnormalities and destruction of interlayer insulation during the manufacturing process of the liquid crystal display panel are connected to the common capacitor pattern and the pixel electrode, the drain electrode and the pixel electrode of the thin film transistor. By independently forming the pattern wirings to be formed, the pixel display is set to a black point, and it is difficult to recognize the defect as an image display defect, so that the display quality can be improved and the yield can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の(実施の形態1)の液晶表示パネルの
一画素の平面図
FIG. 1 is a plan view of one pixel of a liquid crystal display panel according to Embodiment 1 of the present invention.

【図2】同実施の形態においてパターン欠陥があった場
合の救済の一例を示す平面図
FIG. 2 is an exemplary plan view showing an example of relief in the case where there is a pattern defect in the embodiment;

【図3】同実施の形態において別のパターン欠陥があっ
た場合の救済の一例を示す平面図
FIG. 3 is a plan view showing an example of remedy when another pattern defect is present in the embodiment.

【図4】従来の液晶表示パネルの一画素の平面図FIG. 4 is a plan view of one pixel of a conventional liquid crystal display panel.

【符号の説明】[Explanation of symbols]

1 走査信号配線 2 映像信号配線 3 薄膜トランジスタ 4 ドレイン電極 5 画素電極 6 共通電極配線 7 共通容量パターン 8 コンタクト 9 共通容量パターン7に接続した重ねパターン 11 第1のパターン配線 12 第2のパターン配線 A ドレイン電極4と映像信号配線2の間のパター
ン異常 B 画素電極5とドレイン電極4をつなぐパターン
配線の切断部 C 画素電極5と共通容量パターン7をつなぐパタ
ーン配線の切断部
Reference Signs List 1 scanning signal wiring 2 video signal wiring 3 thin film transistor 4 drain electrode 5 pixel electrode 6 common electrode wiring 7 common capacitance pattern 8 contact 9 overlapping pattern connected to common capacitance pattern 7 11 first pattern wiring 12 second pattern wiring A drain Abnormal pattern between electrode 4 and video signal wiring 2 B Cut part of pattern wiring connecting pixel electrode 5 and drain electrode 4 C Cut part of pattern wiring connecting pixel electrode 5 and common capacitance pattern 7

───────────────────────────────────────────────────── フロントページの続き (72)発明者 満生 敦士 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 中川 毅 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 2H092 JA24 JB56 JB69 JB73 KB25 MA52 NA29 5C094 AA02 AA42 AA48 BA03 BA43 CA19 DA13 DB04 DB10 EA04 EA10 FA01 FB12 FB14 FB15 GB10 5F110 AA02 AA27 HM18 NN73 QQ30 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Atsushi Mitsuo, Inventor 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Terms (reference) 2H092 JA24 JB56 JB69 JB73 KB25 MA52 NA29 5C094 AA02 AA42 AA48 BA03 BA43 CA19 DA13 DB04 DB10 EA04 EA10 FA01 FB12 FB14 FB15 GB10 5F110 AA02 AA27 HM18 NN73 QQ30

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】一対のガラス基板間に液晶が封入され、前
記ガラス基板の一方に対向電極基板を備え、前記ガラス
基板の他方に、複数の走査信号配線と、前記走査信号配
線と交差する複数の映像信号配線と、前記複数の走査信
号配線と並行に配線された共通電極配線と、前記複数の
走査信号配線と前記複数の映像信号配線が交差する部分
に設けた薄膜トランジスタと、前記薄膜トランジスタの
ドレイン電極にコンタクトを介して接続した画素電極
と、この画素電極と接続し共通電極配線と容量を形成す
る共通容量パターンとを備えて各画素を形成した液晶表
示パネルにおいて、 共通容量パターンは、前記ドレイン電極と画素電極とを
接続する第1のパターン配線とは別の第2のパターン配
線を介して前記画素電極と接続され、同じ画素の画素電
極に接続した薄膜トランジスタのゲート電極を形成する
走査信号配線と層間絶縁膜を介して部分的に重なる重ね
パターンを設けた液晶表示パネル。
A liquid crystal is sealed between a pair of glass substrates, a counter electrode substrate is provided on one of the glass substrates, and a plurality of scanning signal wirings and a plurality of scanning signal wirings intersecting the scanning signal wirings are provided on the other of the glass substrates. Video signal wiring, a common electrode wiring wired in parallel with the plurality of scanning signal wirings, a thin film transistor provided at a portion where the plurality of scanning signal wirings and the plurality of video signal wirings intersect, and a drain of the thin film transistor In a liquid crystal display panel in which each pixel is formed including a pixel electrode connected to an electrode via a contact, and a common capacitance pattern connected to the pixel electrode and forming a capacitance with a common electrode wiring, the common capacitance pattern includes the drain The pixel electrode of the same pixel is connected to the pixel electrode via a second pattern wiring different from the first pattern wiring connecting the electrode and the pixel electrode. A liquid crystal display panel provided with an overlapping pattern that partially overlaps with a scanning signal wiring forming a gate electrode of a thin film transistor connected to a pole via an interlayer insulating film.
【請求項2】重ねパターンは、共通容量パターンから走
査信号配線の側に平面的に突き出し走査信号配線と交差
した請求項1記載の液晶表示パネル。
2. The liquid crystal display panel according to claim 1, wherein the overlapping pattern protrudes from the common capacitance pattern toward the scanning signal wiring in a plane and crosses the scanning signal wiring.
【請求項3】重ねパターンの走査信号配線との間の静電
容量が、このパターンの接続する薄膜トランジスタとゲ
ート配線間に形成される寄生容量以下である請求項1ま
たは請求項2記載の液晶表示パネル。
3. The liquid crystal display according to claim 1, wherein a capacitance between the scanning signal wiring of the overlapping pattern and a parasitic capacitance formed between the thin film transistor connected to the pattern and the gate wiring is equal to or smaller than the capacitance. panel.
【請求項4】重ねパターンの走査信号配線との間の静電
容量が、このパターンの接続する共通容量パターンと共
通電極配線との間に形成される蓄積容量の10分の1以
下である請求項1または請求項2記載の液晶表示パネ
ル。
4. A storage capacitor formed between a common capacitance pattern and a common electrode wiring connected to this pattern, wherein the capacitance between the scanning signal wiring and the overlapping pattern is not more than one-tenth of the storage capacitance. 3. The liquid crystal display panel according to claim 1 or 2.
【請求項5】請求項1〜請求項4の何れかに記載の液晶
表示パネルにおける欠陥画素の第1のパターン配線を切
断するとともに、走査信号配線と前記走査信号配線上に
層間絶縁膜を介して部分的に重なる重ねパターンとを前
記層間絶縁膜を破壊し電気的に接続して前記欠陥画素の
表示を黒点化して認識しにくくする液晶表示パネルの製
造方法。
5. The liquid crystal display panel according to claim 1, wherein the first pattern wiring of the defective pixel in the liquid crystal display panel is cut, and a scanning signal wiring and an interlayer insulating film are interposed on the scanning signal wiring. A method of manufacturing a liquid crystal display panel in which the overlapping pattern partially overlapped is electrically connected by breaking the interlayer insulating film to make the display of the defective pixel black dots and difficult to recognize.
【請求項6】請求項1〜請求項4の何れかに記載の液晶
表示パネルにおける欠陥画素の第2のパターン配線を切
断するとともに、走査信号配線と前記走査信号配線上に
層間絶縁膜を介して部分的に重なる重ねパターンとを層
間絶縁膜を破壊し電気的に接続して前記欠陥画素を黒点
化して認識しにくくする液晶表示パネルの製造方法。
6. The liquid crystal display panel according to claim 1, wherein the second pattern wiring of the defective pixel in the liquid crystal display panel is cut, and a scanning signal wiring and an interlayer insulating film are interposed on the scanning signal wiring. A method of manufacturing a liquid crystal display panel in which the overlapped pattern partially overlaps and electrically connects the destructed interlayer insulating film to blacken the defective pixels to make them difficult to recognize.
JP27348999A 1999-09-28 1999-09-28 Liquid crystal display panel and its manufacturing method Pending JP2001100249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27348999A JP2001100249A (en) 1999-09-28 1999-09-28 Liquid crystal display panel and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27348999A JP2001100249A (en) 1999-09-28 1999-09-28 Liquid crystal display panel and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2001100249A true JP2001100249A (en) 2001-04-13

Family

ID=17528627

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001100249A (en)

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KR20030094452A (en) * 2002-06-04 2003-12-12 삼성전자주식회사 Thin film transistor array panel for liquid crystal display
JP2006201245A (en) * 2005-01-18 2006-08-03 Mitsubishi Electric Corp Display device and defect repairing method of display device
JP2007241183A (en) * 2006-03-13 2007-09-20 Mitsubishi Electric Corp Display device and repairing method for display device
KR101183434B1 (en) 2006-06-30 2012-09-14 엘지디스플레이 주식회사 Thin Film Transistor Substrate of Horizontal Electronic Field Applying Type
KR20150013406A (en) * 2014-12-19 2015-02-05 삼성디스플레이 주식회사 Liquid crystal display device
US9164344B2 (en) 2006-11-03 2015-10-20 Samsung Display Co., Ltd. Liquid crystal display device and method of repairing bad pixels therein

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030094452A (en) * 2002-06-04 2003-12-12 삼성전자주식회사 Thin film transistor array panel for liquid crystal display
JP2006201245A (en) * 2005-01-18 2006-08-03 Mitsubishi Electric Corp Display device and defect repairing method of display device
JP4622532B2 (en) * 2005-01-18 2011-02-02 三菱電機株式会社 Display device and display device defect repair method
JP2007241183A (en) * 2006-03-13 2007-09-20 Mitsubishi Electric Corp Display device and repairing method for display device
KR101183434B1 (en) 2006-06-30 2012-09-14 엘지디스플레이 주식회사 Thin Film Transistor Substrate of Horizontal Electronic Field Applying Type
US9164344B2 (en) 2006-11-03 2015-10-20 Samsung Display Co., Ltd. Liquid crystal display device and method of repairing bad pixels therein
US9268187B2 (en) 2006-11-03 2016-02-23 Samsung Display Co., Ltd. Liquid crystal display device and method of repairing bad pixels therein
KR20150013406A (en) * 2014-12-19 2015-02-05 삼성디스플레이 주식회사 Liquid crystal display device
KR101595828B1 (en) * 2014-12-19 2016-03-08 삼성디스플레이 주식회사 Liquid crystal display device

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