JP2001068832A - Wiring board and method of manufacturing the same - Google Patents
Wiring board and method of manufacturing the sameInfo
- Publication number
- JP2001068832A JP2001068832A JP23768699A JP23768699A JP2001068832A JP 2001068832 A JP2001068832 A JP 2001068832A JP 23768699 A JP23768699 A JP 23768699A JP 23768699 A JP23768699 A JP 23768699A JP 2001068832 A JP2001068832 A JP 2001068832A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- anisotropic conductive
- particles
- semiconductor chip
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29499—Shape or distribution of the fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、配線板とその製造
方法に関する。The present invention relates to a wiring board and a method for manufacturing the same.
【0002】[0002]
【従来の技術】配線板に電子部品を搭載する方法とし
て、配線板上に形成した電極に異方導電膜を介して電子
部品を接続する方法があり、このような配線板に形成さ
れた電極の厚さは10〜50μmで、半導体チップのバ
ンプが10〜50μmで、その間に厚さ15〜50μm
の異方導電性フィルムを挟み、加熱・加圧して積層接着
する。2. Description of the Related Art As a method of mounting an electronic component on a wiring board, there is a method of connecting an electronic component to an electrode formed on the wiring board via an anisotropic conductive film. The thickness of the semiconductor chip is 10 to 50 μm, the bump of the semiconductor chip is 10 to 50 μm, and the thickness is 15 to 50 μm.
Is sandwiched, and heated and pressed to laminate and bond.
【0003】[0003]
【発明が解決しようとする課題】ところで、半導体チッ
プは、ダイシングして分割されているので、その端部の
加工ができず、切断した箇所に半導体チップ内部の回路
導体が露出しており、そのような半導体チップを配線板
上に搭載しようとすると、その半導体チップの端部が電
極に接触して短絡することがあるという課題があった。Incidentally, since the semiconductor chip is divided by dicing, the end cannot be processed, and the circuit conductor inside the semiconductor chip is exposed at the cut portion. When mounting such a semiconductor chip on a wiring board, there is a problem that an end of the semiconductor chip may come into contact with an electrode to cause a short circuit.
【0004】本発明は、短絡のない配線板とその配線板
を製造する方法を提供することを目的とする。An object of the present invention is to provide a wiring board free from short circuits and a method for manufacturing the wiring board.
【0005】[0005]
【課題を解決するための手段】本発明の配線板は、配線
板上に形成した電極に異方導電膜を介して電子部品を接
続した配線板であって、異方導電膜が絶縁粒子を含むこ
とを特徴とする。A wiring board according to the present invention is a wiring board in which electronic components are connected to electrodes formed on the wiring board via an anisotropic conductive film, wherein the anisotropic conductive film contains insulating particles. It is characterized by including.
【0006】また、本発明の配線板の製造方法は、配線
板上に形成した電極に異方導電膜を介して電子部品を接
続する配線板の製造方法であって、異方導電膜に絶縁粒
子を含むものを用いることを特徴とする。A method of manufacturing a wiring board according to the present invention is a method of manufacturing a wiring board in which an electronic component is connected to an electrode formed on the wiring board via an anisotropic conductive film. It is characterized in that a material containing particles is used.
【0007】本発明者らは、鋭意、検討の結果、図3に
示すように、半導体チップ1を配線板11に搭載しよう
とすると、その半導体チップ1の端部が電極14に接触
して短絡するという現象が、半導体チップ1のバンプ2
が搭載するときの圧力で配線板11の電極14に埋まる
ので、配線板11の電極14と半導体チップ1の端部と
が接近することにより発生するということが分かり、さ
らに、半導体チップ1が埋まらないように接続しようと
すると、接続が不完全になるという知見が得られた。そ
こで、この知見を元に、図1に示すように、半導体チッ
プ1と電極14の接続を完全に行えるための接続条件下
で、半導体チップ1が電極14に埋まる量を抑制する方
法として、異方導電膜3に絶縁粒子4を混入するという
本発明をなすことができた。As a result of diligent studies, as shown in FIG. 3, when the present inventors attempt to mount the semiconductor chip 1 on the wiring board 11, the end of the semiconductor chip 1 contacts the electrode 14 and short-circuits. Phenomenon is caused by the bump 2 of the semiconductor chip 1.
Is buried in the electrodes 14 of the wiring board 11 by the pressure at the time of mounting, it is understood that this occurs when the electrode 14 of the wiring board 11 and the end of the semiconductor chip 1 approach each other. It was found that trying to connect in such a way would result in an incomplete connection. Therefore, based on this finding, as shown in FIG. 1, as a method for suppressing the amount of the semiconductor chip 1 buried in the electrode 14 under a connection condition for completely connecting the semiconductor chip 1 and the electrode 14, a different method is used. The present invention in which the insulating particles 4 were mixed in the conductive film 3 was able to be achieved.
【0008】[0008]
【発明の実施の形態】本発明の異方導電膜は、樹脂と導
電粒子からなるもので、樹脂には、ポリエチレン、ポリ
プロピレン等の熱可塑性樹脂でも用いることができる
が、エポキシ樹脂、ポリイミド樹脂等の熱、光、電子線
等のエネルギーによる硬化性絶縁材料が、耐熱性、耐湿
性及び機械的特性に優れることから好ましく適用でき
る。本発明は加熱加圧下での製造法であるため、エポキ
シ樹脂類と潜在性硬化剤の系や、アクリルやウレタン、
エポキシ樹脂類と光活性化剤との組み合わせ系が比較的
低温下で反応し易いことから、より好ましい。DESCRIPTION OF THE PREFERRED EMBODIMENTS The anisotropic conductive film of the present invention comprises a resin and conductive particles. The resin may be a thermoplastic resin such as polyethylene or polypropylene, but may be an epoxy resin, a polyimide resin or the like. The curable insulating material by the energy of heat, light, electron beam or the like can be preferably applied because it is excellent in heat resistance, moisture resistance and mechanical properties. Since the present invention is a production method under heating and pressure, epoxy resin and latent curing agent system, acrylic and urethane,
A combination system of an epoxy resin and a photoactivator is more preferable because it easily reacts at a relatively low temperature.
【0009】また、導電粒子は、導電性を有する各種の
金属や合金、酸化物等が採用できる。導電性と耐腐食性
を加味して好ましく用いられる材料としてはNi、Cu、
Al、Sn、Zn、Au、Pd、Ag、Co、Pb等の粒子であ
る。粒形はほぼ球状が好ましいが、表面に多数の突起を
設ける等の任意の形でよい。また、導電粒子は、核材の
表面に金属薄層を設けた構成のものが、均一粒径の球状
品が容易に入手可能なことから好ましい。核材が有機物
の例としては、ポリスチレン、ナイロン、各種ゴム類等
の高分子類があり、これらは架橋体であると耐溶剤性が
向上するので、例えばシート原材料中に溶剤が含有され
る場合に溶出がなく、シートの特性に影響が少ないこと
から好ましい。核材が高分子類のような変形可能な粒子
であると、製造時の加熱加圧により、シートからの突出
部を扁平化することや弾力性を付与することも可能であ
り、電極への接触面積の増大による信頼性の向上に有効
である。核材は、ガラス、セラミック、シリカ等の無機
物の粒子でも良く、この場合は高分子の核材に比べて更
に耐熱性の向上が可能となる。そして、その導電粒子の
直径は、中心粒径が2〜5000μm程度が好ましく、
5〜100μmにすれば更に好ましく、10〜80μm
にすれば特に好ましい。これらは所望の分解能に応じて
選択する。即ち、導電性粒子の粒径を隣接する電極や配
線パターン間距離の最小幅よりも小さくすることが、シ
ョートを防止し、配線の細線化に対応する上で必要であ
る。また、粒径が小さ過ぎるとシート厚みの減少により
強度が不足し、取り扱いがやりにくくなる。Further, as the conductive particles, various metals, alloys, oxides and the like having conductivity can be adopted. Materials that are preferably used in consideration of conductivity and corrosion resistance include Ni, Cu, and Ni.
These are particles of Al, Sn, Zn, Au, Pd, Ag, Co, Pb and the like. The particle shape is preferably substantially spherical, but may be any shape such as providing a large number of protrusions on the surface. Further, the conductive particles having a structure in which a thin metal layer is provided on the surface of a core material are preferable because spherical products having a uniform particle size can be easily obtained. Examples of the organic material in which the core material is an organic material include polymers such as polystyrene, nylon, and various rubbers.When these are cross-linked, the solvent resistance is improved.For example, when a solvent is contained in the sheet raw material. This is preferable because there is no elution and the properties of the sheet are hardly affected. When the core material is a deformable particle such as a polymer, it is possible to flatten a projection from the sheet or to impart elasticity by heating and pressing at the time of manufacturing, and it is possible to impart elasticity to the electrode. This is effective for improving reliability by increasing the contact area. The core material may be inorganic particles such as glass, ceramic, and silica. In this case, the heat resistance can be further improved as compared with a polymer core material. The diameter of the conductive particles is preferably such that the center particle diameter is about 2 to 5000 μm,
More preferably, the thickness is 5 to 100 μm, and 10 to 80 μm.
It is particularly preferred to set These are selected according to the desired resolution. That is, it is necessary to make the particle size of the conductive particles smaller than the minimum width of the distance between adjacent electrodes and wiring patterns in order to prevent short circuit and to cope with thinning of wiring. On the other hand, if the particle size is too small, the strength becomes insufficient due to the decrease in the sheet thickness, and the handling becomes difficult.
【0010】本発明に用いる異方導電膜に含ませる絶縁
粒子には、前記核材と同じものを用いることができ、ポ
リスチレン、ナイロン、各種ゴム類等の高分子類があ
り、これらは架橋体であると耐溶剤性が向上するので、
例えばシート原材料中に溶剤が含有される場合に溶出が
なく、シートの特性に影響が少ないことから好ましい。
核材が高分子類のような変形可能な粒子であると、製造
時の加熱加圧により、シートからの突出部を扁平化する
ことや弾力性を付与することも可能であり、電極への接
触面積の増大による信頼性の向上に有効である。核材
は、ガラス、セラミック、シリカ等の無機物の粒子でも
良く、この場合は高分子の核材に比べて更に耐熱性の向
上が可能となる。そして、その絶縁粒子の直径は、電極
の厚さの0.6〜1.3倍程度の範囲が好ましい。粒子
径が電極の厚さの0.6倍未満であると、バンプ2の埋
まり込みを抑制するのが少なく、粒子径が電極の厚さの
1.3倍を越えると、異方導電膜中の導電粒子による電
気的接続が困難となる。The insulating particles contained in the anisotropic conductive film used in the present invention may be the same as the core material, and include polymers such as polystyrene, nylon, and various rubbers. Since the solvent resistance is improved when
For example, when a solvent is contained in the sheet raw material, there is no elution, and it is preferable because the properties of the sheet are hardly affected.
When the core material is a deformable particle such as a polymer, it is possible to flatten a projection from the sheet or to impart elasticity by heating and pressing at the time of manufacturing, and it is possible to impart elasticity to the electrode. This is effective for improving reliability by increasing the contact area. The core material may be inorganic particles such as glass, ceramic, and silica. In this case, the heat resistance can be further improved as compared with a polymer core material. The diameter of the insulating particles is preferably in the range of about 0.6 to 1.3 times the thickness of the electrode. When the particle diameter is less than 0.6 times the thickness of the electrode, burying of the bump 2 is hardly suppressed, and when the particle diameter exceeds 1.3 times the thickness of the electrode, the particle diameter in the anisotropic conductive film is reduced. It becomes difficult to electrically connect the conductive particles.
【0011】この絶縁粒子を、導電粒子、及び樹脂と共
に、有機溶剤に混合してワニスとし、支持フィルムに塗
布し、加熱・半硬化させ、異方導電接着剤フィルムとし
て用いる。また、支持フィルムに塗布せずに、ワニスを
直接、配線板に塗布して異方導電膜を形成することもで
きる。The insulating particles, together with the conductive particles and the resin, are mixed with an organic solvent to form a varnish, applied to a support film, heated and semi-cured, and used as an anisotropic conductive adhesive film. Instead of coating the support film, a varnish can be directly applied to the wiring board to form the anisotropic conductive film.
【0012】絶縁粒子、導電粒子及び樹脂を混合する割
合は、支持フィルムに塗布する場合には、導電粒子:絶
縁粒子=90:10〜50:50となるようにすること
が好ましく、導電粒子がこの範囲未満であると、接続抵
抗が大きくなり回路の損失が大きくなり、絶縁粒子がこ
の範囲未満であると、半導体チップの端部と配線板の電
極が接触することを抑制する効果が小さく、絶縁粒子が
この範囲を超えると、導電粒子の妨げになり、電気的に
接続することが困難になる。そして、樹脂と導電粒子及
び絶遠粒子の割合は、樹脂:(導電及び絶縁)粒子=5
0:50〜10:90であることがより好ましい。When the insulating particles, the conductive particles and the resin are mixed on the support film, the ratio of the conductive particles to the insulating particles is preferably 90:10 to 50:50. If it is less than this range, the connection resistance increases and the loss of the circuit increases.If the insulating particles are less than this range, the effect of suppressing the contact between the end of the semiconductor chip and the electrode of the wiring board is small, If the insulating particles exceed this range, they hinder the conductive particles, making it difficult to electrically connect. Then, the ratio of the resin to the conductive particles and the far particles is: resin: (conductive and insulating) particles = 5
The ratio is more preferably 0:50 to 10:90.
【0013】[0013]
【実施例】異方導電性フィルムは、核材に平均粒径30
μmの架橋ポリスチレン粒子(ガラス転移点160℃)
を用い、表面を塩化パラジウム系の活性化処理を行った
後、無電解Niめっき液を用いて90℃でNiめっきを行
い、更にAuめっき液を用いて70℃で置換めっきを行
って金属薄層を被覆した導電性粒子と、絶縁粒子として
架橋ポリスチレン粒子(ガラス転移点160℃)の平均
直径がそれぞれ2μm、10μm、12μm、20μ
m、26μm、30μmの球状のものを、絶縁材料とし
て、ゴム変性可撓性エポキシ樹脂、マイクロカプセル型
潜在性硬化剤(活性化温度120℃)及びトルエン溶剤
を主成分(不揮発分50%)とする接着剤に、導電粒
子:絶縁粒子=50:50となるようにしたものを40
体積%添加してロール間隔40μmで形成した後、10
0℃で10分乾燥し、厚さ20μmの接着剤(純水で1
00℃10時間抽出後の抽出水のNaイオン、Clイオン
が各10ppm以下)を基材のテトラフルオロエチレンフ
イルム(セパレータ、厚さ50μm)の上に形成したも
のを用いた。配線板は、片面に厚さ18μmの銅箔を貼
り合わせた厚さ50μmのポリエチレンテレフタレート
フィルム製フレキシブル銅張り積層板の不要な銅箔の部
分を、塩化第二銅エッチング液をスプレー噴霧してエッ
チング除去し、ニッケル/金めっき(ニッケル2μm、
金0.2μm)を行い、厚さ約20μmの回路導体と厚
さ20μmの電極を形成して作製した。その電極に、異
方導電性フィルムを3mm×4mmに切断したものを貼
り付け、その上に、大きさが2mm×3mmで高さ15
μmのバンプを形成した半導体チップを搭載した、半導
体チップを電極に接続するために、図2に示すように、
電極14を有する配線板11を固定する固定板12と、
加圧ヘッド13と、その加圧ヘッド13を加熱する加熱
ヒータ15と、加圧ヘッド13を半導体チップ1を固定
する位置に移動させるXYステージ17とからなる加圧
装置16を用い、加圧ヘッド13には、その寸法が6m
m×6mmのものを用い、175℃で、0.4kgf/
cm2の圧力を20秒間加えた。そして、半導体チップ
を搭載した配線板の回路の短絡と接続不良とを、それぞ
れ100枚づつの試験片で調べたところ、表1のように
なった。EXAMPLE An anisotropic conductive film has an average particle size of 30 as a core material.
μm crosslinked polystyrene particles (glass transition point 160 ° C)
After performing a palladium chloride-based activation treatment on the surface, Ni plating is performed at 90 ° C. using an electroless Ni plating solution, and displacement plating is further performed at 70 ° C. using an Au plating solution. The conductive particles coated with the layer and the crosslinked polystyrene particles (glass transition point 160 ° C.) as insulating particles have an average diameter of 2 μm, 10 μm, 12 μm, and 20 μm, respectively.
m, 26 μm, and 30 μm spheres are used as insulating materials, with rubber-modified flexible epoxy resin, microcapsule-type latent curing agent (activation temperature of 120 ° C.), and toluene solvent as main components (nonvolatile content: 50%). Adhesive to be used is prepared by adding 40:50 conductive particles: insulating particles.
Volume% and formed at a roll interval of 40 μm.
After drying at 0 ° C. for 10 minutes, an adhesive having a thickness of 20 μm (1
The extraction water after extraction at 00 ° C. for 10 hours, Na ion and Cl ion each being 10 ppm or less) was formed on a tetrafluoroethylene film (separator, thickness 50 μm) as a base material. The wiring board is etched by spraying a cupric chloride etching solution on the unnecessary copper foil part of a flexible copper-clad laminate made of polyethylene terephthalate film with a thickness of 50 μm with a copper foil with a thickness of 18 μm bonded to one side. Removed, nickel / gold plating (nickel 2μm,
(Gold 0.2 μm) to form a circuit conductor having a thickness of about 20 μm and an electrode having a thickness of 20 μm. A 3 mm x 4 mm cut of an anisotropic conductive film was attached to the electrode, and the size was 2 mm x 3 mm and the height was 15 mm.
As shown in FIG. 2, in order to connect the semiconductor chip with the semiconductor chip having the μm bumps formed thereon to the electrodes,
A fixing plate 12 for fixing the wiring board 11 having the electrodes 14,
Using a pressure device 16 including a pressure head 13, a heater 15 for heating the pressure head 13, and an XY stage 17 for moving the pressure head 13 to a position where the semiconductor chip 1 is fixed, 13 has a size of 6m
m × 6 mm, 0.4 kgf /
A pressure of cm 2 was applied for 20 seconds. Then, the short circuit and the connection failure of the circuit of the wiring board on which the semiconductor chip was mounted were examined by using 100 test pieces, and the results were as shown in Table 1.
【0014】[0014]
【表1】 [Table 1]
【0015】表1に示すように、絶縁樹粒子の直径を、
電極の厚さ20μmの0.6〜1.3倍の範囲では、半
導体チップの短絡率が、大幅に低く、また、回路の接続
不良もなかった。As shown in Table 1, the diameter of the insulating tree particles is
In the range of 0.6 to 1.3 times the electrode thickness of 20 μm, the short-circuit rate of the semiconductor chip was significantly low, and there was no circuit connection failure.
【0016】[0016]
【発明の効果】以上に説明したとおり、本発明によっ
て、短絡のない配線板とその配線板を製造する方法を提
供することができる。As described above, according to the present invention, it is possible to provide a wiring board having no short circuit and a method for manufacturing the wiring board.
【図1】(a)は本発明の構成を示す上面図であり、
(b)はその断面図である。FIG. 1A is a top view showing a configuration of the present invention,
(B) is a sectional view thereof.
【図2】本発明の一実施例に用いた装置の側面図であ
る。FIG. 2 is a side view of an apparatus used in one embodiment of the present invention.
【図3】本発明の課題を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a problem of the present invention.
1.半導体チップ 2.バンプ 3.異方導電膜 4.絶縁粒子 11.配線板 12.固定板 13.加圧ヘッド 14.電極 15.加熱ヒータ 16.加圧装置 17.XYステージ 1. Semiconductor chip 2. Bump 3. Anisotropic conductive film 4. Insulating particles 11. Wiring board 12. Fixing plate 13. Pressure head 14. Electrode 15. Heater 16. Pressurizing device 17. XY stage
───────────────────────────────────────────────────── フロントページの続き (72)発明者 後藤 泰史 茨城県下館市大字五所宮1150番地 日立化 成工業株式会社五所宮事業所内 (72)発明者 井坂 和博 茨城県つくば市和台48 日立化成工業株式 会社総合研究所内 Fターム(参考) 5E319 AA03 AB05 BB16 CC61 GG20 5F044 KK01 LL09 QQ01 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yasushi Goto 1150 Goshonomiya, Shimodate-shi, Ibaraki Pref.Hitachi Kasei Kogyo Co., Ltd. F-term in the Research Institute of Japan, Ltd. (Reference) 5E319 AA03 AB05 BB16 CC61 GG20 5F044 KK01 LL09 QQ01
Claims (2)
して電子部品を接続した配線板であって、異方導電膜が
絶縁粒子を含む配線板。1. A wiring board in which electronic components are connected to electrodes formed on the wiring board via an anisotropic conductive film, wherein the anisotropic conductive film contains insulating particles.
して電子部品を接続する配線板の製造方法であって、異
方導電膜に絶縁粒子を含むものを用いる配線板の製造方
法。2. A method for manufacturing a wiring board for connecting an electronic component to an electrode formed on the wiring board via an anisotropic conductive film, wherein the anisotropic conductive film contains insulating particles. Method.
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JP23768699A JP4344966B2 (en) | 1999-08-25 | 1999-08-25 | Wiring board and manufacturing method thereof |
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JP23768699A JP4344966B2 (en) | 1999-08-25 | 1999-08-25 | Wiring board and manufacturing method thereof |
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JP2006215516A (en) * | 2005-02-07 | 2006-08-17 | Samsung Electronics Co Ltd | Display apparatus |
WO2008146688A1 (en) * | 2007-05-28 | 2008-12-04 | Sony Chemical & Information Device Corporation | Method for producing adhesive, method for connecting electronic component and bonded body |
EP2056406A1 (en) * | 2006-08-25 | 2009-05-06 | Hitachi Chemical Company, Ltd. | Circuit connecting material, connection structure for circuit member using the same and production method thereof |
US7967943B2 (en) | 1997-03-31 | 2011-06-28 | Hitachi Chemical Company, Ltd. | Circuit-connecting material and circuit terminal connected structure and connecting method |
JP2011198773A (en) * | 2011-06-28 | 2011-10-06 | Sony Chemical & Information Device Corp | Anisotropic conductive film, connection method, and connected body |
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1999
- 1999-08-25 JP JP23768699A patent/JP4344966B2/en not_active Expired - Fee Related
Cited By (11)
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US7967943B2 (en) | 1997-03-31 | 2011-06-28 | Hitachi Chemical Company, Ltd. | Circuit-connecting material and circuit terminal connected structure and connecting method |
US8142605B2 (en) | 1997-03-31 | 2012-03-27 | Hitachi Chemical Company, Ltd. | Circuit-connecting material and circuit terminal connected structure and connecting method |
JP2006215516A (en) * | 2005-02-07 | 2006-08-17 | Samsung Electronics Co Ltd | Display apparatus |
JP4542939B2 (en) * | 2005-02-07 | 2010-09-15 | サムスン エレクトロニクス カンパニー リミテッド | Display device |
US7982727B2 (en) | 2005-02-07 | 2011-07-19 | Samsung Electronics Co., Ltd. | Display apparatus |
EP2056406A1 (en) * | 2006-08-25 | 2009-05-06 | Hitachi Chemical Company, Ltd. | Circuit connecting material, connection structure for circuit member using the same and production method thereof |
EP2056406A4 (en) * | 2006-08-25 | 2010-09-08 | Hitachi Chemical Co Ltd | Circuit connecting material, connection structure for circuit member using the same and production method thereof |
EP2339695A1 (en) * | 2006-08-25 | 2011-06-29 | Hitachi Chemical Company, Ltd. | Circuit connecting material, connection structure for circuit member using the same and production method thereof |
WO2008146688A1 (en) * | 2007-05-28 | 2008-12-04 | Sony Chemical & Information Device Corporation | Method for producing adhesive, method for connecting electronic component and bonded body |
JP2008291161A (en) * | 2007-05-28 | 2008-12-04 | Sony Chemical & Information Device Corp | Method for producing adhesive, and method for connecting electrical component |
JP2011198773A (en) * | 2011-06-28 | 2011-10-06 | Sony Chemical & Information Device Corp | Anisotropic conductive film, connection method, and connected body |
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