JP2001061097A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image pickup device that photographs an object under lighting modulated at in other than 1/60 sec period, by using an electronic shutter so as to output a video signal whose luminance flicker is suppressed. SOLUTION: An image pickup means 111 including an image pickup device 102, an image pickup device drive circuit 110, an ASP-A/D converter 103, and a sychronizing circuit 104 is used to generate a signal S1 by photographing an object at an electronic shutter speed of 1/m sec within one vertical scanning period and a signal S2 by photographing an object at an electronic shutter speed of 1/n sec within one vertical scanning period. A microcomputer 109 of a gain control means 112 calculates a correction gain so that the ratio of the signal S1 to the signal S2 is n:m. A multiplier 105 multiplies the correction gain by the signal S2 to provide a signal S2' to a signal processing circuit 106. Thus, luminance flicker can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus capable of suppressing flicker generated in a video signal when an object is photographed by using an electronic shutter function under fluorescent lamp illumination.

[0002]

2. Description of the Related Art A conventional image pickup apparatus having a function of suppressing flicker is disclosed in Japanese Patent Application Laid-Open No. 7-274183. FIG. 14 is a block diagram showing a configuration of a main part of a conventional imaging device, that is, a video camera disclosed in the publication. This video camera has a lens 1401,
CCD 1402, CDS / AGC 1403, signal processing circuit 1404, differential amplifier 1405, clamp circuit 140
6, an LPF 1407, a voltage controlled oscillator 1408, a timing pulse generation circuit 1409, a drive circuit 1410, and a synchronization signal generation circuit 1411.

The operation of a video camera having such a configuration will be described. When a subject is photographed using the electronic shutter function under illumination that repeats blinking with a commercial AC power supply of 60 Hz, a difference initially occurs between the blinking cycle of the illumination and the cycle of the vertical synchronization signal. Therefore, a change occurs in the R component and the B component of the color signal. The R component and the B component are input to the differential amplifier 1405, and the differential amplifier 1405 outputs a BR signal whose level periodically changes. This BR signal is supplied to a clamp circuit 1406.
And LPF 1407 to the voltage controlled oscillator 1408, and the BR signal causes the voltage controlled oscillator 140
8 is controlled. Then, the periods of the vertical transfer pulse, the horizontal transfer pulse, and the signal charge sweeping-out pulse output from the timing pulse generation circuit 1409 are respectively adjusted based on the clock output from the voltage controlled oscillator 1408, whereby the illumination flickers. The period and the period of the vertical synchronizing signal match. As described above, when the flickering cycle of the illumination completely matches the cycle of the vertical synchronization signal, color flicker does not occur.

[0004]

In such a conventional image pickup apparatus, no matter what kind of commercial frequency is used for image pickup under a fluorescent lamp, the output video signal contains flicker. Not required. However, in the above conventional example, when the electronic shutter function is used to capture an image under illumination that repeats blinking with a 50 Hz AC power supply, the vertical synchronizing signal has a repetition frequency of 60 Hz, and luminance flicker occurs. There is a problem of getting it.

Further, in the above-mentioned conventional example, the BR signal whose level changes periodically is detected and adjusted so that the blinking period of the illumination and the period of the vertical synchronizing signal coincide with each other. There is also a problem that a malfunction may occur if the -R signal is erroneously detected.

In the above-mentioned conventional example, the adjustment is performed so that the period of the vertical synchronization signal coincides with the blinking period of the illumination. Therefore, if the period of the vertical synchronization signal changes more than a specified value, the vertical synchronization is lost. is there.

The present invention has been made in view of such a conventional problem, and compares a signal level of a video signal photographed using an electronic shutter function with a signal level of a video signal having no flicker. It is another object of the present invention to provide an imaging apparatus capable of outputting a video signal with reduced luminance flicker and color flicker by performing gain control so that the comparison result always has a constant ratio.

[0008]

In order to solve such a problem, the invention of claim 1 of the present application relates to an S1 signal captured at an electronic shutter speed of 1 / m second within one vertical scanning period. An imaging means for outputting an S2 signal captured at an electronic shutter speed of n seconds, and a ratio of the S1 signal and the S2 'signal obtained by correcting the S2 signal with the S2 correction gain is n: m
And a gain control means for calculating the S2 correction gain so as to obtain the S2 signal, multiplying the S2 signal by the S2 correction gain, and outputting a result of the multiplication as the flicker-suppressed S2 ′ signal. It is assumed that.

According to such a configuration, a flicker can be reduced by using, as an S1 signal, a signal captured at 1/100 second, for example, as an electronic shutter speed of 1 / m second. Also, flicker correction can be performed by multiplying the S2 signal by an S2 correction gain so that the ratio of the S1 signal and the S2 'signal with reduced flicker becomes n: m. Therefore, when photographing is performed at an electronic shutter speed of 1 / n second, a video signal without flicker can be output.

According to a second aspect of the present invention, there is provided an image pickup device for outputting an S1 signal imaged at an electronic shutter speed of 1 / m second and an S2 signal imaged at an electronic shutter speed of 1 / n second within one vertical scanning period. Means, an S1 integration circuit for calculating an integrated value ΣS1 of the S1 signal during one vertical scanning period,
S2 for calculating integral value ΣS2 of one signal in one vertical scanning period
Using the integration circuit and the data of ΣS1 and ΣS2, the S2 signal is adjusted so that the ratio of the S1 signal and the S2 ′ signal obtained by correcting the S2 signal with the S2 correction gain becomes n: m.
A control unit that calculates a correction gain and outputs the S2 correction gain with a delay of a predetermined time; and the S2 correction gain generated by the control unit is multiplied by the S2 signal. And a multiplier that outputs the signal as an S2 ′ signal.

[0011] According to such a configuration, a flicker can be reduced by using, as an S1 signal, a signal captured at 1/100 second, for example, at an electronic shutter speed of 1 / m second. Also, flicker correction can be performed by multiplying the S2 signal by an S2 correction gain so that the ratio of the S1 signal and the S2 'signal with reduced flicker becomes n: m. When shooting at an electronic shutter speed of 1 / n second, a video signal without flicker can be output.

According to a third aspect of the present invention, there is provided an image pickup device for outputting an S1 signal imaged at an electronic shutter speed of 1 / m second and an S2 signal imaged at an electronic shutter speed of 1 / n second within one vertical scanning period. Means for dividing a screen area of one vertical scanning period into a plurality of blocks Bi (i is a block number);
The S1 signal for each block is integrated, and the integrated value BiΣS
1, an S2 block division and integration circuit that integrates the S2 signal for each of the blocks Bi in the screen area during one vertical scanning period to calculate an integral value BiΣS2, and the BiΣS1 and the BiΣS2. The BiS2 correction gain is calculated for each of the blocks Bi so that the ratio of the S1 signal and the BiS2 ′ signal obtained by correcting the S2 signal with the BiS2 correction gain in each block Bi is n: m using the above data. And a control unit that outputs the BiS2 correction gain with a delay of a predetermined time, and the S2 signal is multiplied by the BiS2 correction gain generated by the control unit for each block Bi, and flicker is suppressed in the multiplication result. And a block multiplier for outputting the signal as the S2 'signal.

According to such a configuration, flicker can be reduced by using, as an S1 signal, a signal imaged at 1/100 second, for example, at an electronic shutter speed of 1 / m second. Also, flicker correction can be performed by multiplying the S2 signal by an S2 correction gain so that the ratio of the S1 signal and the S2 'signal with reduced flicker becomes n: m for each block. For this reason, when a specific color of the subject is flickering, only the flicker portion can be corrected, and a video signal without flicker can be output when photographing is performed at an electronic shutter speed of 1 / n second. .

According to a fourth aspect of the present invention, there is provided an imaging apparatus for outputting an S1 signal captured at an electronic shutter speed of 1 / m second and an S2 signal captured at an electronic shutter speed of 1 / n second within one vertical scanning period. Means, an S1C integration circuit for calculating an integration value ΣS1 of the S1 signal for one vertical scanning period for each color signal, and an S2C integration circuit for calculating an integration value ΣS2 of the S2 signal for one vertical scanning period for each color signal. Using the data of ΣS1 and ΣS2, the S2 correction gain is calculated such that the ratio of the S1 signal and the S2 ′ signal obtained by correcting the S2 signal with the S2 correction gain is n: m for each color signal. Control means for outputting the S2 correction gain for each color signal with a delay of a predetermined time; and multiplying the S2 signal by the S2 correction gain generated by the control means for each color signal. Deterrence A multiplier for outputting as the S2 'signal, is characterized in that it comprises a.

According to a fifth aspect of the present invention, there is provided an image pickup device for outputting an S1 signal imaged at an electronic shutter speed of 1 / m second and an S2 signal imaged at an electronic shutter speed of 1 / n second within one vertical scanning period. Means, and for each color signal, a screen area of one vertical scanning period of the S1 signal is divided into a plurality of blocks Bi (i
Is a block number), integrates the S1 signal for each block, calculates an integrated value BiΣS1C, and calculates an integrated value BiΣS1C. The S for each block Bi
An S2 block-divided C integrating circuit for integrating the two signals to calculate an integrated value BiΣS2C, the BiΣS1C and the Bi
を Using the S2C data, the BiS2 correction gain is set to the block so that the ratio of the S1 signal to the S2 ′ signal obtained by correcting the S2 signal with the BiS2 correction gain is n: m for each color signal and each block Bi. And a control means for calculating for each color signal and outputting the BiS2 correction gain after a predetermined time delay, and multiplying the S2 signal for each block and color signal by a BiS2 correction gain generated by the control means, The multiplication result is obtained by the above S2 ′ in which flicker is suppressed.
And a block multiplier for outputting as a signal.

According to such a configuration, flicker can be reduced by using a signal captured at, for example, 1/100 second as the S1 signal with an electronic shutter speed of 1 / m second. Also, the ratio between the S1 signal and the S2 ′ signal with reduced flicker is n: m for each color filter and block.
Flicker correction can be performed by multiplying the S2 signal by the S2 correction gain. Therefore, when a specific block or color of the subject is flickering,
It is possible to correct only the flicker portion, and it is possible to output a video signal without flicker when photographing at an electronic shutter speed of 1 / n second.

According to a sixth aspect of the present invention, in the imaging apparatus according to any one of the first to fifth aspects, when the blinking cycle of the illumination device for illuminating the subject is different from the vertical scanning cycle of the imaging means, A shutter speed of 1 / msec is made equal to a blinking cycle of the illumination device.

According to a seventh aspect of the present invention, in the imaging apparatus according to any one of the first to fifth aspects, when the blinking cycle of the illumination device for illuminating a subject is different from the vertical scanning cycle of the imaging means, Shutter speed 1 / msec 1/10
It is characterized in that it is set to 0 seconds.

[0019]

(Embodiment 1) An imaging apparatus according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of the imaging device according to the first embodiment. In FIG. 1, an imaging unit 111 indicated by a broken line includes an optical system 101 and an imaging device 10.
2. ASP / A / D converter 103, synchronization circuit 104,
An S1 signal, which is composed of an image sensor driving circuit 110 and is captured at an electronic shutter speed of 1 / m second within one vertical scanning period, and S2 which is captured at an electronic shutter speed of 1 / n second
It has a function of an imaging unit that outputs a signal.

The image pickup device (CCD) 102 includes the optical system 10
When the optical image of the subject formed by the step 1 is incident, the pixel image is photoelectrically converted and a pixel signal is output. Image sensor 1
02 is supplied to the ASP / A / D converter 103. The ASP / A / D converter 103 samples the output signal of the image sensor 102, adjusts the gain, and then performs analog / digital conversion for output. ASP ・ A /
The output of the D converter 103 is provided to the synchronization circuit 104. The synchronization circuit 104 generates pixel signals having different accumulation timings and accumulation times as the S1 signal and the S2 signal.
This is a circuit that outputs the signals 1 and S2 at the same timing. The image sensor driving circuit 110 drives the image sensor 102 according to a control signal from the microcomputer 109.

The signal processing circuit 106 performs signal processing such as contour enhancement on the S2 'signal obtained by correcting the S2 signal,
It outputs a video signal Sout. The gain control means 112 indicated by the broken line part includes the multiplier 105, the S1 integration circuit 10
7, an S2 integration circuit 108 and a microcomputer (microcomputer) 109. The S1 signal and the S2 signal are
The S2 correction gain is calculated so that the ratio to the S2 'signal corrected by the correction gain is n: m, the S2 signal is multiplied by the S2 correction gain, and the multiplication result is S2' in which flicker is suppressed.
It has the function of gain control means for outputting as a signal.

The S2 signal output from the synchronizing circuit 104 is supplied to a signal processing circuit 106 via a multiplier 105 and also to an S2 integrating circuit 108. The S1 signal output from the synchronization circuit 104 is provided to the S1 integration circuit 107. The S1 integrator circuit 107 calculates S1
A signal is input, integration is performed for one vertical scanning period, and an integration value Σ
This is a circuit that outputs S1. The S2 integration circuit 108 calculates S2
A signal is input, integration is performed for one vertical scanning period, and an integration value Σ
This is a circuit that outputs S2. Integral value ΣS1 and integral value ΣS
2 is input to the microcomputer 109 as control means.

The microcomputer 109 includes an image pickup device driving circuit 11
0 and outputs a control signal to the S1 integration circuit 1
07 and S2 given by the integrator 108
From S2, S1 signal and S output from multiplier 105
S2 such that the ratio of the signal level to the 2 ′ signal becomes n: m.
The correction gain is calculated, the timing is adjusted and the multiplier 10 is adjusted.
5 is control means. The multiplier 105 is a circuit that multiplies the S2 signal by an S2 correction gain and outputs the multiplication result as an S2 ′ signal.

Here, the synchronization circuit 104 will be described in detail. As shown in FIG. 2, the synchronization circuit 104 includes a selector 301, a first memory 302, and a second memory 303. The selector 301 is the ASP / A / D of FIG.
When a signal is input from the converter 103, the S1 signal and S2
It is a circuit that separates it into signals. The separated S1 signal is stored in the first memory 302, and the S2 signal is stored in the second memory 303.

The principle of operation of the synchronization circuit 104 is shown in the timing chart of FIG. The vertical synchronizing signal VD shown in FIG. 3A is a synchronizing signal whose vertical scanning period is 1/60 second. As shown in FIG. 3B, the charge accumulation timing in the image sensor 102 is synchronized with the vertical synchronization signal. The accumulation time of the S1 signal is set to 1 / m second, and here, the signal charge is accumulated at 1/100 second which is equal to the blinking cycle of the lighting device. Also, the accumulation time of the S2 signal is set to 1 / n second, and here, the signal charge is accumulated at 1 / n second = 1/400 second. FIG.
As shown in (c), a read pulse is generated at the end of accumulation of the S1 signal and the S2 signal. As shown in FIG. 3D, the S1 signal and the S2 signal are generated by these read pulses.
A signal is output from the image sensor 102. The signal including the S1 signal and the S2 signal is input to the synchronization circuit 104 via the ASP / A / D converter 103 in FIG. In the synchronization circuit 104, the selector 301 separates the S1 signal and the S2 signal from the input signal. The S1 signal is input from the image sensor 102 to the synchronization circuit 104 at the timing A shown in FIG. 3D, and is output from the synchronization circuit 104 at the timing C shown in FIG. The S2 signal is input from the image sensor 102 to the synchronization circuit 104 at the timing B shown in FIG. 3D, and is synchronized at the timing D shown in FIG.
04. Thus, at the same timing C,
The S1 signal and the S2 signal are output in accordance with D, and supplied to the gain control means 112.

The first memory 302 shown in FIG. 2 starts writing the S1 signal at the timing A shown in FIG. Also, the second memory 303
Starts writing the S2 signal at timing B and starts reading at timing D. Thus, the S1 signal and the S2 signal are output at the same timing.

The operation of the imaging apparatus according to Embodiment 1 configured as described above will be described. In FIG.
An optical image of a subject formed by the optical system 101 is incident on an image sensor (CCD) 102 and is photoelectrically converted. For example, an electronic shutter speed of 1 / m second is 1/100
Seconds and 1 / n second electronic shutter speed of 1
/ 400 seconds. In the image sensor 102, 1
The S1 signal accumulated at an electronic shutter speed of 1/100 second and the S2 signal accumulated at an electronic shutter speed of 1/400 second during the vertical scanning period are output.

The output of the image pickup device 102 is input to an ASP / A / D converter 103, where it is sampled and gain-adjusted, and then subjected to analog / digital conversion. ASP / A / D
When the output of the converter 103 is input to the synchronization circuit 104, it is separated into the S1 signal and the S2 signal, and output at the same timing. S output from the synchronization circuit 104
The two signals are multiplied by the S2 correction gain in the multiplier 105, and the corrected S2 ′ signal is input to the signal processing circuit 106. The signal processing circuit 106 performs signal processing such as contour enhancement on the S2 'signal and outputs a video signal Sout.

Here, the image sensor 102 will be described with reference to FIGS.
And the operation of the synchronization circuit 104 will be specifically described. The vertical synchronizing signal VD shown in FIG. 3A is a synchronizing signal having a period of the vertical scanning period, that is, a period of 1/60 second, as described above. The image sensor 102 is driven in synchronization with the vertical synchronization signal. As shown in FIG. 3B, the charge of the S1 signal is accumulated for a period of 1/100 second in synchronization with the vertical synchronization signal. Also, S2
The signal is also accumulated for a period of 1/400 second. Next, FIG.
As shown in (c), when the accumulation of the S1 signal and the S2 signal is completed, a read pulse is output. As shown in FIG. 3D, the S1 signal and the S2 signal are output from the image sensor 102 by these read pulses. These S1 signals and S
The two signals are input to the synchronization circuit 104 via the ASP / A / D converter 103.

The selector 301 shown in FIG.
Signal and the S2 signal. The separated S1 signal is stored in the first memory 302, and the S2 signal is stored in the second memory 303. The first memory 302 is shown in FIG.
The writing of the S1 signal is started at a timing A shown in FIG. 3D, and the reading is started at a timing C in FIG.
The second memory 303 starts writing the S2 signal at the timing B in FIG. 3D and starts reading at the timing D in FIG. 3F. By doing so, the S1 signal and S
The output timings of the two signals match.

Next, the operation of flicker correction will be described with reference to FIGS. FIG. 4 is a schematic diagram illustrating a change in accumulated charge of the image sensor 102 when the image capturing apparatus according to the present embodiment is illuminated by a fluorescent lamp of an AC power supply having a commercial frequency of 50 Hz. When illuminated by a fluorescent lamp driven at 50 Hz, an image of a subject is captured and signal charges are accumulated every vertical scanning period at an electronic shutter speed of 1/100 second, and any vertical scanning period shown in FIG. FIG.
As shown by the hatched portions in (b) and (c), substantially the same accumulated charges are obtained. In addition, when illuminated by a fluorescent lamp driven at 50 Hz, an image of a subject is captured and signal charges are accumulated every vertical scanning period at an electronic shutter speed of 1/400 second.
As shown in (d), the accumulation timing differs for each vertical scanning period. For this reason, as indicated by the hatched portion shown in FIG.
The accumulated charge amount fluctuates in a cycle of three vertical scanning periods.

Therefore, under a fluorescent lamp driven at 50 Hz,
When the image is captured at the electronic shutter speed of 1/100 second,
When charge is accumulated for 1/100 second every vertical scanning period,
As shown in FIG. 4C, almost the same accumulated charge is obtained in every vertical scanning period, so that flicker does not occur. Also, 50
When an image is taken at an electronic shutter speed of 1/400 second under a fluorescent lamp driven at 1 Hz, 1/40 every vertical scanning period
If charge is accumulated for only 0 seconds, the accumulation timing differs for each vertical scanning period, so that the accumulated electric charge fluctuates in a cycle of three vertical scanning periods, and flicker occurs.

When the S1 signal output from the synchronization circuit 104 is input to the S1 integration circuit 107, the S1 integration circuit 1
07 integrates the S1 signal over one vertical scanning period and outputs an integrated value 積分 S1. Similarly, when the S2 signal output from the synchronization circuit 104 is input to the S2 integration circuit 108, the S2 integration circuit 108 integrates the S2 signal over one vertical scanning period and outputs an integrated value 積分 S2. These integral values ΣS1 and ΣS2 are input to the microcomputer 109.

The microcomputer 109 calculates S from S1 and S2.
The S2 correction gain is calculated so that the ratio between the 1 signal and the S2 ′ signal output from the multiplier 105 is n: m, that is, 400: 100, and the S2 correction gain is output to the multiplier 105 after a predetermined time delay. . At this time, since the signal level of the luminance flicker fluctuates in a cycle of three vertical scanning periods, {S1 and {
The time delayed by three vertical scanning periods from the calculated vertical scanning period for S2 is defined as a predetermined delay time. The multiplier 105 multiplies the S2 signal by an S2 correction gain, and obtains S2
Two signals are output. The signal processing circuit 106 performs signal processing such as contour enhancement on the input S2 signal ′,
The video signal Sout is output.

Since the S1 signal is originally a signal captured at an electronic shutter speed of 1/100 second, flicker does not occur. The ratio with the S1 signal without flicker is always 40
Since the S2 signal is multiplied by the S2 correction gain and corrected so as to be 0: 100, the corrected S2 signal ′ obtained by imaging at an electronic shutter speed of 1/400 second is a flicker-free video signal.

In the above description of the operation, 1/100 second is set as the electronic shutter speed of 1 / m second.
Although 1/400 second is set as the electronic shutter speed of 1 / n second, another combination may be used. To change the combination of the electronic shutter speeds to a value other than 1/100 seconds and 1/400 seconds, the microcomputer 109 sends a control signal for changing the electronic shutter speed to the image sensor driving circuit 110, and the designated electronic shutter speed , The image sensor driving circuit 110 drives the image sensor 102. The electronic shutter speed of 1 / m second needs to be close to 1/100 second, but the electronic shutter speed of 1 / n second is 1/100 second.
The value may be a value other than 400 seconds, and flicker can be reduced by exactly the same operation.

The S1 signal and the S2 signal are read from one image sensor 102 in the imaging unit 111 indicated by a broken line in FIG. 1, and these signals are supplied to the synchronization circuit 104.
Although the S1 signal and the S2 signal are output at the same timing, the same effect can be obtained by using another image sensor or sensor as long as the S1 signal that originally does not cause flicker is output. it can.

(Embodiment 2) Next, an image pickup apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 5 is a block diagram illustrating a configuration of the imaging device according to the present embodiment. The same parts as in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. In the image pickup means 111 shown in FIG.
When an optical image of a subject formed by the optical system 101 is incident, photoelectric conversion is performed to output a pixel signal. The output of the image sensor 102 is the ASP / A / D converter 10
3 given. The ASP / A / D converter 103 samples the output signal of the image sensor 102, adjusts the gain, and then performs analog / digital conversion for output.
The output of the ASP / A / D converter 103 is output to the synchronization circuit 104.
Given to. The synchronizing circuit 104 is a circuit that generates pixel signals having different accumulation times and accumulation times as the S1 signal and the S2 signal, and outputs the S1 signal and the S2 signal at the same timing.

The signal processing circuit 106 includes the block multiplier 5
The signal processing such as edge enhancement is performed on the S2 'signal output from the controller 05, and a video signal Sout is output. The gain control means 512 indicated by a broken line portion includes a block multiplier 505, an S1 block division and integration circuit 507, an S2 block division and integration circuit 508, and a microcomputer 509. The S1 signal output from the synchronization circuit 104 is supplied to the S1 block integration circuit 507, and the S2 signal is supplied to the block multiplier 505 and also to the S2 block integration circuit 508.

The S1 block dividing / integrating circuit 507 receives the S1 signal, divides the screen area for one vertical scanning period into a plurality of blocks, and generates a block i (i indicates a block number, for example, 01, 02... 48). Integral value Bi)
This is a circuit for calculating 算出 S1. Similarly, the S2 block division integration circuit 508 is a circuit that receives the S2 signal, divides the screen area in one vertical scanning period into a plurality of blocks, and calculates an integral value BiΣS2 for each block i. BiΣS1 output from the S1 block division integration circuit 507, and S2
BiΣS2 output from block division integration circuit 508
Is input to the microcomputer 509 as control means.

The microcomputer 509 includes the image pickup device driving circuit 11
0, a control signal is output, and BiΣS1 and B
From iΣS2, the S2 correction gain is calculated such that the ratio of the S1 signal output from the synchronization circuit 104 to the S2 ′ signal output from the block multiplier 505 becomes n: m for each divided block i. Control means for outputting to the block multiplier 505. The block multiplier 505 is a circuit that multiplies the S2 signal by the S2 correction gain for each block at the same timing and outputs the multiplication result as the S2 'signal.

FIG. 6 is an explanatory diagram showing a method of dividing a screen area into blocks in one vertical scanning period in this embodiment. As shown in this figure, the screen of one frame is divided into eight in the horizontal direction and six in the vertical direction, and the entire screen area is B01,
It is divided into 48 blocks, such as B02,... Bi. An area indicated by oblique lines is an area where flicker occurs (a flicker area).

FIG. 7 is a block division integration circuit 507 of FIG.
And FIG. 508 is a block diagram showing the configuration of a block division integration circuit 700. The block division and integration circuit 700 shown in FIG.
, 703 and a selector circuit 705. The multiplexer 701 outputs a signal from the synchronization circuit 104 to S
When one signal or S2 signal is input, the divided block Bi
This is a circuit that distributes pixel signals for each (i = 01 to 48). The integration circuits 702, 703,... 704 perform integration for one vertical scanning period for each block Bi, and the integrated value BiＢS
n is a circuit that outputs n. The selector circuit 705 is a circuit that sequentially selects and outputs the integral value BiΣSn for each block.

FIG. 8 is a block diagram showing the configuration of the block multiplier 505. This block multiplier 505 has 48
Block gain registers 801, 802,... 8
03, a selector 804, and a multiplier 805. The block gain register 801 (B1GR) stores B1S among the BiS2 correction gains calculated by the microcomputer 509.
When the second correction gain (B1G) is input, the B1S2 correction gain is temporarily held. Similarly, the block gain register 802 (B2GR)
When the B2S2 correction gain is input among the BiS2 correction gains calculated in (2), the B2S2 correction gain (B2G
R) is temporarily held. Thus, 48 correction gains B1G, B2G,... B48G are set in each register. The set BiS2 correction gain is read from the selector 804 in synchronization with the S2 signal, and is provided to the multiplier 805. The multiplier 805 is a circuit that multiplies the S2 signal by the BiS2 correction gain for each block Bi and outputs an S2 ′ signal.

The operation of the imaging apparatus according to Embodiment 2 configured as described above will be described. In FIG. 5, when an optical image of a subject formed by an optical system 101 is incident on an image sensor (CCD) 102, it is photoelectrically converted. For example, as an electronic shutter speed of 1 / m second, 1
/ 100 sec. And 1/400 sec. As the electronic shutter speed of 1 / n sec.
Outputs an S1 signal accumulated at an electronic shutter speed of 1/100 second and an S2 signal accumulated at an electronic shutter speed of 1/400 second within one vertical scanning period. When the output of the image sensor 102 is input to the ASP / A / D converter 103, it is sampled, gain-adjusted, and subjected to analog / digital conversion. The synchronization circuit 104 is an ASP
Separate the S1 signal and the S2 signal from the signal output from the A / D converter 103, and output them at the same timing. The S2 signal output from the synchronization circuit 104 is provided to the signal processing circuit 106 via the block multiplier 505. The signal processing circuit 106 performs signal processing such as contour enhancement on the S2 'signal output from the block multiplier 505, and outputs a video signal Sout.

The driving operation of the image sensor 102 and the operation of the synchronization circuit 104 will be specifically described with reference to FIGS. The vertical synchronization signal VD shown in FIG. 3A is a synchronization signal having a period of one vertical scanning period, that is, a period of 1/60 second. The image sensor 102 is driven in synchronization with the vertical synchronization signal. As shown in FIG. 3B, the charge accumulation timing of the S1 signal is synchronized with the vertical synchronization signal, and the signal charge is accumulated for a period of 1/100 second. Is done. The S2 signal is 1 /
It is accumulated for a period of 400 seconds. Also, as shown in FIG. 3C, a pulse is generated at the end of the accumulation of the S1 signal and the S2 signal. As shown in FIG. 3D, the S1 signal and the S2 signal are output from the image sensor 102 by these read pulses. The pixel signal including the S1 signal and the S2 signal passes through the ASP / A / D converter 103,
4 is input.

In the synchronizing circuit 104 shown in FIG. 2, the selector 301 separates the S1 signal and the S2 signal. The separated S1 signal and S2 signal are input to a first memory 302 and a second memory 303, respectively. First memory 302
Starts writing the S1 signal at timing A in FIG. 3D and starts reading it at timing C in FIG. 3E. Further, the second memory 303 starts writing the S2 signal at timing B and starts reading at timing D. Thus, the synchronization circuit 104 outputs the S1 signal and the S2 signal at the same timing.

Next, the operation of flicker correction will be described with reference to FIG. As shown in FIG. 4B, consider a case where a subject is imaged under an electronic shutter speed of 1/100 second under a fluorescent lamp driven at 50 Hz. When electric charges are accumulated for 1/100 second every vertical scanning period, almost the same accumulated electric charge is obtained in every vertical scanning period as shown in FIG. 4C, so that flicker does not occur. Also, as shown in FIG. 4D, under a fluorescent lamp driven at 50 Hz, 1/400
Consider a case where a subject is imaged at an electronic shutter speed of seconds. If the charge is accumulated for 1/400 second for each vertical scanning period, the accumulation timing for each vertical scanning period is different. Therefore, as shown by the hatched portions in FIGS. It fluctuates in the period cycle. The fluctuation of the cycle of the three vertical scanning periods causes flicker.

S output from the synchronization circuit 104 in FIG.
The 1 signal and the S2 signal are respectively divided into an S1 block division and integration circuit 5
07 and the S2 block dividing and integrating circuit 508.
The S1 block dividing and integrating circuit 507 and the S2 block dividing and integrating circuit 508 respectively generate one signal for the S1 signal and one for the S2 signal.
The screen area in the vertical scanning period is divided into a plurality of blocks as shown in FIG. 6, and integration is performed in each block. For this reason, the multiplexer 701 of FIG. 7 distributes the Sn (n is 1 or 2) signal for each block Bi (i = 0, 02,..., 48) and supplies the signal to any of the corresponding integration circuits 702 to 704. The integration circuits 702, 703,... 704 integrate the pixel signals distributed to the blocks, and obtain an integrated value BiΣS
1 and BiΣS2 are calculated. Integral value BiΣS1 and Bi
$ S2 is switched by the selector circuit 705 and sequentially input to the microcomputer 509.

The microcomputer 509 shown in FIG.
Based on S2, the BiS2 correction gain is calculated such that the ratio of the S1 signal and the S2 'signal for each divided block is n: m, that is, 400: 100, and the calculation result is delayed for a predetermined time to obtain a block multiplier 505. Output to Since the signal level of the luminance flicker in this case fluctuates in the cycle of three vertical scanning periods, the BiS2 correction gain is set to a predetermined time, with a time delayed by three vertical scanning periods from the vertical scanning period in which BiΣS1 and BiΣS2 are calculated as a predetermined time. The output is delayed and output to the block multiplier 505.

In the block multiplier 505 shown in FIG. 8, the input BiS2 correction gain is stored in a block gain register (B1GR) 801, a block gain register (B2GR) 802,... Hold. Then, the selector circuit 804 reads out the BiS2 correction gain at the same timing and supplies it to the multiplier 805. The multiplier 805 multiplies the S2 signal by a BiS2 correction gain for each block Bi. The multiplication result of the block multiplier 505 is provided to the signal processing circuit 106 of FIG. 5 as a corrected S2 ′ signal. The signal processing circuit 106 performs signal processing such as contour enhancement on the S2 'signal, and outputs a video signal Sout.

Since the S1 signal is a signal captured at an electronic shutter speed of 1/100 second, flicker does not occur. Thus, the ratio with the S1 signal without flicker is always 4
Since the S2 signal for each block is multiplied by the BiS2 correction gain so as to be 00: 100, flicker is not included in the S2 ′ signal. At this time, as shown by the hatched portion in FIG. 6, even if a part of the subject is flickering, the ratio of the S1 signal to the S2 'signal is 400:
Since flicker correction is performed so as to be 100, it is possible to correct only a flicker portion without overcorrecting a portion having no flicker.

In the above description of the operation, the electronic shutter speed of 1 / m second is set to 1/100 second,
Although the electronic shutter speed of n seconds was set to 1/400 second, the electronic shutter speed was set to 1/100 or 1/4.
To change to a value other than 00 seconds,
By transmitting a control signal for changing the electronic shutter speed to the image sensor driving circuit 110, the image sensor 102 can be driven in accordance with the designated electronic shutter speed. The electronic shutter speed of 1 / m second is 1 /
Although the setting needs to be close to 100 seconds, the electronic shutter speed of 1 / n second can reduce flicker by exactly the same operation even if it is other than 1/400 second.

In the above description of the operation, the screen is divided into eight horizontal blocks and six vertical blocks in one vertical scanning period. However, if the partial flicker area matches the divided block,
Partial flicker can be reduced even in a case other than the block division of 8 horizontal divisions and 6 vertical divisions.

In the above description of the operation, the S1 signal and the S2 signal are read from one image sensor 102, and the S1 signal and the S2 signal are output at the same timing by the synchronization circuit 104. However, a similar effect can be obtained by using another image sensor or sensor as long as it outputs an S1 signal without flicker.

(Embodiment 3) Next, an image pickup apparatus according to Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 9 is a block diagram illustrating a configuration of an imaging device according to the present embodiment. The same parts as in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. In the imaging means 111 of FIG. 9, an image sensor (CCD) 102
When an optical image of a subject formed by the optical system 101 is incident, photoelectric conversion is performed to output a pixel signal. The output of the image sensor 102 is the ASP / A / D converter 10
3 given. The ASP / A / D converter 103 samples the output signal of the image sensor 102, adjusts the gain, and then performs analog / digital conversion for output.
The output of the ASP / A / D converter 103 is output to the synchronization circuit 104.
Given to. The synchronizing circuit 104 is a circuit that generates pixel signals having different accumulation times and accumulation times as the S1 signal and the S2 signal, and outputs the S1 signal and the S2 signal at the same timing.

FIG. 10A is a layout diagram showing an arrangement of color filters of the image sensor 102 in the present embodiment.
FIG. 3B is a schematic diagram illustrating a pixel mixed reading method of the EVEN field and the ODD field in the image sensor 102. In FIG. 10A, the color filter is a complementary color filter, and Mg indicates magenta, Cy indicates cyan, Ye indicates yellow, and G indicates green. As shown in FIG. 10B, a color signal is read out by changing the combination of lines for mixing pixels for each field. Mg + Cy (MC) and G +
A repetition line of Ye (GY) and a line of repetition of G + Cy (GC) and Mg + Ye (MY) are alternately read to output a color signal.

The signal processing circuit 106 shown in FIG.
The signal processing such as contour enhancement is performed on the S2 'signal output from No. 5 to output a video signal Sout. The gain control means 912 indicated by a broken line includes a multiplier 105, a gain register 901, a selector 902, and an S1C integration circuit 9.
07, an S2C integration circuit 908, and a microcomputer 909. The S2 signal output from the synchronization circuit 104 is supplied to the signal processing circuit 106 via the multiplier 105 and also to the S2C integration circuit 908. The S1 signal output from the synchronization circuit 104 is S1C
The signal is provided to the integration circuit 907.

FIG. 11 is a block diagram showing the configuration of the S1C integration circuit 907 and the S2C integration circuit 908. Since both circuits have the same configuration, they are shown as SnC integration circuits 1100. The SnC integration circuit 1100 includes a multiplexer 1101, an integration circuit (ΣMY) 1102, an integration circuit (ΣGC) 1103, and an integration circuit (ΣGY) 110.
4. It is composed of an integration circuit (１０５MC) 1105 and a selector 1106. The multiplexer 1101 is a circuit that distributes the input signal S1 or the input signal S2 from the synchronization circuit 104 for each color filter (color signal). Integration circuit 11
Reference numerals 02, 1103, 1104, and 1105 denote circuits for calculating integral values ΣMY, ΣGC, ΣGY, and ΣMC for one vertical scanning period, respectively. The selector 1106 selects these integrated values and outputs them in order.

The signal processing circuit 106 shown in FIG.
Signal processing such as edge enhancement is performed on the S2 'signal corrected in step 5, and a video signal Sout is output. S
ΣS1C output from the 1C integration circuit 907 and ΣS2C output from the S2C integration circuit 908 are input to a microcomputer 909 as control means.

The microcomputer 909 includes the image pickup device driving circuit 11
0 and outputs a control signal, and outputs S1C and S
From 2C, the S1 signal which is the output of the synchronization circuit 104,
Control for calculating the S2 correction gain for each color filter so that the ratio of the S2 ′ signal output from the multiplier 105 for each color filter becomes n: m, and setting the S2 correction gain for each color filter in the gain register 901 Means.

The gain register 901 indicated by the broken line indicates that M
This register holds the S2 correction gain for Y, GC, GY, and MC. The selector 902 controls the output timing of the S2 correction gain for each color filter, and
5 is given. The multiplier 105 is used for the synchronization circuit 10
4 is multiplied by the S2 correction gain output from the selector 902 to the S2 signal output from
This is a circuit provided to the signal processing circuit 106 as a 2 ′ signal.

The operation of the imaging apparatus according to Embodiment 3 configured as described above will be described. In FIG. 9, an optical image of a subject formed by an optical system 101 is an image sensor.
(CCD) 102 and photoelectrically converted. For example, an electronic shutter speed of 1 / m second is 1/100
Seconds and 1 / n second electronic shutter speed of 1
When set to / 400 seconds, the image sensor 102 outputs both the S1 signal accumulated at an electronic shutter speed of 1/100 second and the S2 signal accumulated at an electronic shutter speed of 1/400 second within one vertical scanning period. Output. Image sensor 1
When the output signal 02 is supplied to the ASP / A / D converter 103, it is sampled, gain-adjusted, and then subjected to analog / digital conversion. The synchronization circuit 104 is an ASP
-Separate the output signal of the A / D converter 103 into the S1 signal and the S2 signal, and output them at the same timing.

The vertical synchronizing signal VD shown in FIG. 3A is a synchronizing signal having a period of a vertical scanning period, that is, a period of 1/60 seconds. The image sensor 102 is driven in synchronization with the vertical synchronization signal. As shown in FIG. 3B, the charge of the S1 signal is accumulated for a period of 1/100 second in the cycle of the vertical synchronization signal, and the charge of the S2 signal is 1/400 in the period of the vertical synchronization signal
Accumulate for a period of seconds. At the end of accumulation of the S1 signal and the S2 signal, a read pulse as shown in FIG. The S1 signal and the S2 signal are output from the image sensor 102 by these read pulses. A signal including the S1 signal and the S2 signal output from the image sensor 102 is output from the ASP
The signal is input to the synchronization circuit 104 via the A / D converter 103.

The synchronizing circuit 104 shown in FIG. 2 uses a selector 301 to separate an input signal into an S1 signal and an S2 signal. The separated S1 signal and S2 signal are input to a first memory 302 and a second memory 303, respectively. In the first memory 302, the timing A shown in FIG.
Then, writing of the S1 signal is started, and reading is started at timing C shown in FIG. Also, the second memory 303
In, writing of the S2 signal is started at timing B shown in FIG. 3D, and reading is started at timing D shown in FIG. Then, the S1 signal and the S2 signal are output at the same timing.

The operation of flicker correction will be described with reference to FIGS. FIG. 12 shows an image pickup device 102 at the time of illuminating a fluorescent lamp driven at 60 Hz in the image pickup apparatus of the present embodiment.
FIG. 4 is a schematic diagram showing a change in accumulated charge of the first embodiment. FIG. 12 (a)
Indicates a vertical synchronization signal, and its period is 1/60 second.
As shown in FIG. 12 (b), the subject is illuminated using a fluorescent lamp driven at 60 Hz, an image is captured at an electronic shutter speed of 1/100 second, and the signal charge is obtained for every 1/100 second vertical scanning period. Is accumulated, there is a slight difference between the blinking cycle of the fluorescent lamp driven at 60 Hz and the cycle of the vertical synchronizing signal. However, since the accumulation time of the signal charge is long, as shown in FIG. In the vertical scanning period, the accumulated charge of each color filter is substantially the same. In addition, as shown in FIG. 12D, the subject is illuminated using a fluorescent lamp driven at 60 Hz.
When an image is captured at an electronic shutter speed of / 400 seconds and signal charges are accumulated during a period of 1/400 seconds every vertical scanning period, a slight difference between the blinking period of the 60 Hz fluorescent lamp and the period of the vertical synchronization signal is obtained. Occurs. In this case, since the accumulation period is further shortened, the accumulation timing for each vertical scanning period gradually changes as shown in FIG. That is, the amount of accumulated charge for each color filter indicated by the hatched portion fluctuates in a long cycle. This causes color flicker.

The S1 signal output from the synchronization circuit 104 is input to the S1C integration circuit 907 in FIG. 9, and the S2 signal is input to the S2C integration circuit 908. S1C integration circuit 9
07 is the multiplexer circuit 11 shown in FIG.
01 for each color filter. Integration circuit 110
2 to 1105 calculate the integral values ΣMY, ΣGC, ΣGY, and ΣMC for each color filter in one vertical scanning period. These integrated values are selected by the selector circuit 1106, read out in order, and output as $ S1C. S2 in FIG.
The operation of the C integration circuit 908 is the same as that of the S1C integration circuit 907. Integration value output from S1C integration circuit 907 ΣS1
C and the integrated value ΣS2C output from the S2C integration circuit 908
Is input to the microcomputer 909.

The microcomputer 909 first determines whether $ S1C and $ S2
From S, the S2 correction gain is calculated so that the signal level ratio of the S1 signal and the S2 ′ signal for each color filter becomes 400: 100, and the S2 correction gain for each color filter is set in the gain register 901. At this time, since the signal level of the luminance flicker fluctuates in a cycle of three vertical scanning periods, {S1C
And ΣS2C are delayed by three vertical scanning periods from the calculated vertical scanning period, and the S2 correction gain for each color filter is set in the gain register 901. S2 for each set color filter
The correction gain is selected by the selector circuit 902 and output to the multiplier 105 at the same timing. The multiplier 105 multiplies the S2 signal by an S2 correction gain for each color filter. In the signal processing circuit 106, the multiplier 105
Performs signal processing such as contour emphasis on the S2 'signal output from the above, and outputs a video signal Sout.

By controlling in this way, the S1 signal is a signal captured at an electronic shutter speed of 1/100 second, so that there is no luminance flicker or color flicker. The ratio to the S1 signal without flicker is always 400: 1
Since the S2 signal is corrected by multiplying the S2 correction gain by the S2 correction gain for each color filter so as to be 00, the S2 ′ signal photographed at an electronic shutter speed of 1/400 second is a signal that does not include luminance flicker and color flicker. Become.

In this embodiment, the operation has been described in the case where the electronic shutter speed of 1 / m second is set to 1/100 second and the electronic shutter speed of 1 / n second is set to 1/400 second. But the electronic shutter speed is 1
When it is desired to change the value to a value other than / 100 seconds or 1/400 seconds, the microcomputer 109 sends a control signal for changing the electronic shutter speed to the image sensor driving circuit 110 so that the image sensor according to the designated electronic shutter speed is sent. 102 can be driven. To reduce color flicker, it is better to set the electronic shutter speed close to the period of the vertical synchronization signal. Therefore, the electronic shutter speed of 1 / m second needs to be set to a value close to 1/100 second. Even when the electronic shutter speed of 1 / n second is other than 1/400 second, flicker can be reduced by the same operation.

In the above description of the operation, in the imaging means 111 indicated by a broken line, one image sensor 102
1 signal and S2 signal are read out, and
Although the signal and the S2 signal are output at the same timing, the same effect can be obtained by using another image sensor or sensor as long as it outputs the S1 signal without flicker.

In the above description of operation, in the pixel mixture readout of the complementary color filter, Mg + Cy (MC), G +
Ye (GY), G + Cy (GC), Mg + Ye (MY)
The gain of the signal level after pixel mixing is adjusted as described above, but the signal level of the complementary color filter (Mg, Cy, G, Ye) or the primary color filter (R, G, B) is adjusted by adjusting the gain. The same effect can be obtained.

(Embodiment 4) Next, an image pickup apparatus according to Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 13 is a block diagram illustrating a configuration of an imaging device according to the present embodiment. Embodiment 2
The same reference numerals are given to the same parts as in FIGS. 3 and 3, and the detailed description is omitted. In the imaging means 111 of FIG. 13, an image sensor (CCD) 102 photoelectrically converts an optical image of a subject formed by the optical system 101 and outputs a pixel signal. The output of the image sensor 102 is ASP
The signal is supplied to the A / D converter 103. The ASP / A / D converter 103 performs analog / digital conversion on the output signal of the image sensor 102 after sampling and gain adjustment, and outputs the result. The output of the ASP / A / D converter 103 is supplied to the synchronization circuit 104. The synchronizing circuit 104 is a circuit that generates pixel signals having different accumulation timings and accumulation times as the S1 signal and the S2 signal, and outputs the S1 signal and the S2 signal at the same timing.

The gain control means 1312 indicated by a broken line portion includes a block multiplier 505, a gain register 901, a selector 902, an S1 block division and integration circuit 507, an S2 block division and integration circuit 508, and a microcomputer 1309. The S2 signal output from the synchronization circuit 104 is input to the signal processing circuit 106 via the block multiplier 505. The signal processing circuit 106 performs signal processing such as contour enhancement on the S2 'signal output from the block multiplier 505, and outputs a video signal Sout. The S1 signal output from the synchronization circuit 104 is supplied to the S1 block division C integration circuit 507, and the S2 signal is
It is also provided to a two-block divided C integration circuit 508.

The S1 block division C integration circuit 507 calculates
This is a circuit that divides a screen area of one vertical scanning period into a plurality of blocks Bi (i = 01, 02... 48) for each color filter of one signal, and calculates an integrated value BiΣS1C for each block. Similarly, the S2 block division C integration circuit 508 calculates
This is a circuit that divides a screen area of one vertical scanning period into a plurality of blocks Bi (i = 01, 02 ... 48) for each color filter of the S2 signal, and calculates an integrated value BiΣS2C for each block. These integral values Bi @ S1C and Bi @ S2C are input to a microcomputer 1309 as control means.

The microcomputer 1309 has an image pickup device driving circuit 1
10 and output a control signal to BiΣS1C
And BiΣS2C, a control means for calculating the BiS2 correction gain so that the signal level ratio for each color filter of the S1 signal and the S2 'signal is n: m for each block. The gain register 901 indicated by a broken line indicates MY, GC, G
This is a register for holding the S2 correction gain for Y and MC, respectively. The selector 902 controls the output timing of the S2 correction gain for each color filter to control the output timing of the block multiplier 50.
5 is given. The block multiplier 505 is a circuit that multiplies the S2 signal by a BiS2 correction gain for each color filter and each block, and provides the multiplication result to the signal processing circuit 106 as an S2 ′ signal.

The operation of the imaging apparatus according to Embodiment 4 configured as described above will be described. In FIG.
An optical image of a subject formed by the optical system 101 is incident on an image sensor (CCD) 102 and is photoelectrically converted. For example, an electronic shutter speed of 1 / m second is 1/100
Seconds and 1 / n second electronic shutter speed of 1
When set to / 400 seconds, the image sensor 102 outputs an S1 signal accumulated at an electronic shutter speed of 1/100 second and an S2 signal accumulated at an electronic shutter speed of 1/400 second within one vertical scanning period. Is done. Image sensor 10
The output of 2 is supplied to an ASP / A / D converter 103, and after sampling and gain adjustment, is subjected to analog / digital conversion. The output of the ASP / A / D converter 103 is supplied to the synchronization circuit 104. The synchronizing circuit 104 separates the input signal into the S1 signal and the S2 signal, and outputs them at the same timing. S2 output from the synchronization circuit 104
The signal passes through a block multiplier 505 to the signal processing circuit 10.
6 is input. The signal processing circuit 106 performs signal processing such as edge enhancement on the S2 'signal output from the block multiplier 505, and outputs a video signal Sout.

The vertical synchronization signal VD shown in FIG. 3A is a synchronization signal having a period of a vertical scanning period, that is, a period of 1/60 second. The image sensor 102 is driven in synchronization with the vertical synchronizing signal. As shown in FIG. 3B, the charge of the S1 signal is accumulated for 1/100 second in the cycle of the vertical synchronizing signal.
The signal charge is accumulated for a period of 1/400 second in the cycle of the vertical synchronization signal. At the end of the accumulation of the S1 signal and the S2 signal, FIG.
A read pulse as shown in (c) is output. With these read pulses, the S1 signal and the S2 signal are
02 is output. S output from the image sensor 102
The signal including the 1 signal and the S2 signal is an ASP / A / D converter 1
03 and input to the synchronization circuit 104.

The synchronizing circuit 104 shown in FIG. 2 supplies an input signal to the selector 301 to separate it into the S1 signal and the S2 signal. The separated S1 signal and S2 signal are input to a first memory 302 and a second memory 303, respectively. In the first memory 302, the timing A shown in FIG.
Then, writing of the S1 signal is started, and reading is started at timing C shown in FIG. Also, the second memory 30
3, the writing of the S2 signal starts at the timing B shown in FIG. 3D, and the timing D shown in FIG.
To start reading. Then, the S1 signal and the S2 signal are output at the same timing.

The operation of flicker correction will be described with reference to FIGS. FIG. 12 shows a lighting device of 60 Hz.
FIG. 5 is a schematic diagram illustrating a change in accumulated charge of an image sensor during illumination of a driven fluorescent lamp. FIG. 12A shows a vertical synchronization signal whose cycle is 1/60 second. As shown in FIG. 12B, the subject is illuminated using a fluorescent lamp driven at 60 Hz, an image is taken at an electronic shutter speed of 1/100 second, and
When signal charges are accumulated for 1/100 second every vertical scanning period, a slight difference occurs between the blinking cycle of the 60 Hz fluorescent lamp and the cycle of the vertical synchronizing signal. As shown in FIG. 12 (c), the accumulated charge for each color filter is substantially the same during any vertical scanning period. Further, as shown in FIG. 12D, the subject is illuminated using a fluorescent lamp driven at 60 Hz, an image is taken at an electronic shutter speed of 1/400 second, and the image is taken at a period of 1/400 second every vertical scanning period. When signal charges are accumulated, a slight difference occurs between the blinking cycle of the 60 Hz fluorescent lamp and the cycle of the vertical synchronization signal. In this case, the accumulation period is further shortened.
As shown in (e), the accumulation timing for each vertical scanning period gradually changes. That is, the amount of accumulated charge for each color filter indicated by the hatched portion fluctuates in a long cycle. This causes color flicker.

The S1 signal output from the synchronization circuit 104 in FIG. 13 is supplied to an S1 block division C integration circuit 507, and the S2 signal is supplied to an S2 block division C integration circuit 508. The S1 block division C integration circuit 507 divides the screen area in one vertical scanning period of the S1 signal into a plurality of blocks shown in FIG. 6, and calculates an integral value BiΣS1C of each block for each color filter. Similarly, the S2 block division C integration circuit 508 divides the screen area of one vertical scanning period in the S2 signal into a plurality of blocks, and calculates an integrated value BiＢS2C of each block for each color filter. These integral values Bi @ S1C and Bi @ S2C are input to the microcomputer 1309.

The microcomputer 1309 determines that BiΣS1C and BiΣ
From S2C, the S2 correction gain is calculated such that the ratio of the signal level of the S1 signal to the signal level of the S2 'signal for each color filter becomes 400: 100. At this time, the signal level of the luminance flicker fluctuates in a cycle of three vertical scanning periods, so that three vertical scanning periods are delayed from the vertical scanning period in which BiΣS1C and BiΣS2C are calculated, and the S2 correction gain is set in the gain register 901 for each color filter. I do. The set S2 correction gain for each color filter is selected by the selector circuit 902 and output to the block multiplier 505 at the same timing. In the block multiplier 505, S2
The signal is multiplied by an S2 correction gain. The multiplication result of the block multiplier 505 is converted to an S2 ′ signal by the signal processing circuit 1
06. The signal processing circuit 106 performs signal processing such as edge enhancement on the S2 ′ signal,
Output out.

By controlling in this manner, the S1 signal is a signal captured at an electronic shutter speed of 1/100 second, so that no flicker occurs. Since the S2 signal for each block is multiplied by the S2 correction gain for each color filter so that the ratio to the flicker-free S1 signal is always 400: 100, the luminance flicker and the color flicker included in the S2 signal are reduced. can do. At this time, even when a part of the subject is flickering as shown in FIG. 6, flicker correction is performed so that the ratio of the S1 signal to the S2 signal is 400: 100 for each block.
It is possible to correct only a flicker portion without overcorrecting a portion having no flicker.

In the above description of the operation, the electronic shutter speed of 1 / m second is set to 1/100 second,
Although the electronic shutter speed of n seconds was set to 1/400 second, the electronic shutter speed was set to 1/100 or 1/4.
When it is desired to change the value to a value other than 00 seconds, the microcomputer 109 sends a control signal for changing the electronic shutter speed to the image sensor driving circuit 110, and can drive the image sensor 102 according to the specified electronic shutter speed. To reduce the color flicker, it is better to set the electronic shutter speed close to the cycle of the vertical synchronization signal. Therefore, the electronic shutter speed of 1 / m second needs to be set to a value close to 1/100 second. However, even when the electronic shutter speed of 1 / n second is other than 1/400 second, flicker can be reduced to the same operation.

In the above description of the operation, the screen is divided into eight horizontal divisions and six vertical divisions in one vertical scanning period. However, if the partial flicker area coincides with the divided block, eight horizontal divisions and six vertical divisions are performed. Even in block division other than division,
Partial flicker can be reduced.

In the above description of the operation, the S1 signal and the S2 signal are read from one image sensor 102, and the S1 signal and the S2 signal are output at the same timing by the synchronization circuit 104. However, there is no flicker. The same effect can be obtained by using another image sensor or sensor as long as it outputs the S1 signal.

In the above description of the operation, in the pixel mixture readout, Mg + Cy (MC) and G + Ye (G
Y), G + Cy (GC), and Mg + Ye (MY) are used to adjust the gain of the signal level after pixel mixing. However, the complementary color filters (Mg, Cy, G, Ye) and the neat primary color filters (R, The same effect can be obtained by adjusting the gain of the signal level as it is in G, B).

[0088]

When a subject is illuminated by an illuminating device having a frequency different from the frequency of the vertical synchronizing signal, a flicker occurs in a video signal output from the imaging means. According to the imaging device of the first aspect of the present invention, by capturing an image at an electronic shutter speed synchronized with a blinking cycle of the illumination device, an S1 signal with reduced flicker is generated, and the image is captured at a desired electronic shutter speed. By correcting the S2 signal so that the level ratio with the S1 signal is constant, the S2 ′ signal with reduced flicker can be generated.

According to the image pickup apparatus of the second aspect of the present invention, the S1 signal has an electronic shutter speed of 1 / m second,
For example, flicker can be reduced by imaging at an electronic shutter speed of 1/100 second, and the ratio of the S1 signal to the S2 'signal imaged at an electronic shutter speed of 1 / n second is n: m.
By multiplying the S2 signal by the S2 correction gain so as to obtain the S2 ′ signal, a flicker-free S2 ′ signal can be obtained. Therefore, even when photographing is performed at an arbitrary electronic shutter speed, a video signal with reduced flicker can be obtained.

According to the imaging apparatus of the present invention, the imaging screen is divided into a plurality of blocks, and the S1 signal for each block is an electronic shutter speed of 1 / m second, for example, an electronic shutter speed of 1/100 second. By imaging at the shutter speed, flicker can be reduced, and the S2 correction gain is applied to the S2 signal so that the ratio of the S1 signal to the S2 ′ signal imaged at an electronic shutter speed of 1 / n second becomes n: m. By multiplying each time, an S2 'signal without flicker can be obtained. Therefore, even when photographing is performed at an arbitrary electronic shutter speed, a video signal with reduced flicker can be obtained. This is particularly effective when flicker occurs in a specific block.

According to the image pickup apparatus of the present invention, flicker is reduced by taking an image at an electronic shutter speed of 1 / m second, for example, 1/100 second, as the S1 signal for each color filter. By multiplying the S2 signal by an S2 correction gain for each color filter so that the ratio of the S1 signal to the S2 'signal captured at an electronic shutter speed of 1 / n second is n: m, there is no flicker. An S2 'signal can be obtained. Therefore, even when photographing at an arbitrary electronic shutter speed, an image with reduced flicker can be obtained. This is particularly effective when flicker occurs in a specific color.

According to the imaging device of the fifth aspect of the present invention, the effects of both the imaging device of the third aspect and the imaging device of the fourth aspect can be obtained.

According to the imaging device of the present invention, even if the blinking period of the illumination device for illuminating the subject is different from the vertical scanning period of the imaging means, the electronic shutter speed is set equal to the blinking period of the illumination device. By doing so, flicker can be eliminated.

According to the imaging device of the present invention, flicker can be eliminated when the illumination device is driven at 50 Hz.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an imaging device according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a synchronization circuit in the imaging device according to each embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of an image sensor and a synchronization circuit in the image pickup apparatus according to each embodiment of the present invention.

FIG. 4 is a schematic diagram showing a change in accumulated charge of an image sensor at the time of illumination of a fluorescent lamp driven at 50 Hz in the image capturing apparatus according to Embodiments 1 and 2 of the present invention.

FIG. 5 is a block diagram illustrating an overall configuration of an imaging device according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram showing block division of a screen area in a vertical scanning period in the imaging device according to the second embodiment.

FIG. 7 is a block diagram showing a configuration of a block division and integration circuit in an imaging device according to Embodiments 2 and 4 of the present invention.

FIG. 8 is a block diagram showing a configuration of a block multiplier in an imaging device according to Embodiments 2 and 4 of the present invention.

FIG. 9 is a block diagram illustrating an overall configuration of an imaging device according to Embodiment 3 of the present invention.

FIG. 10 is a schematic diagram showing a color filter of an image sensor and a read operation in the image pickup device according to Embodiments 3 and 4 of the present invention.

FIG. 11 is a block diagram showing a configuration of an SnC integration circuit in an imaging device according to Embodiments 3 and 4 of the present invention.

FIG. 12 is a schematic diagram illustrating a change in accumulated charge for each color filter of an image sensor when illuminating a fluorescent lamp driven at 60 Hz in the image capturing apparatus according to Embodiments 3 and 4 of the present invention.

FIG. 13 is a block diagram illustrating an overall configuration of an imaging device according to a fourth embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration example of a conventional imaging device.

[Explanation of symbols]

Reference Signs List 101 optical system 102 imaging device 103 ASP / A / D converter 104 synchronization circuit 105,805 multiplier 106 signal processing circuit 107 S1 integration circuit 108 S2 integration circuit 109, 509, 909, 1309 microcomputer 110 imaging device driving circuit 111 imaging Means 112, 512, 912, 1312 Gain control means 301, 705, 804, 902, 1106 Selector 302 First memory 303 Second memory 507 S1 block division C integration circuit 508 S2 block division C integration circuit 505 Block multiplier 700 Block division and integration circuit 701, 1101 Multiplexers 702, 703, 704, 1102, 1103, 110
4,1105 Integrating circuits 801,802,803 Block gain register 901 Gain register 907 S1C integrating circuit 908 S2C integrating circuit 1100 SnC integrating circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masayuki Yoneyama 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5C021 PA17 PA42 PA52 PA67 YA07 5C022 AB15 AB17 AB20 AB51 AC42 AC69

Claims (7)

[Claims] An imaging means for outputting an S1 signal imaged at an electronic shutter speed of 1 / m second and an S2 signal imaged at an electronic shutter speed of 1 / n second within one vertical scanning period; The S2 correction gain is calculated so that the ratio of the S2 signal to the S2 'signal obtained by correcting the S2 signal with the S2 correction gain is n: m, and the S2 signal is multiplied by the S2 correction gain, and flicker is suppressed in the multiplication result. And a gain control means for outputting the signal as the S2 ′ signal. 2. An image pickup means for outputting an S1 signal picked up at an electronic shutter speed of 1 / m second and an S2 signal picked up at an electronic shutter speed of 1 / n second within one vertical scanning period; An S1 integration circuit for calculating an integration value ΣS1 of one vertical scanning period; an S2 integration circuit for calculating an integration value ΣS2 of the S2 signal for one vertical scanning period; and an S1 signal using data of the ΣS1 and the ΣS2. Control means for calculating the S2 correction gain so that the ratio of the S2 signal and the S2 'signal obtained by correcting the S2 signal with the S2 correction gain is n: m, and outputting the S2 correction gain after a predetermined time delay; An image pickup apparatus comprising: a multiplier for multiplying an S2 signal by an S2 correction gain generated by the control unit, and outputting a multiplication result as the S2 ′ signal with flicker suppressed. 3. An imaging means for outputting an S1 signal imaged at an electronic shutter speed of 1 / m second and an S2 signal imaged at an electronic shutter speed of 1 / n second within one vertical scanning period, and one vertical scanning period Is divided into a plurality of blocks Bi (i is a block number), the S1 signal of each block is integrated, and an S1 block division and integration circuit for calculating an integrated value BiΣS1 is provided. S2 for integrating the S2 signal for each block Bi to calculate an integrated value BiΣS2
Using the block division and integration circuit and the data of BiΣS1 and BiΣS2, the S1 signal and the S2 signal are Bi in each block Bi.
The ratio with the BiS2 'signal corrected by the S2 correction gain is n:
control means for calculating the BiS2 correction gain for each of the blocks Bi so as to obtain m, and outputting the BiS2 correction gain with a delay of a predetermined time; and wherein the control means generates the S2 signal for each of the blocks Bi And a block multiplier that multiplies the obtained BiS2 correction gain and outputs the multiplication result as the S2 ′ signal in which flicker is suppressed. 4. An image pickup means for outputting an S1 signal picked up at an electronic shutter speed of 1 / m second and an S2 signal picked up at an electronic shutter speed of 1 / n second within one vertical scanning period; Integral value of the S1 signal during one vertical scanning period ΔS
And an S1C integration circuit for calculating 1, and an integration value ΣS of the S2 signal for one vertical scanning period for each color signal.
The ratio of the S1 signal and the S2 'signal obtained by correcting the S2 signal with the S2 correction gain using the data of the ΣS1 and the ΣS2 is n: m for each color signal. Control means for calculating the S2 correction gain and delaying the S2 correction gain by a predetermined time for each color signal; and controlling the S2 correction gain generated by the control means for the S2 signal for each color signal. A multiplier that multiplies and outputs a result of the multiplication as the S2 ′ signal in which flicker is suppressed. 5. An image pickup means for outputting an S1 signal picked up at an electronic shutter speed of 1 / m second and an S2 signal picked up at an electronic shutter speed of 1 / n second within one vertical scanning period; , The screen area of one vertical scanning period of the S1 signal is divided into a plurality of blocks Bi (i is a block number),
The S1 signal for each block is integrated, and the integrated value BiΣS
An S1 block division C integration circuit for calculating 1C, and an S2 block for integrating, for each color signal, the S2 signal of each block Bi in the screen area of one vertical scanning period of the S2 signal to calculate an integrated value BiΣS2C. Using the divided C integrator circuit and the data of BiΣS1C and BiΣS2C, the ratio of the S1 signal and the S2 ′ signal obtained by correcting the S2 signal with the BiS2 correction gain is determined for each color signal and for block B.
control means for calculating the BiS2 correction gain for each block and color signal so that n: m for each i, and outputting the BiS2 correction gain with a predetermined time delay; An imaging apparatus, comprising: a block multiplier that multiplies a signal by a BiS2 correction gain generated by the control unit and outputs a result of the multiplication as the S2 ′ signal in which flicker is suppressed. 6. The electronic shutter speed of 1 / msec is made equal to the blinking cycle of the lighting device when the blinking period of the lighting device for illuminating the subject is different from the vertical scanning period of the imaging means. Item 6. The imaging device according to any one of Items 1 to 5. 7. The electronic shutter speed of 1 / m second is reduced to 1/100 second when a blinking period of an illuminating device for illuminating a subject is different from a vertical scanning period of the imaging unit. 6. The imaging device according to claim 5.