JP2001057282A - Surface mounting-type surge absorbing element and manufacture of the same - Google Patents

Surface mounting-type surge absorbing element and manufacture of the same

Info

Publication number
JP2001057282A
JP2001057282A JP11232289A JP23228999A JP2001057282A JP 2001057282 A JP2001057282 A JP 2001057282A JP 11232289 A JP11232289 A JP 11232289A JP 23228999 A JP23228999 A JP 23228999A JP 2001057282 A JP2001057282 A JP 2001057282A
Authority
JP
Japan
Prior art keywords
internal electrode
absorbing element
surge absorbing
electrode layers
type surge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11232289A
Other languages
Japanese (ja)
Inventor
Hideki Matsuzawa
秀樹 松沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP11232289A priority Critical patent/JP2001057282A/en
Publication of JP2001057282A publication Critical patent/JP2001057282A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To manufacture a surface mounting-type surge absorbing element having small electrostatic capacity without requiring complex processes by forming internal electrode layers respectively conducted to external electrodes at both ends with difference in level, inside of an insulating ceramic layer, forming a discharging space as a cavity part in a part between the internal electrode layers, and forming the inside of the discharging space into a hollowed gourd shape. SOLUTION: A pair of internal electrode layers 3 conducted to external electrodes at both ends with difference in level, are formed inside of an insulating ceramic layer 2 having a pair of external electrodes 1 at both ends, a discharging space 4 is partially formed between the internal electrode layers 3, the inside of the discharging space 4 has the shape of a hollowed gourd, and an insulating layer between the internal electrode layers 3 has at least a multilayer structure of at least three layers. By applying this constitution, the discharging is generated by the dielectric breakdown generated in the atmosphere in the discharging space when the excess voltage is applied between the internal electrodes, and the surge voltage is absorbed thereby.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、主として電子回路
や電子部品をサージから保護するためのサージ吸収素子
及びその製造方法に関し、特に、プリント基板への自動
実装に有利な表面実装型のサージ吸収素子及びその製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge absorbing element for protecting electronic circuits and electronic components from surges and a method of manufacturing the same, and more particularly to a surface mount type surge absorbing element which is advantageous for automatic mounting on a printed circuit board. The present invention relates to an element and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、通信機器等をサージから保護する
サージ吸収素子として、電圧非直線特性を有する高抵抗
体素子よりなるバリスタや放電空間を気密容器内に封入
した放電式サージ吸収素子等が広く利用されている。
2. Description of the Related Art Conventionally, as a surge absorbing element for protecting a communication device from a surge, a varistor composed of a high-resistance element having a voltage non-linear characteristic and a discharge type surge absorbing element in which a discharge space is sealed in an airtight container are known. Widely used.

【0003】従来のバリスタは、サージ吸収の応答性に
優れるとともに、素子の小型化や表面実装部品に対応し
た構造とすることが容易であるという利点を有している
一方で、静電容量が大きく、信号系回路に使用しにくい
という欠点を有する。
[0003] The conventional varistor has an advantage that it has excellent responsiveness of surge absorption and that it is easy to reduce the size of an element and to adopt a structure corresponding to a surface mount component, but it has an advantage that the capacitance is low. It has the disadvantage of being large and difficult to use in signal-related circuits.

【0004】また、従来の放電式サージ吸収素子は、静
電容量が小さいため、信号系回路にも広く利用されてい
る。しかし、その構造は、マイクロギャップを気密構造
とするため、ガラス封入してリード線を引き出すもの
で、プリント基板への実装にあたっては、リード線の適
切な長さへの切断、曲げ加工が必要となる。また、その
後にプリント基板の穴にリード線を挿入し、半田付けす
るものであった。このようなプリント基板への放電式サ
ージ吸収素子の実装は、工数のかかる方法であり、多く
の電子部品が表面実装型の電子部品へと移り変わってき
ている。
[0004] Further, the conventional discharge-type surge absorbing element is widely used in signal-related circuits because of its small capacitance. However, in order to make the micro gap an airtight structure, the lead wire is drawn out by encapsulating glass.When mounting on a printed circuit board, it is necessary to cut and bend the lead wire to an appropriate length. Become. Thereafter, a lead wire is inserted into a hole in the printed circuit board and soldered. Mounting the discharge type surge absorbing element on such a printed circuit board is a time-consuming method, and many electronic components have been switched to surface-mounted electronic components.

【0005】[0005]

【発明が解決しようとする課題】しかし、上述した従来
の表面実装型のサージ吸収素子は、次のような欠点があ
る。即ち、マイクロギャップを気密に保つために、真空
排気しキャップを封着する工程、あるいは、キャップと
マイクロギャップが短絡しないようマイクロギャップに
絶縁被膜を形成する工程等、工数がかかり生産性があが
らないという問題があった。
However, the above-mentioned conventional surface mount type surge absorbing element has the following disadvantages. In other words, in order to keep the micro gap airtight, evacuation and sealing of the cap, or a step of forming an insulating film on the micro gap so that the cap and the micro gap are not short-circuited, the number of steps is increased and productivity is not reduced. There was a problem.

【0006】従って、本発明は、かかる課題を解決すべ
くなされたもので、静電容量が小さく、複雑な製造工程
を必要としない、表面実装型サージ吸収素子及びその製
造方法を提供することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a surface mount type surge absorbing element having a small capacitance and requiring no complicated manufacturing steps, and a method of manufacturing the same. is there.

【0007】[0007]

【課題を解決するための手段】本発明は、両端に一対の
外部電極を有する絶縁性セラミック層の内部に、両端の
外部電極と各々段違いになるように導通した内部電極層
を有し、さらに、該内部電極層間の一部分には空洞部か
らなる放電空間を有し、該放電空間の内部がくぼんだ形
状から構成されている表面実装型サージ吸収素子であ
る。
According to the present invention, there is provided an insulating ceramic layer having a pair of external electrodes at both ends, and an internal electrode layer electrically connected to the external electrodes at both ends so as to be stepped, respectively, inside the insulating ceramic layer. The surface-mounted surge absorbing element has a discharge space formed of a cavity in a part between the internal electrode layers, and the inside of the discharge space has a concave shape.

【0008】また、本発明は、上記表面実装型サージ吸
収素子において、内部電極層間の絶縁層が3層以上の多
層構造を有している表面実装型サージ吸収素子である。
Further, the present invention is the above-mentioned surface-mounted surge absorbing element, wherein the insulating layer between the internal electrode layers has a multilayer structure of three or more layers.

【0009】かかる構成により、内部電極間に過度の電
圧が印加されると、放電空間内の雰囲気が絶縁破壊を起
こし放電を生じることにより、サージ電圧を吸収させる
ことができる。
With this configuration, when an excessive voltage is applied between the internal electrodes, the atmosphere in the discharge space causes dielectric breakdown and discharge occurs, so that the surge voltage can be absorbed.

【0010】また、絶縁層の放電空間内部にくぼみをつ
けない場合、絶縁層表面に沿って沿面放電しやすく、電
極材が絶縁層表面にスパッタされることにより、短絡が
生じることがあるが、本発明における絶縁層の構造にお
いては、そのような短絡がおきにくく、繰り返し放電に
対する耐久性が改善することができる。また、放電開始
電圧は、内部電極間のギャップ長により調整することが
可能である。本発明によるサージ吸収素子の静電容量
は、内部電極の対抗部分の面積によって決まるので、用
途に応じて静電容量を小さくすることが可能である。
[0010] In addition, when no depression is formed inside the discharge space of the insulating layer, creeping discharge is likely to occur along the surface of the insulating layer, and the electrode material is sputtered on the surface of the insulating layer. In the structure of the insulating layer according to the present invention, such a short circuit does not easily occur, and the durability against repeated discharge can be improved. Further, the discharge starting voltage can be adjusted by the gap length between the internal electrodes. Since the capacitance of the surge absorbing element according to the present invention is determined by the area of the opposing portion of the internal electrode, it is possible to reduce the capacitance according to the application.

【0011】また、本発明は、上記表面実装型サージ吸
収素子において、絶縁性セラミック層は印刷法またはグ
リーンシート法により形成され、内部電極層は印刷法に
より形成され、及び放電空間はせん断加工によって形成
され、各々のシートを熱圧着後、一体焼結してなる表面
実装型サージ吸収素子の製造方法である。
Further, the present invention provides the above surface mount type surge absorbing element, wherein the insulating ceramic layer is formed by a printing method or a green sheet method, the internal electrode layer is formed by a printing method, and the discharge space is formed by shearing. This is a method for manufacturing a surface-mounted surge absorbing element formed, and each sheet is thermocompressed and then integrally sintered.

【0012】このような製造方法は、量産性に優れ、外
形寸法、電極面積および間隔、積層数は所望の電気特性
に合わせて適時選択できる。絶縁性セラミック層として
は、アルミナ、ムライト、ステアタイト、フォルステア
タイト、コーディエライト、ガラス、チタニア、ジルコ
ニアなど固有体積抵抗率の高いセラミック材料を単独あ
るいは組み合わせて使用することができ、目的に応じて
選択すればよい。
Such a manufacturing method is excellent in mass productivity, and the external dimensions, the electrode area and the interval, and the number of layers can be appropriately selected according to the desired electric characteristics. As the insulating ceramic layer, ceramic materials having a high specific volume resistivity such as alumina, mullite, steatite, forsteatite, cordierite, glass, titania, and zirconia can be used alone or in combination. You can select it.

【0013】また、内部電極層には、銅、銀、アルミニ
ウム、ニッケルなどの低抵抗金属、ステンレス、コパー
ルなどの合金材料、及び炭素など、導電性に優れた材料
を使用することができる。また、SnO,Nb
,MoO、WO、TiC、SiC、ZrC、
WC、HfC、VC,TiN,TaN,VN、ZrN,
NbN等の酸化物、炭化物、及び窒化物などの導電性セ
ラミック材料なども使用することができる。これらの導
電性セラミックスを使用すると、気体放電時の溶融や酸
化による電極の劣化を抑制できる。これらの電極材料
は、金属系、セラミックス系をそれぞれ単独で使用して
もよいが、それぞれを組み合わせて使用することもでき
る。
For the internal electrode layer, a material having excellent conductivity such as a low resistance metal such as copper, silver, aluminum and nickel, an alloy material such as stainless steel and copearl, and carbon can be used. In addition, SnO 2 , Nb
2 O 5 , MoO 3 , WO 3 , TiC, SiC, ZrC,
WC, HfC, VC, TiN, TaN, VN, ZrN,
Conductive ceramic materials such as oxides such as NbN, carbides, and nitrides can also be used. When these conductive ceramics are used, deterioration of the electrodes due to melting and oxidation during gas discharge can be suppressed. These electrode materials may be used alone or in combination of a metal material and a ceramic material, or may be used in combination.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0015】図1は、本発明の第1の実施の形態による
表面実装型サージ吸収素子の断面図である。図1(a)
及び図1(a)のA−A断面を図1(b)に示すよう
に、本発明におけるサ−ジ吸収素子は、両端に一対の外
部電極1を有する絶縁性セラミック層2内部に、両端の
外部電極1と各々段違いになるように導通した一対の内
部電極層3を有し、さらに、内部電極層3間の一部分が
放電空間4からなり、放電空間4の内部が、くぼんだ杵
形状を有し、かつ、内部電極層3間の絶縁層が3層以上
の多層構造から構成されている。
FIG. 1 is a sectional view of a surface mount type surge absorbing element according to a first embodiment of the present invention. FIG. 1 (a)
As shown in FIG. 1B, a cross section taken along the line AA in FIG. 1A, the surge absorbing element according to the present invention has two ends inside an insulating ceramic layer 2 having a pair of external electrodes 1 at both ends. Has a pair of internal electrode layers 3 electrically connected to each other so as to be different from each other, and a portion between the internal electrode layers 3 is formed of a discharge space 4, and the inside of the discharge space 4 has a concave punch shape. And the insulating layer between the internal electrode layers 3 has a multilayer structure of three or more layers.

【0016】また、図1(c)、図1(d)に示すよう
に、内部電極層3間の絶縁層部分を3層以上の多層で構
成し、絶縁層のうち、内部電極層3に接していない層の
放電空間部径5を、内部電極層3に接している層の放電
空間部径6よりも小さくし、内部電極層3に接していな
い層を少なくとも1層以上で構成することにより、放電
空間4は、内部がくぼんだ杵形状を有するものとなる。
As shown in FIGS. 1 (c) and 1 (d), the insulating layer between the internal electrode layers 3 is composed of three or more layers. The discharge space portion diameter 5 of the layer not in contact with the internal electrode layer 3 is made smaller than the discharge space portion diameter 6 of the layer in contact with the internal electrode layer 3, and the layer not in contact with the internal electrode layer 3 is composed of at least one layer. As a result, the discharge space 4 has a punch shape in which the inside is depressed.

【0017】図2は、本発明の第2の実施の形態による
表面実装型サージ吸収素子の製造方法の説明図である。
FIG. 2 is an explanatory diagram of a method of manufacturing a surface mount type surge absorbing element according to a second embodiment of the present invention.

【0018】まず、平均粒径約3μmのステアタイト粉
末とホウ珪酸ガラス粉末を表1に示す比率でバインダ、
溶剤と混合し、ビーズミルを用いて絶縁層用ペーストを
作製した。
First, a binder comprising a steatite powder having an average particle size of about 3 μm and a borosilicate glass powder in a ratio shown in Table 1 was prepared.
After mixing with a solvent, a paste for an insulating layer was prepared using a bead mill.

【0019】[0019]

【表1】 [Table 1]

【0020】次に、平均粒径約0.3μmの70重量部
銀−30重量部パラジウム合金粉末を表2に示す比率で
バインダ、溶剤と混合し、ビーズミルをかけて内部電極
層用ペーストを作製した。
Next, 70 parts by weight of silver-30 parts by weight of palladium alloy powder having an average particle diameter of about 0.3 μm are mixed with a binder and a solvent in the ratio shown in Table 2, and the mixture is mixed with a bead mill to prepare a paste for an internal electrode layer. did.

【0021】[0021]

【表2】 [Table 2]

【0022】これらを、図2(a)に示すように、絶縁
性セラミック層2を基板8上にスクリーン印刷した後、
図2(a)及び図2(b)に示すように、打抜き加工で
放電空間4を設けた絶縁性セラミックのシートを作製し
た。なお、図2(b)の放電空間径6は700μm、放
電空間の内径5は300μmとした。
As shown in FIG. 2A, these are screen-printed on the substrate 8 with the insulating ceramic layer 2,
As shown in FIGS. 2A and 2B, an insulating ceramic sheet provided with the discharge space 4 was formed by punching. In FIG. 2B, the discharge space diameter 6 was 700 μm, and the inner diameter 5 of the discharge space was 300 μm.

【0023】これらのシートを重ねて、図2(d)に示
すような積層体を作製した後、110℃で熱圧着した。
このようにして、ギャップ長7を変化させた試料No.
1から3について、大気中で1000℃、5時間、一体
焼結した。
After laminating these sheets to form a laminate as shown in FIG. 2D, the laminate was thermocompression-bonded at 110.degree.
Thus, the sample No.
Samples 1 to 3 were integrally sintered in the atmosphere at 1000 ° C. for 5 hours.

【0024】最後に、外部電極としてガラス含有銀ペー
ストを塗布し、600℃で30分焼結し、表面実装可能
なサージ吸収素子を得た。
Finally, a silver paste containing glass was applied as an external electrode, and sintered at 600 ° C. for 30 minutes to obtain a surge absorbing element capable of surface mounting.

【0025】これらのサージ吸収素子に対して、500
pF−500Ω−10kVの静電気を繰り返し与え、放
電開始電圧及びそのばらつきを調べた。また、繰り返し
放電において、放電開始電圧のばらつきが基準の放電開
始電圧の±30%以上になるところをサイクル寿命とし
た。その結果を表3に示す。
For these surge absorbing elements, 500
Static electricity of pF-500Ω-10 kV was repeatedly applied, and the discharge starting voltage and its variation were examined. In addition, in the repeated discharge, a point where the variation of the discharge start voltage becomes ± 30% or more of the reference discharge start voltage is defined as the cycle life. Table 3 shows the results.

【0026】[0026]

【表3】 [Table 3]

【0027】いずれの素子も繰り返し放電2000回に
おいて、放電開始電圧のばらつきは±22%以内であっ
た。また、絶縁抵抗は1010Ω以上であり、静電容量
は0.7pF以下であった。
In each of the devices, the variation of the firing voltage was within ± 22% after 2,000 repeated discharges. The insulation resistance was 10 10 Ω or more, and the capacitance was 0.7 pF or less.

【0028】以上の結果より、内部電極のギャップ長、
放電空間の雰囲気を制御することにより、所望の放電開
始電圧を有し、静電容量の小さい表面実装型サージ吸収
素子を得ることが可能となった。
From the above results, the gap length of the internal electrode,
By controlling the atmosphere in the discharge space, it has become possible to obtain a surface mount type surge absorbing element having a desired discharge starting voltage and a small capacitance.

【0029】また、従来使用されているサージ吸収素子
と本発明を比較して、表4に示した。
Table 4 shows a comparison between the conventionally used surge absorbing element and the present invention.

【0030】[0030]

【表4】 [Table 4]

【0031】表4より、本発明による表面実装型サージ
吸収素子は、従来の放電型サージ吸収素子と同レベルの
低い静電容量であり、しかも、表面実装が容易な構造を
有するという特徴を備えたものであることがわかる。
From Table 4, it can be seen that the surface-mount type surge absorbing element according to the present invention has the same low capacitance as that of the conventional discharge-type surge absorbing element, and has a structure that allows easy surface mounting. It turns out that it is a thing.

【0032】なお、本発明品は、上記実施の形態に限定
されるものではなく、絶縁性材料、電極材料として、ほ
かの絶縁性セラミック材料や導電性材料を使用できるこ
とは、当該業者であれば容易に類推できることである。
同様に、印刷用ペーストの作製方法として、ほかの手法
を適用することや、印刷積層厚さ、電極層の厚さ、各部
寸法などの積層体作製にかかわる条件、また焼結条件な
どは、本発明の実施例以外の条件でもよいことは、当該
業者であれば容易に類推できることである。
It should be noted that the product of the present invention is not limited to the above-described embodiment, and that other insulating ceramic materials or conductive materials can be used as the insulating material and the electrode material. It can be easily analogized.
Similarly, the conditions for producing the paste for printing, applying other methods, and the conditions for producing the laminate, such as the thickness of the printed laminate, the thickness of the electrode layer, and the dimensions of each part, and the sintering conditions are described in this book. The fact that conditions other than the embodiment of the invention may be used can be easily estimated by those skilled in the art.

【0033】[0033]

【発明の効果】以上説明したごとく、本発明によれば、
従来からあるスクリーン印刷技術等の量産性の高い技術
を利用しているため、製造が容易で、しかも、静電容量
が低くサージ吸収特性の優れた表面実装型サージ吸収素
子を提供できる。
As described above, according to the present invention,
Since a technology with high mass productivity such as a conventional screen printing technology is used, it is possible to provide a surface mount type surge absorbing element which is easy to manufacture, has low capacitance, and has excellent surge absorbing characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態による表面実装型サ
ージ吸収素子の構造を示す断面図。図1(a)は、表面
実装型サージ吸収素子の縦断面図。図1(b)は、図1
(a)で示すA−Aの横断面図。図1(c)は、図1
(a)で示すB−Bの横断面図。図1(d)は、図1
(a)で示すC−Cの横断面図。
FIG. 1 is a sectional view showing a structure of a surface mount type surge absorbing element according to a first embodiment of the present invention. FIG. 1A is a longitudinal sectional view of a surface mount type surge absorbing element. FIG.
FIG. 2 is a cross-sectional view of AA shown in FIG. FIG.
FIG. 3 is a cross-sectional view taken along line BB shown in FIG. FIG.
FIG. 3 is a cross-sectional view taken along the line CC shown in FIG.

【図2】本発明の表面実装型サージ吸収素子の製造方法
の説明図。図2(a)は、絶縁性セラミック層及び内部
電極層の形成方法の説明図。図2(b)は、内部電極に
接している放電空間内部の絶縁性セラミック層の形成方
法の説明図。図2(c)は、内部電極に接していない絶
縁性セラミック層の形成方法の説明図。図2(d)は、
熱圧着後の構成図。
FIG. 2 is an explanatory diagram of a method for manufacturing a surface mount type surge absorbing element of the present invention. FIG. 2A is an explanatory diagram of a method for forming an insulating ceramic layer and an internal electrode layer. FIG. 2B is a diagram illustrating a method of forming an insulating ceramic layer inside a discharge space in contact with an internal electrode. FIG. 2C is an explanatory diagram of a method for forming an insulating ceramic layer that is not in contact with an internal electrode. FIG. 2 (d)
Configuration diagram after thermocompression bonding.

【符号の説明】[Explanation of symbols]

1 外部電極 2 絶縁性セラミック層 3 内部電極層 4 放電空間 5 (内部電極に接していない層の)放電空間部径 6 (内部電極に接している層の)放電空間部径 7 ギャップ長 8 基板 DESCRIPTION OF SYMBOLS 1 External electrode 2 Insulating ceramic layer 3 Internal electrode layer 4 Discharge space 5 Discharge space part diameter (of the layer not in contact with the internal electrode) 6 Discharge space part diameter (of the layer in contact with the internal electrode) 7 Gap length 8 Substrate

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 両端に一対の外部電極を有する絶縁性セ
ラミック層の内部に、両端の外部電極と各々段違いにな
るように導通した内部電極層を有し、さらに、該内部電
極層間の一部分には空洞部からなる放電空間を有し、該
放電空間の内部が、くぼんだ杵形状から構成されている
ことを特徴とする表面実装型サージ吸収素子。
1. An insulating ceramic layer having a pair of external electrodes at both ends has an internal electrode layer electrically connected to the external electrodes at both ends so as to be different from each other, and further includes a part between the internal electrode layers. Is a surface-mount type surge absorbing element, characterized by having a discharge space consisting of a cavity, wherein the inside of the discharge space is formed in a concave punch shape.
【請求項2】 請求項1記載の表面実装型サージ吸収素
子において、前記内部電極層間の絶縁層が3層以上の多
層構造であることを特徴とする表面実装型サージ吸収素
子。
2. The surface mount type surge absorbing element according to claim 1, wherein the insulating layer between the internal electrode layers has a multilayer structure of three or more layers.
【請求項3】 請求項1または2記載の表面実装型サー
ジ吸収素子において、絶縁性セラミック層は印刷法また
はグリーンシート法により形成し、内部電極層は印刷法
により形成し、放電空間はせん断加工によって形成し、
各々のシートを熱圧着後、一体焼結してなることを特徴
とする表面実装型サージ吸収素子の製造方法。
3. The surface-mount type surge absorbing element according to claim 1, wherein the insulating ceramic layer is formed by a printing method or a green sheet method, the internal electrode layer is formed by a printing method, and the discharge space is sheared. Formed by
A method for manufacturing a surface mount type surge absorbing element, wherein each sheet is thermally sintered and integrally sintered.
JP11232289A 1999-08-19 1999-08-19 Surface mounting-type surge absorbing element and manufacture of the same Pending JP2001057282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11232289A JP2001057282A (en) 1999-08-19 1999-08-19 Surface mounting-type surge absorbing element and manufacture of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11232289A JP2001057282A (en) 1999-08-19 1999-08-19 Surface mounting-type surge absorbing element and manufacture of the same

Publications (1)

Publication Number Publication Date
JP2001057282A true JP2001057282A (en) 2001-02-27

Family

ID=16936895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11232289A Pending JP2001057282A (en) 1999-08-19 1999-08-19 Surface mounting-type surge absorbing element and manufacture of the same

Country Status (1)

Country Link
JP (1) JP2001057282A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016039021A1 (en) * 2014-09-10 2016-03-17 株式会社村田製作所 Esd protection device and production method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016039021A1 (en) * 2014-09-10 2016-03-17 株式会社村田製作所 Esd protection device and production method therefor
CN106537701A (en) * 2014-09-10 2017-03-22 株式会社村田制作所 ESD protection device and production method therefor
JPWO2016039021A1 (en) * 2014-09-10 2017-04-27 株式会社村田製作所 ESD protection device and manufacturing method thereof
US10297982B2 (en) 2014-09-10 2019-05-21 Murata Manufacturing Co., Ltd. ESD protective device and method for manufacturing thereof

Similar Documents

Publication Publication Date Title
JP2001043954A (en) Surge absorbing element and manufacture of the same
JP4140173B2 (en) Chip-type surge absorber and manufacturing method thereof
JP2001143846A (en) Surface mounting surge absorber and method of manufacturing the same
JP2000311764A (en) Surge absorbing element, and manufacture thereof
JP2001185322A (en) Surface mounting surge absorbing element and its manufacturing method
JP2001057282A (en) Surface mounting-type surge absorbing element and manufacture of the same
JPH11265808A (en) Surge absorbing element and manufacture of the same
JP3303025B2 (en) Chip type micro gap type surge absorber
TW478229B (en) Chip type surge absorbing device and its manufacturing method
JP2003243249A (en) Laminated ceramic capacitor and its manufacturing method
JP2001267037A (en) Surge absorbing element and manufacturing method therefor
JPH10172346A (en) Terminal electrode for electronic component and laminated ceramic capacitor using the same
JP3286855B2 (en) Manufacturing method of chip type PTC thermistor
JP2001076839A (en) Surface mounting type surge absorbing element and manufacture thereof
JP2000188169A (en) Surge absorbing element
JPH10149945A (en) Multilayered ceramic chip parts and its manufacture
JP2001068247A (en) Surge absorbing element and its manufacture
JP2001143845A (en) Surface mounting surge absorber and method of manufacturing the same
JP2001110544A (en) Surface mount surge absorbing element and manufacturing method
JPH09266053A (en) Chip type surge absorber and its manufacture
JPH09283365A (en) Layered ceramic electronic part and its manufacture
JP3265827B2 (en) Chip type micro gap type surge absorber
JPH11354249A (en) Surge absorbing element
JPH11144835A (en) Surge absorbing element and its manufacture
JP2000077163A (en) Surface mounted surge absorbing element

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees