JP2001044325A - Semiconductor device and semiconductor module - Google Patents
Semiconductor device and semiconductor moduleInfo
- Publication number
- JP2001044325A JP2001044325A JP21632299A JP21632299A JP2001044325A JP 2001044325 A JP2001044325 A JP 2001044325A JP 21632299 A JP21632299 A JP 21632299A JP 21632299 A JP21632299 A JP 21632299A JP 2001044325 A JP2001044325 A JP 2001044325A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- semiconductor
- external electrodes
- semiconductor device
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及び半
導体モジュールに関し、特に複数の半導体装置を並列に
接続してモジュール実装する場合に適用して有効な技術
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a technique effective when a plurality of semiconductor devices are connected in parallel and mounted on a module.
【０００２】[0002]
【従来の技術】ＤＲＡＭに代表される半導体記憶装置
は、コンピュータ等に用いられているが、マルチメディ
アデータ等の大容量データの処理等の必要性から更に大
容量化することが求められている。コンピュータでは、
複数の半導体装置を基板に実装したメモリモジュールと
して用いられており、一定寸法のモジュール基板により
多くの半導体記憶装置を搭載するためには、半導体記憶
装置の小型化が望ましい。また、近年では各種家電製品
にも半導体記憶装置が搭載されており、家電製品の小型
化のためには、半導体記憶装置もより小型化が必要とな
っている。2. Description of the Related Art Semiconductor storage devices such as DRAMs are used in computers and the like. However, the necessity of processing large-capacity data such as multimedia data requires a further increase in capacity. . On the computer,
It is used as a memory module in which a plurality of semiconductor devices are mounted on a substrate. In order to mount more semiconductor storage devices on a module substrate having a fixed size, it is desirable to reduce the size of the semiconductor storage device. In recent years, various types of home appliances have also been equipped with a semiconductor storage device. In order to reduce the size of home appliances, the size of the semiconductor storage device needs to be further reduced.
【０００３】更に、前述したメモリモジュールでは、複
数の半導体記憶装置が基板に実装されたメモリモジュー
ルとして提供されることによって、複数の半導体装置を
一体化してより大容量とし、加えて複数の半導体記憶装
置を搭載することによって、モジュールのデータバス幅
を各半導体記憶装置のメモリのビット幅×搭載数に拡張
することができるので、より高速のデータ転送が可能と
なる。Further, in the above-described memory module, a plurality of semiconductor memory devices are provided as a memory module mounted on a substrate, so that a plurality of semiconductor devices are integrated to have a larger capacity, and a plurality of semiconductor memory devices are additionally provided. By mounting the device, the data bus width of the module can be expanded to the bit width of the memory of each semiconductor storage device x the number of mounted devices, so that higher-speed data transfer becomes possible.
【０００４】半導体装置の小型化では、搭載する半導体
チップサイズと同等乃至わずかに大きなＣＳＰ（Chip S
ize Package）型の封止構造の半導体装置が用いられて
おり、このようなＣＳＰ型の半導体装置では、封止構造
の小型化によって外部電極も小型化及び狭ピッチ化され
ている。こうしたＣＳＰについては、例えば工業調査会
刊行「ＣＳＰ技術のすべて」に記載されている。In order to reduce the size of a semiconductor device, a CSP (chip chip) having a size equal to or slightly larger than the size of a semiconductor chip to be mounted is used.
(CSP) type semiconductor device is used, and in such a CSP type semiconductor device, the external electrodes are also reduced in size and pitch with a reduction in the size of the sealing structure. Such CSP is described in, for example, “All of CSP Technology” published by the Industrial Research Council.
【０００５】こうした半導体装置の小型化、外部電極の
小型化及び狭ピッチ化では、部品としての互換性を保つ
ために、半導体装置の外形寸法及び外部電極の配置につ
いて、ＥＩＡＪ，ＪＥＤＥＣ等のパッケージの外形標準
化機関にて検討されて標準化され、各社の同種半導体装
置はこの規格に従って設計され、外形寸法及び外部電極
の配置が同様の寸法・配置となっている。In such miniaturization of semiconductor devices, miniaturization of external electrodes, and narrowing of pitch, in order to maintain compatibility as components, external dimensions of semiconductor devices and arrangement of external electrodes must be determined by using packages such as EIAJ and JEDEC. It is examined and standardized by an external standardization organization, and the same type of semiconductor device of each company is designed according to this standard, and the external dimensions and the arrangement of the external electrodes have the same dimensions and arrangement.
【０００６】[0006]
【発明が解決しようとする課題】本発明者等は、ＪＥＤ
ＥＣ標準のＣＳＰ型６０ピンのＤＤＲ（Double Data Ra
te）−ＳＤＲＡＭ（Synchronous Dynamic Random Acces
s Memory）半導体装置を複数実装したメモリモジュール
の設計を行なったが、半導体装置の外部電極が狭ピッチ
化されたために、この外部電極と接続するため基板に設
けられる接続電極の間隔も狭くなり、このため基板の実
装面の接続電極間に配線を通すことが困難になってい
る。DISCLOSURE OF THE INVENTION The present inventors have proposed JED
EC standard CSP type 60-pin DDR (Double Data Ra)
te) -SDRAM (Synchronous Dynamic Random Acces)
s Memory) Although a memory module was designed with a plurality of semiconductor devices mounted thereon, the pitch of the external electrodes of the semiconductor device was narrowed, so that the distance between the connection electrodes provided on the substrate for connection with the external electrodes was also reduced. For this reason, it is difficult to pass wiring between the connection electrodes on the mounting surface of the substrate.
【０００７】メモリモジュールでは、夫々の半導体記憶
装置に対して共通に接続されるアドレス信号或いは制御
信号等の各半導体装置に共通する配線（以下、共通配線
という）については並列に接続してモジュールの外部端
子に接続し、データ信号或いは入出力信号等の各半導体
装置に個別の配線（以下、個別配線という）については
夫々個別に外部端子９に接続する。この共通配線に接続
される共通外部電極と、夫々の半導体装置に対して個別
に接続されるデータ信号或いは入出力信号等の個別配線
に接続される個別外部電極とがある。共通配線では複数
の半導体記憶装置を並列に接続してモジュールの外部端
子に接続され、個別配線では夫々の半導体記憶装置から
モジュールの外部端子に夫々接続されている。In a memory module, wires (hereinafter referred to as common wires) common to each semiconductor device such as an address signal or a control signal commonly connected to each semiconductor memory device are connected in parallel to each other. The semiconductor device is connected to external terminals, and individual wirings (hereinafter referred to as individual wirings) for each semiconductor device such as data signals or input / output signals are individually connected to the external terminals 9. There are common external electrodes connected to the common wiring, and individual external electrodes connected to individual wirings for data signals or input / output signals individually connected to the respective semiconductor devices. In the common wiring, a plurality of semiconductor storage devices are connected in parallel and connected to external terminals of the module. In the individual wiring, each semiconductor storage device is connected to external terminals of the module.
【０００８】例えば前記の半導体装置では、図１に示す
ように、半導体装置１の底面に狭ピッチ化され等間隔に
配置された接続電極２の列が４列設けられている。この
ため、この半導体装置を複数並列に接続する基板では、
図２に示すように、基板３の実装面に設けられた半導体
装置搭載領域４に、半導体装置１の外部電極２に対応す
る接続電極５を形成するが、４列に配置された接続電極
５を並列に接続するためには、接続電極５の間に３本の
配線６を通す必要がある。そこで、配線数Ｎが３の場合
の接続電極５と配線６との関係を図３に示す。配線幅Ｌ
ｗ、配線間の間隙Ｌｇから配線領域の幅Ｄは最低でも
０．７ｍｍ程度必要となり、この配線領域の幅Ｄを確保
するためには、接続電極の直径Ｌｄ、接続電極のピッチ
Ｐとすると、Ｐ＝１．２ｍｍ程度が必要となり、前記の
半導体装置を実装した場合には現状では実装面に配線を
通すことができない。For example, in the above-described semiconductor device, as shown in FIG. 1, four rows of connection electrodes 2 having a narrow pitch and arranged at equal intervals are provided on the bottom surface of the semiconductor device 1. For this reason, in a substrate connecting a plurality of the semiconductor devices in parallel,
As shown in FIG. 2, the connection electrodes 5 corresponding to the external electrodes 2 of the semiconductor device 1 are formed in the semiconductor device mounting area 4 provided on the mounting surface of the substrate 3, and the connection electrodes 5 arranged in four rows are formed. , It is necessary to pass three wires 6 between the connection electrodes 5. FIG. 3 shows the relationship between the connection electrode 5 and the wiring 6 when the number N of wirings is three. Wiring width L
w, the width D of the wiring region is required to be at least about 0.7 mm from the gap Lg between the wirings. In order to secure the width D of the wiring region, the diameter Ld of the connection electrode and the pitch P of the connection electrode are as follows: P = about 1.2 mm is required, and when the above-described semiconductor device is mounted, wiring cannot be passed through the mounting surface at present.
【０００９】実装面に配線を形成することができない場
合には、基板内層にこれらの配線を形成する必要があ
り、層数の増加によって基板のコストが上昇する。加え
て、基板内層に配線を形成すると、図４に示すように、
半導体装置搭載領域４の各接続電極５から引き出した信
号配線６をビアホール７を使って内層の配線８（破線図
示）を使って外部端子９と接続する必要があり、このた
め接続信号数×（搭載チップ数＋１）のビアホール７が
必要となる。通常、ビアホール７の部分では基板の全層
にわたって配線が不能となるため、ビアホール７の増加
によって基板配線の自由度が著しく限定され、層数を増
やしても全ての信号を接続できない場合もある。この問
題を回避するためには、ベリードビア或いはブラインド
ビア等の全層にわたらないビアを用いることも考えられ
るが、一般に基板コストが上昇し、信頼性も低下する可
能性がある。If wiring cannot be formed on the mounting surface, it is necessary to form these wirings in the inner layer of the substrate, and the cost of the substrate increases due to the increase in the number of layers. In addition, when wiring is formed in the inner layer of the substrate, as shown in FIG.
It is necessary to connect the signal wiring 6 drawn out from each connection electrode 5 in the semiconductor device mounting area 4 to the external terminal 9 using the wiring 8 (illustrated by a broken line) in the inner layer using the via hole 7. Therefore, the number of connection signals × ( A via hole 7 of the number of mounted chips + 1) is required. Normally, wiring cannot be performed in all the layers of the substrate in the via hole 7 portion. Therefore, the degree of freedom of the substrate wiring is significantly limited by the increase in the number of via holes 7, and even if the number of layers is increased, all signals may not be connected. In order to avoid this problem, it is conceivable to use a via that does not extend over all layers, such as a buried via or a blind via. However, in general, the cost of the substrate increases, and the reliability may decrease.
【００１０】しかしながら、図５に示すように、配線を
通すために半導体装置１の外部電極２の間隔を拡げたの
では、破線図示のようにパッケージの外形寸法を大きく
せざるを得ず、半導体チップサイズに対してパッケージ
サイズが過大となる。この点は、搭載される半導体チッ
プが世代ごとにシュリンク化される点を考慮すると、将
来的には更に大きな問題となる。However, as shown in FIG. 5, if the distance between the external electrodes 2 of the semiconductor device 1 is increased to allow the wiring to pass through, the outer dimensions of the package must be increased as shown by the broken line, and the The package size is too large for the chip size. This point will become a bigger problem in the future, considering that the mounted semiconductor chip is shrunk for each generation.
【００１１】本発明の目的は、パッケージサイズを増大
させずに、実装面への基板配線を可能とする技術を提供
することにある。An object of the present invention is to provide a technique which enables wiring of a substrate to a mounting surface without increasing the package size.
【００１２】本発明の前記ならびにその他の課題と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１３】[0013]
【問題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記の通りである。Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.
【００１４】搭載された半導体チップと電気的に接続さ
れた外部電極が列状に配置された半導体装置において、
前記外部電極の列方向の間隔を不等ピッチとする。In a semiconductor device in which external electrodes electrically connected to a mounted semiconductor chip are arranged in a row,
The intervals in the column direction of the external electrodes are unequal pitches.
【００１５】また、半導体チップと電気的に接続されて
いる複数の外部電極が等間隔に配置された外部電極の列
が行方向に複数配置された半導体装置において、前記外
部電極の各列の外部電極の数を異ならせる。Further, in a semiconductor device in which a plurality of columns of external electrodes in which a plurality of external electrodes electrically connected to a semiconductor chip are arranged at equal intervals are arranged in a row direction, an external electrode of each column of the external electrodes is provided. Different number of electrodes.
【００１６】また、搭載された半導体チップと電気的に
接続された外部電極が列状に配置された半導体装置を基
板に複数実装し、前記外部電極と前記基板の接続電極と
を電気的に接続した半導体モジュールにおいて、前記半
導体装置の外部電極の列方向の間隔を不等ピッチとし、
前記外部電極と対応する基板の接続電極間の実装面に配
線を形成する。A plurality of semiconductor devices having external electrodes electrically connected to a mounted semiconductor chip arranged in a row are mounted on a substrate, and the external electrodes are electrically connected to connection electrodes of the substrate. In the semiconductor module, the intervals in the column direction of the external electrodes of the semiconductor device are unequal pitches,
Wiring is formed on the mounting surface between the external electrode and the corresponding connection electrode of the substrate.
【００１７】上述した手段によれば、前記接続電極の間
隔が広い部分にて、基板実装面に各半導体装置を並列に
接続する共通配線を通すことが可能となる。According to the above-described means, it is possible to pass the common wiring for connecting the respective semiconductor devices in parallel to the substrate mounting surface in the portion where the distance between the connection electrodes is wide.
【００１８】以下、本発明の実施の形態を説明する。な
お、実施の形態を説明するための全図において、同一機
能を有するものは同一符号を付け、その繰り返しの説明
は省略する。Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
【００１９】[0019]
【発明の実施の形態】（実施の形態１）図６は、本発明
の一実施の形態である半導体装置の外部電極の配置を示
す底面図であり、図７は図６中のａ−ａ線に沿った縦断
面図であり、図８はこの半導体装置を複数実装したモジ
ュールを示す平面図である。本実施の形態の半導体装置
はＤＤＲ−ＳＤＲＡＭの半導体記憶装置であり、ＣＳＰ
型の封止構造となっている。(Embodiment 1) FIG. 6 is a bottom view showing the arrangement of external electrodes of a semiconductor device according to an embodiment of the present invention, and FIG. 7 is aa-a in FIG. FIG. 8 is a vertical sectional view taken along a line, and FIG. 8 is a plan view showing a module in which a plurality of the semiconductor devices are mounted. The semiconductor device of this embodiment is a DDR-SDRAM semiconductor memory device,
It has a mold sealing structure.
【００２０】この半導体装置では、ベース１０に半導体
チップ１１を固定し、半導体チップ１１のパッドとベー
ス１０の配線とがバンプ１２によって電気的に接続さ
れ、ベース１０と半導体チップ１１との間隙には樹脂等
のアンダーフィル１３が充填されている。搭載された半
導体チップ１１と電気的に接続されたベース１０の配線
は、ベース１０の底面にアレイ状に形成された外部電極
２に接続されており、外部電極２は、列状に配置され、
列方向の間隔が不等ピッチとなっている。In this semiconductor device, a semiconductor chip 11 is fixed to a base 10, pads of the semiconductor chip 11 are electrically connected to wirings of the base 10 by bumps 12, and a gap between the base 10 and the semiconductor chip 11 is provided. An underfill 13 such as a resin is filled. The wiring of the base 10 electrically connected to the mounted semiconductor chip 11 is connected to the external electrodes 2 formed in an array on the bottom surface of the base 10, and the external electrodes 2 are arranged in a row.
The intervals in the column direction are unequal pitches.
【００２１】ＤＲＡＭを複数実装するメモリモジュール
では、アドレス信号或いは制御信号等の各半導体装置に
共通する共通配線６ａについては並列に接続してモジュ
ールの外部端子９に接続し、データ信号或いは入出力信
号等の各半導体装置に個別の個別配線６ｂについては夫
々個別に外部端子９に接続する。本実施の形態では、共
通配線６ａと接続する共通外部電極２ａの間隔が、個別
配線６ｂと接続する個別外部電極２ｂの間隔よりも広く
なっており、この広くなった共通外部電極２ａに対応さ
せて基板３に設けられた共通接続電極５ａ間の実装面に
共通配線６ａが形成されている。In a memory module in which a plurality of DRAMs are mounted, common wirings 6a common to each semiconductor device, such as address signals or control signals, are connected in parallel and connected to external terminals 9 of the module, and data signals or input / output signals are output. The individual wirings 6b that are individual to each semiconductor device are individually connected to the external terminals 9. In the present embodiment, the interval between the common external electrodes 2a connected to the common wiring 6a is wider than the interval between the individual external electrodes 2b connected to the individual wiring 6b. The common wiring 6a is formed on the mounting surface between the common connection electrodes 5a provided on the substrate 3.
【００２２】また、本実施の形態では共通外部電極２ａ
の間隔が、個別外部電極２ｂの間隔の整数倍となってい
る。このため等ピッチを前提とした従来の試験装置等を
用いたテスティング等の処理を行なうことが可能であ
る。In this embodiment, the common external electrode 2a
Is an integral multiple of the interval between the individual external electrodes 2b. Therefore, it is possible to perform processing such as testing using a conventional test device or the like on the premise of equal pitch.
【００２３】また、マザーボード等との接続のために設
けられるモジュールの外部端子９は、基板３の長辺端部
に並設されたエッジコネクタとなっており、搭載される
半導体装置１は、モジュール基板３の短辺に沿って半導
体装置１の長辺を配置し、モジュール基板３の長辺方向
に横並びに配置されている。このため図９に示す、個別
外部電極２ｂの間隔を拡げ、個別接続電極５ｂの間隔も
拡げた場合との比較では、基板３の個別接続電極５ｂか
ら外部端子９までの配線長を短くすることができる。こ
のためデータ信号或いは入出力信号等の配線に高速性を
要求されるＤＤＲ等の方式では、特に有利となる。The external terminals 9 of the module provided for connection to a motherboard or the like are edge connectors arranged side by side on the long side of the substrate 3. The long sides of the semiconductor device 1 are arranged along the short side of the substrate 3, and are arranged side by side in the long side direction of the module substrate 3. Therefore, in comparison with the case where the distance between the individual external electrodes 2b is increased and the distance between the individual connection electrodes 5b is increased as shown in FIG. 9, the wiring length from the individual connection electrode 5b of the substrate 3 to the external terminal 9 is reduced. Can be. This is particularly advantageous in a system such as DDR that requires high-speed wiring for data signals or input / output signals.
【００２４】図１０には、２５６Ｍビットの４８ピンＤ
ＤＲ−ＳＤＲＡＭ型半導体装置に本発明を適用した例を
示し、図１１にはこの半導体装置を実装したメモリモジ
ュールの例を示す。半導体チップ１１に対して、共通外
部電極２ａ及び個別外部電極２ｂは、ベース１０の内部
配線１４によって、対応する半導体チップ１１のパッド
と接続されている。なお、図中の１１ａは次世代の同等
チップのチップサイズの予定値を、１１ｂは次々世代の
同等チップのチップサイズの予想値を示している。FIG. 10 shows a 256-Mbit, 48-pin D
An example in which the present invention is applied to a DR-SDRAM type semiconductor device is shown. FIG. 11 shows an example of a memory module in which this semiconductor device is mounted. With respect to the semiconductor chip 11, the common external electrode 2a and the individual external electrode 2b are connected to the corresponding pads of the semiconductor chip 11 by the internal wiring 14 of the base 10. In the figure, 11a indicates the expected value of the chip size of the next-generation equivalent chip, and 11b indicates the expected value of the chip size of the next-generation equivalent chip.
【００２５】（実施の形態２）図１２は、本発明の他の
実施の形態である半導体装置の外部電極の配置を示す底
面図である。本実施の形態の半導体装置はＤＤＲ−ＳＤ
ＲＡＭの半導体記憶装置であり、ＣＳＰ型の封止構造と
なっている。Embodiment 2 FIG. 12 is a bottom view showing the arrangement of external electrodes of a semiconductor device according to another embodiment of the present invention. The semiconductor device of this embodiment is a DDR-SD
This is a semiconductor storage device for a RAM and has a CSP type sealing structure.
【００２６】この半導体装置では、外部電極２ａ，２ｂ
の配置を除いた構成は前述した実施の形態の場合と同様
である。本実施の形態では、等間隔に配置された外部電
極２ａ，２ｂの列が行方向に複数配置されており、共通
外部電極２ａの行方向の数が、個別外部電極２ｂの行方
向の数よりも少なくなっている。即ち、共通外部電極２
ａは２列に形成し、個別外部電極２ｂは４列に形成して
ある。このため、共通外部電極２ａ間を通る共通配線の
数は１本となり、基板の実装面に共通配線を形成するこ
とが可能となる。In this semiconductor device, the external electrodes 2a, 2b
The configuration except for the arrangement is the same as in the above-described embodiment. In the present embodiment, a plurality of columns of external electrodes 2a and 2b arranged at equal intervals are arranged in the row direction, and the number of common external electrodes 2a in the row direction is larger than the number of individual external electrodes 2b in the row direction. Is also decreasing. That is, the common external electrode 2
a is formed in two rows, and the individual external electrodes 2b are formed in four rows. Therefore, the number of common wires passing between the common external electrodes 2a is one, and it is possible to form the common wires on the mounting surface of the substrate.
【００２７】また、本実施の形態では、共通外部電極２
ａの間隔を個別外部電極２ｂの間隔と同一としたまま
で、基板の実装面に共通配線を形成することが可能とな
る。In this embodiment, the common external electrode 2
The common wiring can be formed on the mounting surface of the substrate while keeping the interval of a the same as the interval of the individual external electrodes 2b.
【００２８】以上、本発明者によってなされた発明を、
前記実施の形態に基づき具体的に説明したが、本発明
は、前記実施の形態に限定されるものではなく、その要
旨を逸脱しない範囲において種々変更可能であることは
勿論である。As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.
【００２９】[0029]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００３０】（１）本発明によれば、モジュールの実装
面に共通配線を形成することができるという効果があ
る。(1) According to the present invention, there is an effect that a common wiring can be formed on a mounting surface of a module.
【００３１】（２）本発明によれば、上記効果（１）に
より、モジュール基板の配線層数の増加を防止すること
が可能となるという効果がある。(2) According to the present invention, the effect (1) has an effect that it is possible to prevent an increase in the number of wiring layers of the module substrate.
【００３２】（３）本発明によれば、上記効果（２）に
より、ビアホール数の増加を防止することができるとい
う効果がある。(3) According to the present invention, the effect (2) has an effect that an increase in the number of via holes can be prevented.
【００３３】（４）本発明によれば、上記効果（１）
（２）により、基板コストの上昇を回避し、信頼性の低
下を防止することができるという効果がある。(4) According to the present invention, the above effect (1)
According to (2), there is an effect that an increase in substrate cost can be avoided and a decrease in reliability can be prevented.
【００３４】（５）本発明によれば、パッケージサイズ
増大を防止することができるという効果がある。(5) According to the present invention, there is an effect that an increase in package size can be prevented.
【図１】従来の半導体装置を示す底面図である。FIG. 1 is a bottom view showing a conventional semiconductor device.
【図２】従来のモジュール基板を示す要部平面図であ
る。FIG. 2 is a plan view of a main part showing a conventional module substrate.
【図３】接続電極の間隔と配線との関係を説明する図で
ある。FIG. 3 is a diagram illustrating the relationship between the spacing between connection electrodes and wiring.
【図４】従来のモジュール基板を示す平面図である。FIG. 4 is a plan view showing a conventional module substrate.
【図５】従来の半導体装置を示す底面図である。FIG. 5 is a bottom view showing a conventional semiconductor device.
【図６】本発明の一実施の形態である半導体装置を示す
底面図である。FIG. 6 is a bottom view showing a semiconductor device according to an embodiment of the present invention.
【図７】図６中のａ−ａ線に沿った縦断面図である。FIG. 7 is a longitudinal sectional view taken along the line aa in FIG.
【図８】本発明の一実施の形態である半導体モジュール
を示す平面図である。FIG. 8 is a plan view showing a semiconductor module according to an embodiment of the present invention.
【図９】従来の半導体モジュールを示す平面図である。FIG. 9 is a plan view showing a conventional semiconductor module.
【図１０】本発明の一実施の形態である半導体装置を示
す底面図である。FIG. 10 is a bottom view showing a semiconductor device according to an embodiment of the present invention.
【図１１】本発明の一実施の形態である半導体モジュー
ルを示す平面図である。FIG. 11 is a plan view showing a semiconductor module according to an embodiment of the present invention.
【図１２】本発明の他の実施の形態である半導体装置を
示す底面図である。FIG. 12 is a bottom view showing a semiconductor device according to another embodiment of the present invention.
１…半導体装置、２ａ…共通外部電極、２ｂ…個別外部
電極、３…基板、４…半導体チップ搭載領域、５ａ…共
通接続電極、５ｂ…個別接続電極、６ａ…共通配線、６
ｂ…個別配線、７…ビアホール、８…配線（内層）、９
…外部端子、１０…ベース、１１…半導体チップ、１２
…バンプ、１３…アンダーフィル、１４…内部配線。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2a ... Common external electrode, 2b ... Individual external electrode, 3 ... Substrate, 4 ... Semiconductor chip mounting area, 5a ... Common connection electrode, 5b ... Individual connection electrode, 6a ... Common wiring, 6
b: individual wiring, 7: via hole, 8: wiring (inner layer), 9
... external terminals, 10 ... base, 11 ... semiconductor chip, 12
... bumps, 13 ... underfill, 14 ... internal wiring.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 齋木 陽造 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 (72)発明者 中込 儀延 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 (72)発明者 管野 利夫 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yozo Saiki 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Yoshinobu Nakagome Josuihoncho, Kodaira-shi, Tokyo 5-20-1, Hitachi Semiconductor Co., Ltd. (72) Inventor Toshio Kanno 5-20-1, Kamimizu Honcho, Kodaira-shi, Tokyo Within Hitachi Semiconductor Co., Ltd.
Claims (11)
された外部電極が列状に配置された半導体装置におい
て、 前記外部電極の列方向の間隔が不等ピッチとなっている
ことを特徴とする半導体装置。1. A semiconductor device in which external electrodes electrically connected to a mounted semiconductor chip are arranged in rows, wherein the external electrodes are arranged at irregular intervals in the column direction. Semiconductor device.
部電極とからなり、前記共通外部電極の間隔が、前記個
別外部電極の間隔よりも広いことを特徴とする請求項１
に記載の半導体装置。2. An external electrode comprising a common external electrode and an individual external electrode, wherein an interval between the common external electrodes is wider than an interval between the individual external electrodes.
3. The semiconductor device according to claim 1.
部電極の間隔の整数倍となっていることを特徴とする請
求項１又は請求項２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein an interval between the common external electrodes is an integral multiple of an interval between the individual external electrodes.
ことを特徴とする請求項１乃至請求項３の何れか一項に
記載の半導体装置。4. The semiconductor device according to claim 1, wherein said semiconductor chip is a memory chip.
複数の外部電極が等間隔に配置された外部電極の列が行
方向に複数配置された半導体装置において、前記外部電
極の各列の外部電極の数が異なっていることを特徴とす
る半導体装置。5. In a semiconductor device in which a plurality of columns of external electrodes, in which a plurality of external electrodes electrically connected to a semiconductor chip are arranged at equal intervals, are arranged in a row direction, an external portion of each column of the external electrodes is provided. A semiconductor device having a different number of electrodes.
部電極とからなり、前記共通外部電極の行方向の外部電
極の数が、前記個別外部電極の行方向の外部電極の数よ
りも少ないことを特徴とする請求項５に記載の半導体装
置。6. The external electrode includes a common external electrode and an individual external electrode, and the number of external electrodes in the row direction of the common external electrode is smaller than the number of external electrodes in the row direction of the individual external electrodes. The semiconductor device according to claim 5, wherein:
ことを特徴とする請求項５又は請求項６に記載の半導体
装置。7. The semiconductor device according to claim 5, wherein said semiconductor chip is a memory chip.
された外部電極が列状に配置された半導体装置を基板に
複数実装し、前記外部電極と前記基板の接続電極とを電
気的に接続した半導体モジュールにおいて、 前記半導体装置の外部電極の列方向の間隔が不等ピッチ
となっており、前記外部電極と対応する基板の接続電極
間の実装面に配線が形成されていることを特徴とする半
導体モジュール。8. A plurality of semiconductor devices in which external electrodes electrically connected to a mounted semiconductor chip are arranged in a row are mounted on a substrate, and the external electrodes are electrically connected to connection electrodes of the substrate. In the semiconductor module, the intervals in the column direction of the external electrodes of the semiconductor device are unequal pitches, and wiring is formed on a mounting surface between the connection electrodes of the substrate and the external electrodes. Semiconductor module.
続電極とからなり、前記共通接続電極の間隔が、前記個
別接続電極の間隔よりも広く、この共通接続電極間に配
線が形成されていることを特徴とする請求項８に記載の
半導体モジュール。9. The connection electrode includes a common connection electrode and an individual connection electrode, an interval between the common connection electrodes is wider than an interval between the individual connection electrodes, and a wiring is formed between the common connection electrodes. The semiconductor module according to claim 8, wherein:
接続電極の間隔の整数倍となっていることを特徴とする
請求項８又は請求項９に記載の半導体モジュール。10. The semiconductor module according to claim 8, wherein an interval between the common connection electrodes is an integral multiple of an interval between the individual connection electrodes.
ることを特徴とする請求項８乃至請求項１０の何れか一
項に記載の半導体モジュール。11. The semiconductor module according to claim 8, wherein said semiconductor device is a semiconductor memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21632299A JP3813768B2 (en) | 1999-07-30 | 1999-07-30 | Semiconductor device and semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21632299A JP3813768B2 (en) | 1999-07-30 | 1999-07-30 | Semiconductor device and semiconductor module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001044325A true JP2001044325A (en) | 2001-02-16 |
| JP3813768B2 JP3813768B2 (en) | 2006-08-23 |
Family
ID=16686722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21632299A Expired - Lifetime JP3813768B2 (en) | 1999-07-30 | 1999-07-30 | Semiconductor device and semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3813768B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7361997B2 (en) | 2003-12-01 | 2008-04-22 | Ricoh Company, Ltd. | Device package, a printed wiring board, and an electronic apparatus with efficiently spaced bottom electrodes including intervals between bottom electrodes of different lengths |
| JP2008135063A (en) * | 2001-04-24 | 2008-06-12 | Rambus Inc | Method and apparatus for coordinating memory operation among diversely-located memory components |
| US8320202B2 (en) | 2001-04-24 | 2012-11-27 | Rambus Inc. | Clocked memory system with termination component |
| JP2016127259A (en) * | 2015-01-07 | 2016-07-11 | 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． | Display device |
| US9437279B2 (en) | 2004-09-15 | 2016-09-06 | Rambus Inc. | Memory controller with clock-to-strobe skew compensation |
-
1999
- 1999-07-30 JP JP21632299A patent/JP3813768B2/en not_active Expired - Lifetime
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8717837B2 (en) | 2001-04-24 | 2014-05-06 | Rambus Inc. | Memory module |
| US9741424B2 (en) | 2001-04-24 | 2017-08-22 | Rambus Inc. | Memory controller |
| US8760944B2 (en) | 2001-04-24 | 2014-06-24 | Rambus Inc. | Memory component that samples command/address signals in response to both edges of a clock signal |
| JP4489817B2 (en) * | 2001-04-24 | 2010-06-23 | ラムバス・インコーポレーテッド | Method and apparatus for coordinating memory operations from variously arranged memory components |
| US8214616B2 (en) | 2001-04-24 | 2012-07-03 | Rambus Inc. | Memory controller device having timing offset capability |
| US8320202B2 (en) | 2001-04-24 | 2012-11-27 | Rambus Inc. | Clocked memory system with termination component |
| US8359445B2 (en) | 2001-04-24 | 2013-01-22 | Rambus Inc. | Method and apparatus for signaling between devices of a memory system |
| US8391039B2 (en) | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
| US8395951B2 (en) | 2001-04-24 | 2013-03-12 | Rambus Inc. | Memory controller |
| US8462566B2 (en) | 2001-04-24 | 2013-06-11 | Rambus Inc. | Memory module with termination component |
| US8537601B2 (en) | 2001-04-24 | 2013-09-17 | Rambus Inc. | Memory controller with selective data transmission delay |
| US8625371B2 (en) | 2001-04-24 | 2014-01-07 | Rambus Inc. | Memory component with terminated and unterminated signaling inputs |
| US10706910B2 (en) | 2001-04-24 | 2020-07-07 | Rambus Inc. | Memory controller |
| US9053778B2 (en) | 2001-04-24 | 2015-06-09 | Rambus Inc. | Memory controller that enforces strobe-to-strobe timing offset |
| US10236051B2 (en) | 2001-04-24 | 2019-03-19 | Rambus Inc. | Memory controller |
| US9311976B2 (en) | 2001-04-24 | 2016-04-12 | Rambus Inc. | Memory module |
| JP2008135063A (en) * | 2001-04-24 | 2008-06-12 | Rambus Inc | Method and apparatus for coordinating memory operation among diversely-located memory components |
| US9472262B2 (en) | 2001-04-24 | 2016-10-18 | Rambus Inc. | Memory controller |
| US7598621B2 (en) | 2003-12-01 | 2009-10-06 | Ricoh Company, Ltd. | Device package, a printed wiring board, and an electronic apparatus with efficiently spaced bottom electrodes including intervals between bottom electrodes of different lengths |
| US7361997B2 (en) | 2003-12-01 | 2008-04-22 | Ricoh Company, Ltd. | Device package, a printed wiring board, and an electronic apparatus with efficiently spaced bottom electrodes including intervals between bottom electrodes of different lengths |
| US9437279B2 (en) | 2004-09-15 | 2016-09-06 | Rambus Inc. | Memory controller with clock-to-strobe skew compensation |
| US9830971B2 (en) | 2004-09-15 | 2017-11-28 | Rambus Inc. | Memory controller with clock-to-strobe skew compensation |
| US11664067B2 (en) | 2004-09-15 | 2023-05-30 | Rambus Inc. | Memory system component that enables clock-to-strobe skew compensation |
| US10325645B2 (en) | 2004-09-15 | 2019-06-18 | Rambus Inc. | Memory controller with clock-to-strobe skew compensation |
| US10755764B2 (en) | 2004-09-15 | 2020-08-25 | Rambus Inc. | Memory component that enables calibrated command- and data-timing signal arrival |
| US11100976B2 (en) | 2004-09-15 | 2021-08-24 | Rambus Inc. | Memory controller with clock-to-strobe skew compensation |
| JP2016127259A (en) * | 2015-01-07 | 2016-07-11 | 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3813768B2 (en) | 2006-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11227639B2 (en) | Stacked DRAM device and method of manufacture | |
| US6836007B2 (en) | Semiconductor package including stacked semiconductor chips | |
| JP6117787B2 (en) | Packaging of DRAM and SOC in IC package | |
| US6297548B1 (en) | Stackable ceramic FBGA for high thermal applications | |
| USRE42363E1 (en) | Stackable electronic assembly | |
| US6242814B1 (en) | Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly | |
| US6583365B2 (en) | Conductive pads layout for BGA packaging structure | |
| JP4707446B2 (en) | Semiconductor device | |
| WO2009104536A1 (en) | Semiconductor chip and semiconductor device | |
| WO1998021752A1 (en) | Memory module | |
| US20020088633A1 (en) | Multi-chip memory devices, modules and control methods including independent control of memory chips | |
| US9123554B2 (en) | Semiconductor device | |
| US5869895A (en) | Embedded memory assembly | |
| US20060081972A1 (en) | Fine pitch grid array type semiconductor device | |
| US5982654A (en) | System for connecting semiconductor devices | |
| JP3813768B2 (en) | Semiconductor device and semiconductor module | |
| US10679956B2 (en) | Semiconductor memory chip, semiconductor memory package, and electronic system using the same | |
| US5991185A (en) | Semiconductor memory | |
| US10952327B2 (en) | Semiconductor module | |
| US20060186403A1 (en) | Semiconductor device | |
| KR100652411B1 (en) | Semiconductor memory device maximizing bonding pad | |
| JPH10284681A (en) | Memory module | |
| KR20020041114A (en) | Semiconductor chip and semiconductor chip package using the same | |
| JPH10303362A (en) | Memory system | |
| JPH10303253A (en) | Memory system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040227 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050701 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060228 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060427 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060530 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060601 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 3813768 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090609 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100609 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100609 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110609 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110609 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120609 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120609 Year of fee payment: 6 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120609 Year of fee payment: 6 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120609 Year of fee payment: 6 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120609 Year of fee payment: 6 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120609 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130609 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130609 Year of fee payment: 7 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130609 Year of fee payment: 7 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130609 Year of fee payment: 7 |
|
| EXPY | Cancellation because of completion of term |