JP2001024192A - Iv family semiconductor field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high performance field-effect transistor using the IV family semiconductor. SOLUTION: Si0.7Ge0.3 layer 213 which is a first barrier layer, i-Si channel layer 214, Si0.7Ge0.3 layer 215 which is a second barrier layer, i-Si channel layer 216, and Si0.7Ge0.3 layer 217 which is a third barrier layer, are laminated on a semiconductor substrate and electron mobility of one channel in the i-Si channel layer is made 1/100 or less of electron mobility of the other channel layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a group IV element of Si or Ge and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional field effect transistor using Si and Ge is disclosed in Extended Abstracts of 1993 International Conference on Solid State Devices and Materials, McHari, 1993, pp. 201-203 (Extended Abstravts of the 1993). International Con
ference on Solid State Devices and Materials, Maku
hari (1993) pp. 201-203). In this field-effect transistor, barrier layers made of Si _0.7 Ge _0.3 are arranged above and below a channel having a thickness of about 25 nm to increase carrier mobility.

[0003]

In the above-mentioned conventional field effect transistor, a voltage is applied between a gate electrode and a source electrode / drain electrode to extract or return carriers of electrons and holes from the source electrode / drain electrode. The transistor operation is performed. Therefore, the operation speed of a transistor is determined by accumulating or discharging electric charge in a channel by a gate voltage, and is represented by a square root of a product of a resistance and a capacitance. Therefore, since the source resistance and the like increase with miniaturization of the element, the performance as the element has not been improved.

A first object of the present invention is to provide a high performance field effect transistor. A second object of the present invention is to provide a method for manufacturing such a field effect transistor.

[0005]

Means for Solving the Problems To achieve the first object, a field effect transistor of the present invention comprises a Si _1-x Ge _x mixed crystal (where x is 0 <x < 1 in the range of 1).
Of a first barrier layer and a first epitaxial layer
A second barrier layer composed of an epitaxially grown Si channel layer, an Si _1-x Ge _x mixed crystal (where x is a value in the above range), and a second Si channel layer composed of a Si epitaxially grown layer And a third barrier layer composed of an epitaxially grown layer of a mixed crystal of Si _1-x Ge _x (where x is a value in the above range), and the first and second Si channel layers are stacked. The mobility of electrons in one of the channel layers is set to be 1/100 or less of the mobility of electrons in the other channel layer.

Here, it is preferable that the first and third barrier layers contain an impurity of a group V element. The above x is
It is preferable to set the value in the range of 0.1 ≦ x ≦ 0.5.
In order to make the mobility of electrons in one channel layer one hundredth or less of that in the other channel layer, for example, one of the channel layers is made to have rough upper and lower surfaces, and its film thickness is reduced. do it. This film thickness is preferably from 10 nm to 2 nm.
The range is 0 nm. If it is less than 10 nm, the thickness as an electron accumulation region is insufficient, and if it is more than 20 nm, the mobility of electrons is difficult to decrease. The mobility of electrons in one channel layer may be zero.

The thickness of the other channel layer is 20 n
It is preferably in the range of m to 30 nm. If the thickness is less than 20 nm, the thickness as an electron accumulation region when the mobility of electrons is large is insufficient, and if it exceeds 30 nm, the voltage of a tunnel current described later increases.

In order to achieve the first object,
The field effect transistor of the present invention has a structure in which S
a _first barrier layer composed of an epitaxially grown layer of i _1-x Ge _x mixed crystal (where x is a value in the range of 0 <x <1), a first Ge channel layer composed of a Ge epitaxially grown layer, A second barrier layer composed of an epitaxially grown Si _1-x Ge _x mixed crystal (where x is in the above range) and a second barrier layer composed of a Ge epitaxially grown layer
An e-channel layer and a third barrier layer composed of an epitaxially grown layer of a mixed crystal of Si _1-x Ge _x (where x is a value in the above range) are stacked, and the first and second Ge channels are stacked. The mobility of electrons in one channel layer of the layers is set to be 1/100 or less of the mobility of electrons in the other channel layer.

Here, it is preferable that the first and third barrier layers contain a group III element impurity. Also, the above x
Is preferably a value in the range of 0.5 ≦ x ≦ 0.9. To make the mobility of electrons in one channel layer one hundredth or less of that in the other channel layer, the same as described above may be used. Therefore, the thickness of one channel layer is 1
It is preferably in the range of 0 nm to 20 nm. The mobility of electrons in one channel layer may be zero. Also,
The other channel layer preferably has a thickness in the range of 20 nm to 30 nm. The preferable reasons for these thickness ranges are the same as described above.

In any of the field effect transistors, two channels having greatly different mobilities are provided close to each other, and a voltage is applied to the gate electrode so that the other channel (the channel having the higher electron mobility) is shifted from the other channel. It operates by moving a carrier to one channel. Therefore,
The second barrier layer needs to be thin enough to allow electrons to tunnel, and a preferred thickness is 1 nm to 5 nm.
Range. If it exceeds 5 nm, it becomes difficult for electrons to tunnel, and if it is less than 1 nm, it becomes difficult to control electrons. According to the present invention, it is possible to realize a field-effect transistor that operates twice or more at high speed as compared with a conventional device that uses charging and discharging of gate capacitance.

FIG. 1A illustrates this principle.
This will be described with reference to FIG. When a voltage is applied to the gate, carriers move by a tunnel effect in the thin Si _1-x Ge _x mixed crystal layer as shown in FIGS. 1A and 1B, and the carrier mobility changes instantaneously. In general, the electrical conductivity of a device is represented by the following equation.

Electric conductivity = elementary charge × mobility × carrier concentration In the conventional device, the carrier concentration is changed by a gate voltage. The present invention is different from the above in that the mobility is changed to change the electric conductivity. A field-effect transistor that can operate without causing carriers to enter and exit from the source / drain electrodes and that does not require gate capacitor charge / discharge time can be operated at high speed.

Further, in order to achieve the second object,
According to the method of manufacturing a field effect transistor of the present invention, a first barrier layer is formed by epitaxially growing a Si _1-x Ge _x mixed crystal (where x is a value in the range of 0 <x <1) on a semiconductor substrate. Is formed thereon, Si is epitaxially grown thereon to form a first Si channel layer, and then Si _{1− X}
Ge _X mixed crystal (where, x is a value in the range described above) to form a second barrier layer is epitaxially grown, by epitaxial growth of Si to the next to form a second Si channel layer, next to the Si _1-X Ge _X mixed crystal (where, x is a is a value within the above range) third with the epitaxially grown
Of the first and second Si layers.
The upper and lower surfaces of one of the channel layers are roughened, and the upper and lower surfaces of the other channel layer of the first and second Si channel layers are smoothed. The mobility of electrons in the channel layer is set to be 1/100 or less of the mobility of electrons in the other channel layer.

Further, in order to achieve the second object, a method of manufacturing a field-effect transistor according to the present invention comprises the steps of: forming a Si _1-x Ge _x mixed crystal (where x is 0 <x) on a semiconductor substrate;
<A value in the range of 1) is epitaxially grown to form a first barrier layer, and Ge is epitaxially grown thereon to form a first Ge channel layer.
i _1-X Ge _X mixed crystal (where x is a value in the above range)
Is epitaxially grown to form a second barrier layer,
Next, Ge is epitaxially grown to form a second Ge channel layer, and then a Si _1-x Ge _x mixed crystal (however, x
Is a value in the above range) to form a third barrier layer by epitaxial growth, wherein the upper and lower surfaces of one of the first and second Ge channel layers are roughened, Furthermore, by making the upper and lower surfaces of the other channel layer of the first and second Ge channel layers smooth, the mobility of electrons in one channel layer can be reduced by the mobility of electrons in the other channel layer. It is designed to be 1/100 or less.

The bulk lattice constant of the Si _1-x Ge _x mixed crystal is
Due to the difference in the atomic radius between Si and Ge, the lattice constant increases from the lattice constant of Si to the lattice constant of Ge with the Ge mixed crystal ratio X.
When the Si _1-x Ge _x mixed crystal is grown on a Si substrate, if the film thickness is small, the mixed crystal grows lattice-matched to the Si substrate, and therefore receives biaxial compressive stress from the Si substrate. When the grown film thickness is increased in such a state, strain energy is accumulated in the film in proportion to the film thickness, and dislocation occurs in the film to relax the strain at a certain film thickness (critical film thickness). As described above, by growing beyond the critical film thickness, dislocations are introduced into the film, and a Si _1-x Ge _x mixed crystal free from stress from the substrate is formed on the Si substrate. The Si _1-x Ge _x mixed crystal thus formed is preferably used as the first barrier layer.

On top of this, a Si layer (or Ge layer) and Si _1-X
By growing the Ge _x mixed crystal layer in lattice matching with the Si _1-x Ge _x mixed crystal, the biaxial tensile stress applied S
An i-channel layer (or Ge channel layer) is formed. Low mobility Si (or Ge) channel layer and high mobility Si
The (or Ge) channel layer is preferably formed so as to sandwich a Si _1-x Ge _x mixed crystal of about _{1 to 5} nm.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. <Embodiment 1> As shown in FIG.
The m-type p-type Si (100) substrate 211 is chemically cleaned and put into a growth apparatus. After surface cleaning, Si is grown on the substrate at a substrate temperature of 600 ° C. using a Si evaporation source by electron beam heating, and impurities are doped. I-Si layer 212 which is not used
Is grown to 50 nm. Next, a Ge vapor deposition source using heater heating and a Si vapor deposition source are simultaneously used, and a Si _0.7 Ge _0.3 layer 213 is further formed on the i-Si layer 212 at a substrate temperature of 600 ° C. beyond the critical film thickness of 2000 nm. Si _0.7 Ge _0.3 layer 21 grown and unstressed by the substrate
3 was formed. At the time of this growth, before growing the last 5 nm, 5 × 10 ¹¹ Sb / cm ^{2 is} deposited as an impurity as an impurity, and then the last 5 nm is grown.

On the Si _0.7 Ge _0.3 layer 213, a thickness of 2
A 0 nm i-Si channel layer 214 is formed at a substrate temperature of 600 ° C.
And the i-Si channel layer 214 is subjected to biaxial tensile stress from the Si _0.7 Ge _0.3 layer 213. On top of this, 5 nm without further impurity doping
An i-Si _0.7 Ge _0.3 layer 215 was formed. At this growth temperature, the mixing of the Si channel and the SiGe layer is 10 n
m, the two hetero interfaces of the Si _0.7 Ge _0.3 layer 213 / i-Si channel layer 214 / i-Si _0.7 Ge _0.3 layer 215 become rough, and the i-Si channel layer 214
Has an extremely low electron mobility of about 10 cm ² / V · s.

This i-Si_0.7Ge_0.3On layer 215,
i-Si_0.7Ge_0.3Purpose of preventing mixing with layer 215
Atomic hydrogen gas at the same time as Si and Ge at the deposition rate of Si
Irradiate the substrate surface with an amount of 1/10 or more of the i-Si
The channel layer 216 is made of 20 nm, Si_0.7Ge_0.3Layer 217
Was grown to 15 nm. Note that Si_0.7Ge_0.3Layer 217
Is the same as above after growing the first 5 nm.
Sb is 5 × 10 ¹¹Pieces / cm^TwoEvaporated, then rest
Of 10 nm was grown. Due to the above hydrogen irradiation effect, i
-Si_0.7Ge_0.3Layer 215 / i-Si channel layer 216
/ Si_0.7Ge_0.3The heterointerface of the layer 217 is 3 nm or less.
It has steepness and the electrons of the i-Si channel layer 216
Mobility is 2000cm^Two/ V · s and the above i-Si channel
Having a mobility 100 times or more higher than that of the
Made. Further, an i-Si cap layer 21 is further formed thereon.
8 was grown to 5 nm. This i-Si cap layer 218
It is not necessary to irradiate hydrogen when growing.

The multilayer structure is taken out of the growth apparatus, and as shown in FIG. 2B, a gate oxide film 219 is formed by photolithography or ion implantation of a conventional process or thermal oxidation of the i-Si cap layer 218, An n-channel field-effect transistor structure using the i-Si channel layers 214 and 216 as an electron channel by using a vapor deposition technique. Here, 220 is an As implantation region of an n-type impurity, 221 is a source electrode, 222 is a drain electrode, 22
Reference numeral 3 denotes a gate electrode, each of which is made of aluminum. Note that the impurities may be V-group impurities such as As and P instead of Sb.

<Embodiment 2> As shown in FIG. 3A, an n-type Si (100) substrate 311 having a resistivity of 5 Ωcm is chemically cleaned and put into a growth apparatus. Using an evaporation source, Si is grown on a substrate at a substrate temperature of 600 ° C.
A Si layer 312 is grown to a thickness of 50 nm. Next, a Ge vapor deposition source using heater heating and a Si vapor deposition source are simultaneously used, and a Si _0.3 Ge _0.7 layer is further formed on the i-Si layer 312.
The layer 313 is deposited at a substrate temperature of
Si _0.3 which was grown to 0 nm and was not stressed from the substrate
A Ge _0.7 layer 313 was formed. At the time of this growth, B was doped at 5 × 10 ¹¹ / cm ^{2 in the same} manner as in Example 1 before growing the last 5 nm.

On this Si _0.3 Ge _0.7 layer 313, 20 nm
The i-Ge channel layer 314 is grown, Si _0.3 Ge
_The i-Ge channel layer 314 was subjected to biaxial compressive stress from the _0.7 layer 313. On top of this, a 5 nm i-Si _0.3 Ge _0.7 layer 315 which is not further doped with impurities.
Was formed. At this growth temperature, the i-Ge channel layer and S
The mixing of the iGe layer occurs at about 10 nm, and the Si _0.3 G
e _0.7 layer 313 / i-Ge channel layer 314 / i-Si
_The two hetero interfaces of the _0.3 Ge _0.7 layer 315 became rough, and the hole mobility of the i-Ge channel layer 314 was extremely low, about 10 cm ² / V · s.

On this i-Si _0.3 Ge _0.7 layer 315,
In order to prevent mixing with the i-Si _0.3 Ge _0.7 layer 315, the substrate surface is irradiated with atomic hydrogen gas at the same time as Ge and Si in an amount equal to or more than one-tenth of the deposition rate of Ge.
The channel layer 316 has a thickness of 20 nm and the Si _0.3 Ge _0.7 layer 317
Was grown to 15 nm. The Si _0.3 Ge _0.7 layer 317
Is B at 5 nm from the bottom in the same manner as in Example 1.
Was doped at 5 × 10 ¹¹ / cm ² . Due to the above hydrogen irradiation effect, the hetero interface of the i-Si _0.3 Ge _0.7 layer 315 / i-Ge channel layer 316 / Si _0.3 Ge _0.7 layer 317 is 3
nm or less, and the i-Ge channel layer 3
The electron mobility of No. 16 is 1300 cm ² / V · s, which is i-
A structure having 100 or more times the electron mobility of the Ge channel layer 314 was manufactured. Further, an i-Si cap layer 318 was grown thereon to a thickness of 5 nm. When growing the i-Si cap layer 318, there is no need for hydrogen irradiation.

The multilayer structure is taken out of the growth apparatus, and as shown in FIG. 3B, a gate oxide film 319 is formed by photolithography or ion implantation of a conventional process or thermal oxidation of the i-Si cap layer 318, and A p-channel field effect transistor structure using the i-Ge channel layers 314 and 316 as a hole channel was formed by using a vapor deposition technique. Here, 320 is a B-implanted region of a p-type impurity,
321 is a source electrode, 322 is a drain electrode, and 323 is a gate electrode, all of which are made of aluminum. Note that the impurities may be Group III impurities such as Ga instead of B.

[0025]

According to the present invention, a high-performance field-effect transistor using a group IV semiconductor can be obtained. Further, such a field effect transistor could be easily formed.

[Brief description of the drawings]

FIG. 1 illustrates the principle of the present invention.

FIG. 2 is a manufacturing process diagram of the n-channel field-effect transistor according to the first embodiment.

FIG. 3 is a manufacturing process diagram of a p-channel field-effect transistor of Example 2.

[Explanation of symbols]

211 ... p-type Si (100) substrate 212, 312 ... i-Si layer 213 ... Si _0.7 Ge _0.3 layer 214, 216 ... i-Si channel layer 215 ... i-Si _0.7 Ge _0.3 layer 217 ... Si _0.7 Ge _0.3 layer 218 318 i-Si cap layer 219 319 gate oxide film 220 As injection region 221 321 source electrode 222 322 drain electrode 223 323 gate electrode 311 n-type Si (100) substrate 313 Si _0.3 Ge _0.7 layer 314, 316 ... i-Ge channel layer 315 ... i-Si _0.3 Ge _0.7 layer 317 ... Si _0.3 Ge _0.7 layer 320 ... B implantation region

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Nobuyuki Sugii 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory F-term (reference) 5F040 DA21 DA22 DC01 EB11 EC04 EE06 EF04 EF05 EH02 FC11 FC15

Claims (14)

[Claims] A first barrier layer comprising an epitaxially grown Si _1-x Ge _x mixed crystal (where x is a value in the range of 0 <x <1); A first Si channel layer, a second barrier layer composed of an epitaxially grown Si _1-x Ge _x mixed crystal (where x is a value in the above range), and a second Si channel composed of an Si epitaxially grown layer Layer and Si _1-X G
a third barrier layer comprising an epitaxially grown layer of e _x mixed crystal (where x is a value in the above range) is laminated;
A field-effect transistor, wherein the mobility of electrons in one of the first and second Si channel layers is one hundredth or less of the mobility of electrons in the other channel layer. 2. The field effect transistor according to claim 1, wherein said first and third barrier layers contain an impurity of a group V element. 3. The field effect transistor according to claim 1, wherein said x is in a range of 0.1 ≦ x ≦ 0.5. 4. The one channel layer has a thickness of 10
2. The range of nm to 20 nm.
4. The field-effect transistor according to any one of items 1 to 3. 5. The second barrier layer has a thickness of 1 nm.
5. The method according to claim 1, wherein the distance is in the range of 5 to 5 nm.
The field effect transistor according to any one of the above. 6. The field-effect transistor according to claim 1, wherein said semiconductor substrate is a p-type Si substrate. 7. A first barrier layer comprising a Si _1-x Ge _x mixed crystal (where x is a value in the range of 0 <x <1) and a first barrier layer comprising a Ge epitaxial growth layer on a semiconductor substrate. A first Ge channel layer, a second barrier layer composed of an epitaxially grown layer of Si _1-x Ge _x mixed crystal (where x is a value in the above range), and a second Ge channel composed of a Ge epitaxially grown layer Layer and Si _1-X G
a third barrier layer comprising an epitaxially grown layer of e _x mixed crystal (where x is a value in the above range) is laminated;
A field-effect transistor, wherein the mobility of electrons in one of the first and second Ge channel layers is one hundredth or less of the mobility of electrons in the other channel layer. 8. The field effect transistor according to claim 7, wherein said first and third barrier layers contain a group III element impurity. 9. The field effect transistor according to claim 7, wherein said x is in a range of 0.5 ≦ x ≦ 0.9. 10. The one channel layer has a thickness of 1
The field effect transistor according to any one of claims 7 to 9, wherein the range is 0 nm to 20 nm. 11. The second barrier layer has a thickness of 1n.
The field effect transistor according to any one of claims 7 to 10, wherein the range is from m to 5 nm. 12. The field effect transistor according to claim 7, wherein said semiconductor substrate is an n-type Si substrate. 13. A first barrier layer is formed by epitaxially growing a Si _1-x Ge _x mixed crystal (where x is a value in the range of 0 <x <1) on a semiconductor substrate. The first Si layer is epitaxially grown on the first barrier layer to form the first Si layer.
Forming a channel layer, and forming S on the first Si channel layer;
i _1-X Ge _X mixed crystal (where x is a value in the above range)
Is epitaxially grown to form a second barrier layer,
On the second barrier layer, Si is epitaxially grown to form a second Si channel layer. On the second Si channel layer, a Si _1-x Ge _x mixed crystal (where x is in the above range) Of forming a third barrier layer by epitaxial growth of the first and second Si channel layers, the upper and lower surfaces of one of the first and second Si channel layers are roughened, By making the upper and lower surfaces of the other channel layer of the first and second Si channel layers smooth,
A method for manufacturing a field-effect transistor, wherein the mobility of electrons in the one channel layer is set to 1/100 or less of the mobility of electrons in the other channel layer. 14. A first barrier layer is formed by epitaxially growing a Si ₁ -x Ge _x mixed crystal (where x is a value in the range of 0 <x <1) on a semiconductor substrate. Ge is epitaxially grown on the first barrier layer to form a first Ge.
Forming a channel layer, and forming S on the first Ge channel layer;
i _1-X Ge _X mixed crystal (where x is a value in the above range)
Is epitaxially grown to form a second barrier layer,
Ge is epitaxially grown on the second barrier layer to form a second Ge channel layer. On the second Ge channel layer, a Si _1-x Ge _x mixed crystal (where x is in the above range) Of forming a third barrier layer by epitaxial growth of the first and second Ge channel layers, wherein the upper and lower surfaces of one of the first and second Ge channel layers are roughened, By making the upper and lower surfaces of the other channel layer of the first and second Ge channel layers smooth,
A method for manufacturing a field-effect transistor, wherein the mobility of electrons in the one channel layer is set to 1/100 or less of the mobility of electrons in the other channel layer.