JP2001014218A - Memory module and memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the transfer speed of a signal in a memory module and to reduce the power consumption. SOLUTION: This memory module 3 consists of a memory controller 3a and memories 4 to 7 and has a configuration in which the semiconductor chips of the memories 4 to 7 are laminated on the semiconductor chip of the controller 3a. The controller 3a consists of AND circuits AD1 to AD16, only an AND circuit corresponding to a memory selected by any of chip enable signals CE1 to CD4 performs input-output of a data signal, an address signal or the like, and the other memories reduce parasitic capacitance to be driven in the module 3 and accelerate a memory system by electrically disconnecting a connection path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed operation technique in a memory system, and more particularly to a technique effective when applied to a high-speed data transfer in a memory module including a plurality of memories.

[0002]

2. Description of the Related Art According to studies made by the present inventor, for example, a memory system provided in a personal computer or the like is an EDO DRAM (Extende).
d Data Out Dynamic Random
Access Memory) and SDRAM (Syn)
a plurality of memories, such as a chronous DRAM)
And a memory controller for controlling these memories.

In this memory system, a plurality of memories are connected to one memory controller, and memory control signals other than a chip enable signal such as an address signal and a column address control signal are all signal terminals of the memory controller. The terminals are connected in parallel.

[0004] Further, the data signal is a set of a number of memories capable of forming a certain bus width, and the data signal terminals of the memories at the corresponding positions of the plurality of sets are connected in parallel to the data signal terminals of the memory controller. .

For example, when a memory system having a 64-bit data bus is composed of 64 memories having 8-bit I / Os, the control signal terminals of all the memories have corresponding control terminals of the memory controller. The signal terminals are connected in parallel, and the data signal terminals of eight memories are connected in parallel for each data signal terminal provided in the memory controller. Data read / write is performed for one memory selected by the chip enable signal among the eight memories connected to one data bus line.

Further, as a technique for mounting these memories, a so-called DIMM (Dual Inlin) in which eight memories are mounted on both sides of a printed wiring board, respectively.
e Memory Module) is widely used, and these four DIMMs are used to connect their terminals and the memory controller in parallel via wiring on the motherboard and DIMM sockets.

As an example describing this type of memory system in detail, see "Semiconductor MOS", published by Nikkan Kogyo Shimbun on August 30, 1990, edited by Yasuji Suzuki (ed.).
Memory and How to Use It "P114 to P126, and this document describes the circuit configuration and operation of a memory expansion DRAM board.

[0008]

However, the present inventors have found that the above-mentioned memory system has the following problems.

That is, since a plurality of memories are connected in parallel to one memory controller, control signals and data signals are transmitted and received between the memory controller and the memory selected by the chip enable signal. However, the input capacity of other memory that is not operating and the printed wiring board and socket connected to it, DI
The parasitic capacitance of the branch wiring on the printed wiring board in the MM must be charged / discharged, so that it is difficult to increase the transfer speed of control signals and data signals, and the power required for data transfer increases.

[0010] In addition, the control signal wiring and the data signal wiring have many branches, and the characteristic impedance is discontinuous there, so that multiple reflection of the signal occurs and the signal waveform is disturbed. In order to transfer data stably so as not to be affected by the disturbance of the signal waveform, the transfer speed must be reduced, and there is a problem that the memory system becomes slow.

Further, among a plurality of memories connected in parallel, the timing at which a data signal from the memory closest to the memory controller arrives differs from the timing at which a data signal from the farthest memory arrives. It is necessary for the memory controller to have a wide time window for receiving the data signal, and in this case also, there is a problem that the speed up in the memory system is hindered.

An object of the present invention is to provide a memory module and a memory system capable of increasing a signal transfer speed and greatly reducing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the memory module of the present invention comprises:
At least two semiconductor memories and memory control means for selecting one semiconductor memory based on a chip enable signal and inputting / outputting a control signal and a data signal only to the selected semiconductor memory are provided.

Also, in the memory module of the present invention, the memory control means calculates a logical product of a corresponding chip enable signal and a data signal to be written, and a corresponding chip enable signal and a read operation. A second arithmetic circuit for calculating the logical product of the data signal for use with the third chip and a third arithmetic circuit for calculating the logical product of the corresponding chip enable signal and the address signal, and a semiconductor selected by the chip enable signal It outputs the calculation results of the first to third calculation circuits corresponding to the memories.

Further, in the memory module according to the present invention, the semiconductor memory comprises a memory semiconductor chip having a connection terminal provided on a main surface near an end of one side, and the memory control means includes a memory semiconductor chip. The connection terminals corresponding to the connection terminals of the chip consist of a control semiconductor chip provided on the main surface, and the back surface of the lower memory semiconductor chip is connected to the main surface of the upper memory semiconductor chip. At least two of the stacked memory semiconductor chips are stacked so that the connection terminals of the memory semiconductor chip located on the upper side overlap and protrude from the end of the memory semiconductor chip located on the lower side. The memory chip is stacked so that the main surface of the memory chip faces the main surface of the control semiconductor chip. Of the connection terminals of the semiconductor chip connection terminals and control being connected by the columnar conductor.

A memory system according to the present invention includes at least one of the memory modules and a system controller that controls the entire electronic device.

Further, the memory system according to the present invention is a memory for selecting at least two semiconductor memories based on a chip enable signal and for inputting / outputting a control signal and a data signal only to the selected semiconductor memories. The semiconductor memory comprises control means and a system controller for controlling the entire electronic device.
A memory semiconductor chip provided with connection terminals on a main surface near an end of a certain side; the memory control means and the system controller are configured such that the connection terminals corresponding to the connection terminals of the memory semiconductor chip are formed on the main surface; , The lower surface of the lower memory semiconductor chip overlaps the main surface of the upper memory semiconductor chip, and the upper semiconductor memory chip Are stacked so as to protrude from the end of the lower memory semiconductor chip, and the main surfaces of at least two of the stacked memory semiconductor chips are the main surface of the system semiconductor chip. Laminated to face each other,
The connection terminals of the memory semiconductor chip and the connection terminals of the system semiconductor chip which are opposed to each other are connected by a columnar conductor.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a memory system according to an embodiment of the present invention, FIG. 2 is a sectional view of a memory module according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 is an explanatory diagram of a connection terminal in a memory controller provided in a memory module according to an embodiment of the present invention. FIG. 4 is an explanatory diagram of a circuit connection configuration of a memory module according to an embodiment of the present invention. FIG. 6 is an explanatory diagram of the circuit connection configuration of the memory module studied by the present inventors, and FIG. 7 is an explanatory diagram of the parasitic capacitance in the memory module studied by the present inventors. .

In the present embodiment, the memory system 1
Is provided, for example, in a personal computer (electronic device). The memory system 1 includes a system controller 2 and a memory module 3, as shown in FIG.

The system controller 2 controls hardware of the entire personal computer. The memory module 3 includes a memory controller (memory control means, control semiconductor chip) 3a,
And a plurality of memories 3b composed of DRAM semiconductor devices. The memory controller 3a stores the memory module 3 based on a control signal of the system controller.
Oversee the control of

The configuration of the memory system 1 will be described with reference to FIGS. Here, a plurality of memories 3
b is composed of four memories (semiconductor memory, semiconductor chip for memory) 4 to 7.

Memory controller 3a and memory 4
As shown in FIG. 2, each of the memory chips 3 to 7 is configured by a semiconductor chip, and has a configuration in which the semiconductor chips of the memories 4 to 7 are stacked on the semiconductor chip of the memory controller 3a. The thickness of the semiconductor chip in each of the memories 4 to 7 is about 50 μm.

FIG. 3 shows the main surface of the memory controller 3a.
As shown in FIG. 2, a plurality of connection terminals ST1 to which signal terminals of the memory 4 are connected near a peripheral portion on one predetermined side are connected to one.
The rows are formed at equal intervals. Similarly, the connection terminal ST
1, a connection terminal ST2 to which a signal terminal of the memory 5 is connected at a predetermined interval from the connection terminal ST1.
Are formed.

On the left of the connection terminal ST2, a connection terminal ST3 to which the signal terminal of the memory 6 is connected is formed at a fixed interval from the connection terminal ST2.
On the left side of the connection terminal ST3, a connection terminal ST4 to which a signal terminal of the memory 7 is connected is formed at a fixed interval from the connection terminal ST3.

Further, tapes 8 to 11 are adhered to the surface of the memory controller 3a as shown in FIG. The tape 8 extends from the connection terminal ST1 to the connection terminal S of the memory controller 3a provided with the connection terminal ST1.
T4 is sufficiently large to cover T4, and columnar conductors 12 are provided at positions corresponding to connection terminals ST1 to ST4.
To 15 are respectively formed.

A tape 9 is adhered to the upper surface of the tape 8, and the tape 9 is large enough to cover from the connection terminal ST2 to the connection terminal ST4 of the memory controller 3a. The tape 9 has columnar conductors 16 at positions corresponding to the connection terminals ST2 to ST4.
To 18 are formed.

A tape 10 is adhered to the upper surface of the tape 9. The tape 10 is a memory controller 3
The columnar conductors 19 and 20 are formed at positions corresponding to the connection terminals ST3 and ST4 so as to sufficiently cover the connection terminals ST3 and ST4.

The tape 11 is adhered to the upper surface of the tape 10 and has a size enough to sufficiently cover the connection terminals ST4 of the memory controller 3a.
A columnar conductor 21 is formed at a position corresponding to.

Further, in the memories 4 to 7, signal terminals are arranged in the vicinity of a peripheral portion of one side in a row in parallel with the side, and these memories 4 to 7 are stacked on the memory controller 3a. Has been implemented.

The memory 4 is stacked at a position where the signal terminal of the memory 4 faces the connection terminal ST1 of the memory controller 2. The memory 5 is stacked on the memory 4 so as to overhang, and the signal terminal of the memory 5 is similarly mounted at a position facing the connection terminal ST2.

The memory 6 is stacked on the memory 5 by overhanging, and the signal terminal of the memory 6 is mounted at a position facing the connection terminal ST3. Similarly, the memory 7 is overhanged and stacked on the memory 6,
The signal terminal of the memory 7 is mounted at a position facing the connection terminal ST4.

The input / output circuit and the power supply circuit are connected to the signal terminals of the memories 4 to 7 via wiring such as copper formed on the wiring layer of each semiconductor chip. The signal terminals provided in the memories 4 to 7 are connected to the corresponding memory controller 3 via the columnar conductors 12 to 21.
a are connected to the connection terminals ST1 to ST4, respectively.

Each of the tapes 8 to 11 has a polyimide tape having a thickness of about 40 μm coated with a heat-resistant adhesive having a thickness of about 5 μm on both sides thereof. The polyimide tape corresponds to the connection terminals ST1 to ST4. A through hole having a diameter of about 50 μm is provided at the position thus formed, and the conductors 12 to 21 are formed by filling the through hole with copper or the like.

The conductors 12 to 21 formed on each of the tapes 8 to 11 are provided with nickel plating as a base on both sides, tin on one side of the tape, and gold plating on the other side. ing. For example, in a state where the conductors 15 and 18 are assembled as a module, gold on the lower surface side of the conductor 18 located above and
Are connected to form a eutectic alloy.

Further, a gold layer is formed on the surface of the signal terminals in the memories 4 to 7, and the tapes 8 to 1 facing each other are formed.
The conductors 12, 16, 19, and 21 formed in 1 are connected to each other by forming a eutectic alloy with tin on the upper surface.

The conductor 12 formed on the lowermost tape 8
To 15 are gold formed on the lower surfaces of the conductors 12 to 15, and connection terminals ST1 to ST of the memory controller 3a.
A eutectic alloy is formed with the tin layer formed on the four surfaces and each is connected. The memories 4 to 7 constituting the memory module are covered with a case or a mold resin in order to prevent damage to each semiconductor chip.

Next, the circuit configuration and connection configuration of the memory module 3 will be described with reference to FIG.

Here, in order to simplify the explanation, the memory controller 3a has one data terminal and two address terminals, and the memories 4 to 7 have the same configuration.
The configuration includes one data terminal and two address terminals. In FIG. 4, power supply terminals of the memories 4 to 7 are omitted.

The memory controller 3a includes an AND circuit A
D1 to AD16. AND circuit (2nd
The operation terminals of AD1, AD3, AD5, and AD7 are connected to data terminals through which the data signal D is input and output. AND circuit (first operation circuit) AD2, AD
Similarly, a data terminal is connected to the other input section of AD4, AD6, and AD8.

To one input of the AND circuit AD1, one of the inputs of the AND circuits AD2, AD9, and AD10, the chip enable terminal to which the chip enable signal CE1 is input, and the chip enable signal CEa1 are output. Chip enable terminals are respectively connected.
The AND circuit AD1 is connected to the other input of the AND circuit AD1.
2 and a data terminal for inputting and outputting the data signal Da1 are connected.

One input of the AND circuit AD3 is connected to one input of the AND circuits AD4, AD11, and AD12.
A chip enable terminal to which the chip enable signal CE2 is input and a chip enable terminal to which the chip enable signal CEa2 is output are connected. The other connection of the AND circuit AD3 is connected to the output of the AND circuit AD4, A data terminal for inputting and outputting the data signal Da2 is connected.

One input of the AND circuit AD5 is connected to one input of the AND circuits AD6, AD13, and AD14.
A chip enable terminal to which a chip enable CE3 is input and a chip enable terminal to which a chip enable signal CEa3 is output are connected. The other connection of the AND circuit AD5 is connected to the output of the AND circuit AD6 and the data terminal for inputting and outputting the data signal Da3.

One input of the AND circuit AD7 is connected to one input of the AND circuits AD8, AD15, and AD16.
A chip enable terminal to which a chip enable signal CE4 is input and a chip enable terminal to which a chip enable signal CEa4 is output are connected. The other connection of the AND circuit AD7 is connected to an output section of an AND circuit AD8, A data terminal for inputting and outputting the data signal Da4 is connected.

The other input of the AND circuit (third operation circuit) AD9 is connected to the AND circuit (third operation circuit) AD1.
1, the other connection portion of AD13 and AD15, and the address terminal to which the address signal A1 is input are connected. The other input of the AND circuit (third operation circuit) AD10 is connected to the AND circuit (third operation circuit) AD12, A
The other connection of D14 and AD16 and the address terminal to which the address signal A2 is input are connected.

An output terminal of the AND circuit AD9 is connected to an address terminal for outputting an address signal A1a.
The output of the AND circuit AD10 has an address signal A2a
Is connected. The output of the AND circuit AD11 is
An address terminal for outputting the address signal A1b is connected, and an output signal of the AND circuit AD12 is connected to the address signal A2b.

An output terminal of the AND circuit AD13 is connected to an address terminal for outputting the address signal A1c, and an output terminal of the AND circuit AD14 is connected to the address signal A.
2c is connected. An output terminal of the AND circuit AD15 is connected to an address terminal for outputting the address signal A1d, and an output terminal of the AND circuit AD16 is connected to an address terminal for outputting the address signal A2d.

A data signal D input / output from the system controller 2 is input / output to / from any of the memories 4 to 7 via the memory controller 3a as data signals Da1 to Da4, and an address signal A1 output from the system controller 2 is output. , A2 are output to any of the memories 4 to 7 as address signals A1a to A1d and A2a to A2d via the memory controller 3a.

The chip enable signals CE1 to CE4 are
The memory 4 without passing through the internal circuit of the system controller 2
To 7 are output. This chip enable signal is a signal for selecting a memory for reading and writing data from the memories 4 to 7.

The data terminal, address terminal,
And the chip enable terminals are connection terminals ST1 to S
T4 is connected to the signal terminals of the memories 4 to 7 via the conductors 12 to 21 described above.

Next, the operation of the present embodiment will be described.

First, in the memory system 1, when the chip enable signal CE1 is at the high level, the data in the memory 4 is read and written. Similarly, when the chip enable signals CE2 to CE4 are at the high level, the data in the memories 5 to 7 are read. Each is read and written.

For example, when a high-level chip enable signal CE1 is input to the memory controller 3a,
This high-level signal is input to the memory 4, and the memory 4 is activated.

The high level signal is output from the AND circuit AD.
9, and is also input to one input unit of AD10. Address signals A1, A2 output from the system controller 2
Are input to the other input units of the AND circuits AD9 and AD10, respectively, and output the operation results of the AND circuits AD9 and AD10 as address signals A1a and A2a.

In the case of data writing, the data signal D output from the system controller 2 is applied to the AND circuit A.
Since the data is input to the other input of D2, the operation result of the AND circuit AD2 is output to the memory 4 as a data signal Da1.

In the case of data reading, the data signal Da1 output from the memory 4 is input to the other input of the AND circuit AD1, and the AND circuit AD1 calculates the result of the operation of the chip enable signal CE1 and the data signal Da1. To the system controller 2 as a data signal D.

Here, the parasitic capacitance in the memory module 3 will be described with reference to FIG.

In FIG. 5, description will be made focusing on the address signal A1 when reading and writing data in the memory 4.

In the memory 4 selected by the chip enable signal CE1, the AND circuit AD9 in which the high-level chip enable signal CE1 is input to one input section is electrically conductive, and the other memories 5 to 7 are electrically connected. Connected AND circuits AD11, AD13, AD15
Is in a non-conductive state.

To transmit the address signal A 1 from the system controller 2 to the memory 4, the parasitic capacitance Cin 1 of the input circuit of the memory 4 and the ESD (Electro-
(Static Discharge) The parasitic capacitance Ces1 of the protection circuit, the parasitic capacitance Cpd1 of the signal terminal of the memory 4 and the wiring leading to it, the parasitic capacitance Cclm1 of the columnar conductor 12 connecting the memory 4 and the memory controller 3a, and the connection of the memory controller 3a The parasitic capacitance Cpdc1 between the terminal ST1 and the wiring leading to the AND circuit AD9, the parasitic capacitance Cesc1 of the ESD protection circuit in the memory controller 3a, the parasitic capacitance Cand1 of the AND circuit AD9,
The respective parasitic capacitances Cand2 to Cand4 in the AND circuits AD11, AD13, and AD15 interrupting the circuits to the unselected memories 5 to 7, and ES at the address signal A1 input of the memory controller 3a.
It suffices to charge and discharge the parasitic capacitance Cia1 of the D protection circuit.

FIG. 6 shows the configuration of the memory module 30 studied by the present inventors, and FIG. 7 shows the parasitic capacitance of the memory module 30.

In FIG. 6, the configuration is simplified for simplicity of description, and one memory controller 31
4 shows two memories 32 to 35, two address signals, and one data signal line, and lines for control signals and power supply other than the address signal and the chip enable signal are omitted.

The address signal terminals AT1 and AT2 and the data signal terminal DT provided in the memories 32 to 35 are connected to the address signal terminals ATC1 and ATC of the memory controller 31, respectively.
2. The data signal terminal DC and each are connected in parallel.

The chip enable signal is transmitted to the memories 32 to 3
5, the chip enable signal terminals CET1 to CET4 provided in the memories 32 to 35 and the chip enable signal terminals CEC1 to CEC of the memory controller 31 are control signals for selecting one memory for reading and writing data.
It is connected independently of C4.

FIG. 7 shows the parasitic capacitance in the memory module 30. In FIG. 7, the capacity of the signal path of one address signal in the address signal that must be charged and discharged is shown, and other signals are not shown, but the address signal and the data signal are the same. It is.

To output an address signal from the memory controller 31 to the memory 32, the memory controller 31
, The parasitic capacitance Cpdc between the bonding pad provided on the memory controller 31 and the wiring on the semiconductor chip reaching there, the parasitic capacitance Cpkc of the wiring of the package, the memory controller 31
Parasitic capacitance Cp of the wiring on the motherboard on which
wb, the parasitic capacitance Cst1 of the branch wiring reaching the memory 32,
Parasitic capacitance Cpk of the wiring in the package of the memory 32
1. Parasitic capacitance Cpd1, ESD of the bonding pad of the memory 32 and the wiring on the semiconductor chip connected thereto
Parasitic capacitance Ces1 of protection circuit, parasitic capacitance Ci of input circuit
n1, and the parasitic capacitances Cst2, Cpk2, Cpd2, Ces2, C
in2, Cst3, Cpk3, Cpd3, Ces3, C
in3, Cst4, Cpk4, Cpd4, Ces4, C
In4 has to be fully charged and discharged.

Therefore, at the time of reading and writing data, these parasitic capacitances must be charged and discharged. Therefore, it is difficult to increase the transfer speed of control signals and data signals, increase the power required for data transfer, and reduce power consumption. Will result in a large system.

However, in the memory module 3 shown in FIG. 4 or the like, the parasitic capacitance to be driven is greatly reduced by cutting off the memory from which data is not read or written by an AND circuit with the chip enable signal. .

Thus, according to the present embodiment, AND circuits AD1 to AD provided in memory controller 3a are provided.
With D16, the speed of the memory system 1 can be increased, and the power consumption of the memory system can be reduced.

Further, since the capacity of the wiring formed in the memory module 3 which becomes a branch wiring when viewed from the entire memory system 1 is reduced, multiple reflection of signals can be prevented, and the memory system can be stably speeded up. Can be.

Further, since a plurality of memories 4 to 7 to be connected are stacked and mounted, the size of the memory module 3 or the memory system 1 can be reduced, and the power consumption for reading data from the memories 4 to 7 can be reduced. The amount of heat to be dissipated is reduced, and the memory system 1 can be downsized.

Further, in this embodiment, the memory controller 3a and the system controller 2 are constituted by different semiconductor chips.
a and the system controller 2 are formed by one semiconductor chip (system semiconductor chip), and the memory 4 to the memory semiconductor chip
7 may be stacked to form the memory system 1.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, D
The memory module configured by the semiconductor memory including the RAM has been described.
The memory module may be a RAM (Static RAM), and may be provided in various electronic devices having a memory system such as a workstation, a server, and a portable information device in addition to a personal computer.

Further, these memory modules are not used as a main memory of an electronic device, but are used as a DRAM or an SD memory.
It may be used as a cache memory constituted by a semiconductor memory such as a RAM.

[0078]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, since the memory control means connects only the semiconductor memory selected for the chip enable signal and electrically disconnects the other semiconductor memories, the parasitic capacitance in the memory module is reduced. Can be greatly reduced.

(2) In the present invention, the memory control means reduces the wiring capacity of the memory module serving as the branch wiring, so that multiple reflection of signals can be prevented and noise and the like can be reduced. .

(3) Further, in the present invention, the memory module is constructed by stacking the control semiconductor chip as the memory control means and the semiconductor chip as the semiconductor memory, so that the memory module can be downsized. it can.

(4) According to the present invention, (1)
According to (3), the data processing speed can be increased while the memory system is downsized, and the power consumption can be reduced, so that the performance of the electronic device can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory system according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a memory module according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram of connection terminals in a memory controller provided in the memory module according to one embodiment of the present invention;

FIG. 4 is an explanatory diagram of a circuit connection configuration of the memory module according to the embodiment of the present invention;

FIG. 5 is an explanatory diagram of a parasitic capacitance in the memory module according to the embodiment of the present invention;

FIG. 6 is an explanatory diagram of a circuit connection configuration of a memory module studied by the present inventors.

FIG. 7 is an explanatory diagram of a parasitic capacitance in a memory module studied by the present inventors.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Memory system 2 System controller 3 Memory module 3a Memory controller (memory control means,
Control semiconductor chip) 3b Memory 4-7 Memory (semiconductor memory, memory semiconductor chip) 8-10 Tape Conductor 16-21 ST1-ST4 Connection terminal AD1, AD3, AD5, AD7 AND circuit (second operation Circuit) AD2, AD4, AD6, AD8 AND circuit (first operation circuit) AD9 to AD16 AND circuit (third operation circuit) 30 memory module 31 memory controller 32 to 35 memory

Claims (5)

[Claims] 1. A semiconductor device comprising: at least two semiconductor memories; and memory control means for selecting the semiconductor memories based on a chip enable signal, and inputting / outputting a control signal and a data signal only to the selected semiconductor memories. A memory module characterized by the above-mentioned. 2. The memory module according to claim 1, wherein said memory control means calculates a logical product of a corresponding chip enable signal and a write data signal, and a corresponding chip enable signal. For calculating the logical product of the read data signal and
And a third arithmetic circuit for calculating the logical product of the corresponding chip enable signal and the address signal, and the first to third arithmetic operations corresponding to the semiconductor memories selected by the chip enable signal. A memory module for outputting an operation result of a circuit. 3. The memory module according to claim 1, wherein said semiconductor memory comprises a memory semiconductor chip having a connection terminal provided on a main surface near an end of one side, and wherein said memory control means is provided. A connection terminal corresponding to a connection terminal of the memory semiconductor chip is formed of a control semiconductor chip provided on a main surface, and a back surface of the memory semiconductor chip located on a lower side is located on an upper side of the memory. The connection terminals of the memory semiconductor chip located on the upper side and overlapping with the main surface of the semiconductor chip for memory are shifted so as to protrude from the end of the semiconductor chip for memory located on the lower side, and the lamination is performed. The main surfaces of the at least two memory semiconductor chips thus formed face the main surface of the control semiconductor chip. A memory module wherein the connection terminals of the memory semiconductor chip and the connection terminals of the control semiconductor chip which are opposed to each other are connected by a columnar conductor. 4. A memory system, comprising: at least one memory module according to claim 1, and a system controller that controls an entire electronic device. 5. At least two semiconductor memories, and memory control means for selecting the semiconductor memories based on a chip enable signal and inputting / outputting a control signal and a data signal only to the selected semiconductor memories,
The semiconductor memory comprises a memory semiconductor chip having a connection terminal provided on a main surface near an end of a certain side; and the memory control means, and the system controller. A connection terminal corresponding to a connection terminal of the semiconductor chip for memory provided on the main surface;
The back surface of the lower semiconductor chip overlaps with the main surface of the upper memory semiconductor chip, and is used for connection in the upper memory semiconductor chip. Terminals are stacked so as to protrude from an end of the lower semiconductor chip, and the main surfaces of the stacked at least two memory semiconductor chips are the main surfaces of the system semiconductor chip. And a connection terminal of the semiconductor chip for memory and a connection terminal of the semiconductor chip for system which are opposed to each other are connected by a columnar conductor.