JP2001007700A - Pll circuit - Google Patents

Pll circuit

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Publication number
JP2001007700A
JP2001007700A JP11175568A JP17556899A JP2001007700A JP 2001007700 A JP2001007700 A JP 2001007700A JP 11175568 A JP11175568 A JP 11175568A JP 17556899 A JP17556899 A JP 17556899A JP 2001007700 A JP2001007700 A JP 2001007700A
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Prior art keywords
signal
frequency
oscillation
division ratio
circuit
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JP11175568A
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JP3434734B2 (en
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Hiroki Shimokawa
弘記 下川
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Nec Ic Microcomput Syst Ltd
日本電気アイシーマイコンシステム株式会社
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Abstract

PROBLEM TO BE SOLVED: To attain desired noise reduction effects, without the need for complicated adjustments, as well as a comparatively small circuit scale. SOLUTION: A PLL circuit is provided with a DIV 15, that variably frequency-divides an oscillated signal PO, so that each frequency of frequency division signals D resulting from frequency-dividing the oscillated signal PO by frequency division ratios 101, 99 is equal to frequency 1 MHz of a reference signal, R when the frequency of the oscillated signal PO is 99 MHz that is a lower limit of a frequency modulation width and 101 MHz that is an upper limit of it, a PFD 11 that compares a phase of the reference signal R with the phase of the frequency division signal D and outputs an UP signal UP or a down signal DN that is a pulse signal corresponding to them, and a dithering control section 2 that controls dithering by outputting a frequency division ratio switching control signal CC set to the frequency division ratio 99, in response to the supply of the down signal DN.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, the present invention relates to a PLL circuit for generating a clock signal with reduced electromagnetic interference (EMI) noise.

[0002]

2. Description of the Related Art In recent years, digitalization of electronic equipment has rapidly progressed, and with this, E (Electronic Equipment) caused by the operation of digital circuits has been increased.
The amount of MI noise has been increasing steadily, and its reduction has become a major problem. As a source of this kind of EMI noise, clock noise occupies the largest specific gravity. Clock noise is noise caused by a clock signal that is a reference for operation of a digital circuit. As is known, clock noise has a spectrum composed of components at odd multiples of the clock frequency. In this spectrum, as the frequency accuracy of the clock signal is improved, the spectrum width becomes narrower and the spectrum level becomes higher.

In recent years, as a method of reducing clock noise,
A clock dithering technique, which modulates the frequency of a clock signal to expand the noise spectrum width corresponding to the clock frequency to spread noise and lower the spectrum level, has attracted attention.

[0004] For example, the electronic device described in Japanese Unexamined Utility Model Publication No. 4-75469 (Reference 1), in which unnecessary radiation noise is suppressed, requires no clock signal by slightly modulating the frequency of a clock signal output from a voltage controlled oscillator. By reducing the sharpness of the spectrum of the radiation (noise) component and dispersing it, the degree of concentration on the frequency axis is reduced.

JP-A-8-125564 (Reference 2)
The radiation reduction device described includes a clock oscillation circuit having a high Q that oscillates a clock of a predetermined frequency, a modulation signal oscillation circuit that oscillates a modulation signal of a predetermined frequency, and a modulation circuit that frequency-modulates the clock with a modulation signal, By configuring the frequency of the clock oscillation output having a high Q, the desired clock dithering with a shallow modulation is performed.

[0006] A general method for generating a system clock of a predetermined frequency from a reference signal of a constant frequency is to use a phase locked loop (PLL) circuit.

[0007] The PLL circuit basically comprises three basic parts, ie, a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector has a first input for receiving a reference clock signal, and a second input for receiving a VCO output signal or a frequency-divided signal thereof (herein collectively referred to as a feedback signal for convenience of description). Also,
The feedback signal is also the input of the PLL circuit. The phase detector is
An output is connected to the loop filter section, and the loop filter section has an output connected to the VCO.

In operation, the phase detector outputs a phase detection signal proportional to the phase difference between the input signal of the reference clock signal and the input signal of the feedback signal. In response to the supply of the phase detection signal, the loop filter outputs a filter output signal that is a function of the phase detection signal. The VCO outputs an oscillation signal having a frequency proportional to the voltage (or current) of the filter output signal, that is, a VCO output signal. As described above, the VCO output signal is frequency-divided as it is or at a predetermined frequency division ratio, and is fed back to the second input of the phase detection unit as a feedback signal. This feedback signal is necessary for the VCO output signal to synchronize the phase with the reference clock signal.

Referring to FIG. 5A, which shows the operation of this general PLL (hereinafter referred to as a normal PLL) in a graph of time versus oscillation frequency, for convenience of explanation, the center of the output signal (oscillation signal) PO of the VCO is shown here. The frequency is 100 MHz, the frequency of the reference clock signal is 1 MHz, and the frequency division ratio of the feedback signal generated by dividing the oscillation signal PO is 100. As shown in the figure, in the normal PLL, the frequency of the oscillation signal PO is locked to 100 MHz because it is locked to the frequency of the oscillation signal PO. In this case, the noise component spectrum of the system clock corresponding to the oscillation signal PO is concentrated on odd harmonic components (hereinafter simply referred to as harmonic components) of 100 MHz, as schematically shown in FIG. In this figure, for convenience of explanation,
Each frequency of noise spectrum (300MHz, 500M
Hz,...) Components are collectively indicated by the frequency of the fundamental wave.

FIG. 5 is a graph showing time vs. oscillation frequency when frequency modulation of 1% of the frequency of the oscillation signal PO, that is, ± 1 MHz, is performed by the clock dithering technique.
Referring to (C), the frequency of the oscillation signal PO changes from 99 MHz to 101 MHz, centering on 100 MHz over time.
The frequency range up to Hz changes at a constant rate of change. The noise component spectrum of the system clock corresponding to the oscillation signal PO in this case is, as schematically shown in FIG. 5D as in FIG. 5B, the frequency band of the noise spectrum as compared with the oscillation signal of the normal PLL. Is from 99MHz to 101M
It covers frequencies up to Hz and the spectral level is considerably reduced. In addition, as the clock dithering width, about 1% of the frequency of the above-described oscillation signal PO is generally used.

As an example of using a PLL circuit to reduce EMI noise by clock dithering, see JP-A-9-2.
A method and apparatus for suppressing the emission of electromagnetic interference noise in a digital system described in Japanese Patent No. 89527 (Reference 3) derives a first signal having a desired average frequency from a base signal and converts the first signal into a frequency. Modulation to obtain a modulation reference signal. A clock generation circuit including a PLL circuit generates a clock based on a modulation reference signal. The radiated emissions of the modulated reference signal are spread over a first frequency band, and the radiated emissions of the clock signal are spread over a second frequency band.

A spread spectrum clock generator described in Japanese Patent Application Laid-Open No. 9-98152 (Document 4) includes an oscillator for generating a reference frequency clock signal, and a fundamental frequency and a harmonic of the fundamental frequency in cooperation with the oscillator. And a spread spectrum clock generator that generates a spread spectrum clock signal having reduced amplitude EMI spectral components. A preferred example of the spread spectrum clock generator includes a PLL circuit including a VCO and generates a series of clock pulses. A clock pulse generator for generating the clock pulse and a spread spectrum modulator for frequency-modulating the clock pulse generator to broaden the spectrum width of the EMI spectrum component and flatten the amplitude thereof. This spread spectrum modulator
A table for storing digital values, a first counter for addressing the table with different counts of the counter itself, and the PLL circuit having a control input;
A second counter for inputting the reference frequency clock signal and providing a control input to the PLL circuit, and for converting the signal from the PLL circuit and the stored digital value to the VC
Combined with the converted signal converted to the signal for controlling O,
A means for supplying this combination signal to the VCO as a control signal is provided.

[0013] In order to compare the PLL circuit described in Document 4 or the like with the present invention, a conventional PLL in which only the essential parts are taken out
Referring to FIG. 6, which shows the circuit in blocks, this conventional P
The LL circuit is a normal PLL circuit that receives the reference frequency signal R and operates so that the center frequency is phase-synchronized with the reference frequency signal R and outputs the oscillation signal PO when a modulation circuit described later does not operate. Unit 1 and a reference signal R
And a modulation circuit 3 for performing predetermined frequency modulation on the oscillation signal PO based on the frequency of the reference signal R.

The PLL unit 1 includes a reference signal R and an oscillation signal PO.
A phase comparison circuit (hereinafter, referred to as an up signal UP or a down signal DN) corresponding to the phase comparison with a frequency-divided signal D obtained by dividing the signal by a predetermined frequency division ratio. PFD) 11, a charge pump circuit (hereinafter referred to as CP) 12 for generating a charge pump signal PC which is a DC voltage signal in accordance with the supplied up signal UP / down signal DN, and a charge pump signal P
A low-pass filter (hereinafter, LPF) 13 for smoothing C, removing unnecessary high-frequency components, and outputting an oscillation control signal CO having a predetermined loop time constant;
A voltage-controlled oscillator (VCO) 14 whose frequency is controlled by the value of O and outputs an oscillation signal PO; and a variable frequency divider that divides the oscillation signal PO by a predetermined frequency division ratio and outputs a frequency-divided signal D. And a frequency divider (hereinafter referred to as DIV) 15.

The modulation circuit 3 receives the reference signal R, counts the reference signal R, and switches the division ratio of the DIV 15 in a predetermined range and a predetermined pattern when the count value reaches a predetermined number. A modulation counter 31 that supplies the signal CX to the DIV 15 is provided.

Next, the operation of the conventional PLL circuit will be described with reference to FIG. 6 and FIG. 7 which shows the waveforms of respective parts in a time chart. The PFD 11 of the PLL unit 1 comprises a reference signal R supplied from the outside and a DIV 15 Is compared with the frequency-divided signal D fed back from the controller, and if the frequency-divided signal D is delayed from the reference signal R in accordance with the comparison result, the up signal UP
On the contrary, when the frequency-divided signal D is ahead of the reference signal R, the down signal DN is output and supplied to the CP 12.
Here, the value of the up signal UP / down signal DN is represented as the number of pulses (hereinafter, the number of pulses) in a predetermined sampling period corresponding to the phase difference. That is, when the phase difference is large, the number of pulses increases, and when the phase difference decreases, the number of pulses decreases. When there is no phase difference, that is, when the phase difference is zero, the number of pulses is zero. CP1
2 is the value of the up signal UP / down signal DN, that is,
A charge pump signal PC corresponding to the number of pulses is generated and supplied to the LPF 13. The LPF 13 smoothes the charge pump signal PC, removes unnecessary high frequency components, and gives a predetermined loop time constant to output the oscillation control signal CO. The VCO 14 generates an oscillation signal PO whose frequency is controlled by the value of the oscillation control signal CO, outputs it to the outside, and supplies it to the DIV 15. When the oscillation signal PO has a predetermined center frequency, the DIV 15 divides the oscillation signal PO by a basic division ratio which is a division ratio for generating the same divided signal as the predetermined reference signal frequency, and outputs a divided signal D. Return to PFD1.

The modulation counter 31 of the modulation circuit 3 counts the supplied reference signal R, and generates a frequency division ratio switching signal CX when the count value reaches a predetermined constant number. That is, the counting of the reference signal sets a fixed period for switching the frequency division ratio.

For convenience of explanation, the numerical examples described above are again used, that is, the center frequency of the oscillation signal PO is 100 MHz, the frequency of the reference signal R is 1 MHz, and the dividing ratio of the DIV 15 is 10
0, frequency modulation (dithering frequency) width ± 1 MHz
This will be described with reference to FIG.

Referring again to FIG. 7, first, the modulation counter is not operating as an initial state, so that the frequency of the oscillation signal PO is locked to the center frequency 100 MHz,
It is assumed that the frequency division ratio of IV15 is set to 100. Therefore, the frequency of the frequency-divided signal D is 1 MHz, which is the same as the frequency of the reference signal R. Since there is no phase difference between the reference signal R and the frequency-divided signal D, the PFD 11 does not output any of the up signal UP and the down signal DN. That is, the number of pulses of the up signal UP / down signal DN is zero.

Next, at a certain time T1, a frequency division ratio switching signal CX is generated, and when the frequency division ratio is switched to 101, the frequency of the oscillation signal PO at the time of the switching is set to 100 MHz with the center frequency of 100 MHz due to the loop time constant of the PLL. Holds the locked state. On the other hand, the divided signal D is 1 MHz in the initial state.
From 100/101 = 0.9900990 MHz (hereinafter referred to as 0.99 MHz for convenience of explanation). Accordingly, the PFD 11 generates, for example, four pulses as the up signal UP and supplies the divided signal D to the CP 12 as the up signal UP. At this time, the value of the down signal DN, that is, the number of pulses is zero. Thereby, CP1
2 outputs a corresponding positive charge pump signal PC, LP
F13 raises the oscillation control signal CO in response to the supply of the positive charge pump signal PC and supplies it to the VCO14. V
The CO 14 raises the oscillation frequency according to the loop time constant in response to the rise in the voltage value of the oscillation control signal CO. When the frequency of the oscillation signal PO approaches 101 MHz, the frequency of the frequency-divided signal D also gradually approaches 1 MHz, and the phase difference from the reference signal R decreases. As a result, the value of the up signal UP, that is, the number of pulses decreases, and the rise of the charge pump signal PC and the oscillation control signal CO decreases, and finally the oscillation signal PO
At a constant voltage corresponding to 101 MHz (T2).

At this time, the frequency division ratio switching signal CX is generated again and the frequency division ratio is switched to 99. At this time, the frequency of the oscillation signal PO is locked at the center frequency 101 MHz due to the loop time constant of the PLL. Holding. On the other hand, the frequency-divided signal D ranges from 0.99 MHz to 100
/99=1.010101 MHz (hereinafter referred to as 1.01 MHz for convenience). Therefore, PFD1
In 1, the frequency-divided signal D leads the phase of the reference signal R, generates, for example, four pulses as the down signal DN, and supplies the pulse to the CP 12. At this time, the value of the up signal UP, that is, the number of pulses is zero. As a result, the CP 12 outputs the corresponding negative charge pump signal PC, and the LPF 13 responds to the supply of the negative charge pump signal PC in response to the oscillation control signal CO.
Is supplied to the VCO 14. The VCO 14 lowers the oscillation frequency in accordance with the above-mentioned loop time constant in response to a drop in the voltage value of the oscillation control signal CO. When the frequency of the oscillation signal PO approaches 99 MHz, the frequency of the frequency-divided signal D also becomes 1 M
Hz, and the phase difference from the reference signal R decreases. As a result, the value of the down signal DN, that is, the number of pulses decreases, and the charge pump signal PC and the oscillation control signal CO
Of the oscillation signal PO finally reaches 99M
Settles at a constant voltage corresponding to Hz (T3).

By repeating the above operation, desired frequency modulation, that is, dithering can be achieved.
At this time, in order to achieve the best clock noise level reduction effect as shown in FIG. 5, it is necessary to optimally set the frequency division ratio switching timing, that is, the dithering period TD.

Referring to FIG. 8 which shows an example of the influence of clock noise on the spectrum level due to inappropriate division ratio switching timing, as shown in FIG. 8 (A), when the switching timing is too early than the optimum timing. Does not reach the desired dithering frequency width, as shown in FIG. 8B, and therefore the desired noise level cannot be reduced. Conversely, as shown in FIG. 8C, when the switching timing is too late than the optimum timing,
As shown in (D), peaks occur at the noise spectrum at both ends of the dithering frequency width, in this example, 99 MHz and 101 MHz, so that a desired reduction in noise level cannot be obtained.

Therefore, in order to set the optimum division ratio switching timing, the CP 12 and the LPF 1 inside the PLL unit 1 are set.
A complicated adjustment including setting of an appropriate loop time constant by adjusting an analog circuit such as 3 and operation simulation is required.

[0025]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
The circuit has a disadvantage that the scale of an additional circuit such as a counter of a modulation circuit for setting the frequency division ratio switching timing and a control circuit associated therewith is large.

Also, since the noise level reduction effect is very sensitively affected by the appropriateness of the division ratio switching timing,
The setting of the optimum frequency division ratio switching timing has a disadvantage that complicated adjustment including setting of an appropriate loop time constant and operation simulation is required.

An object of the present invention is to provide a PLL circuit which eliminates the above-mentioned drawbacks and can achieve a desired noise reduction effect with a relatively small circuit scale and without requiring complicated adjustment.

[0028]

The PLL circuit of the present invention comprises:
By generating an oscillation signal having a predetermined clock signal frequency from a reference signal having a constant frequency and performing dithering, which is frequency modulation of a predetermined frequency width, on the oscillation signal, the noise spectrum width of the clock signal is expanded to reduce noise. In a phase locked loop (hereinafter, PLL) circuit for spreading and lowering a spectrum level, when the oscillation signal has a lower limit frequency of the frequency modulation width, the oscillation signal is transmitted to a first frequency.
When the frequency of the first frequency-divided signal divided by the frequency division ratio is equal to the frequency of the reference signal and the oscillation signal has the upper limit frequency of the frequency modulation width, the oscillation signal is divided by the second frequency division ratio. A variable frequency dividing circuit that variably divides the frequency of the divided second frequency-divided signal so as to be equal to the frequency of the reference signal; and compares the phase of the reference signal with the first or second frequency-divided signal. And a phase detection circuit that outputs an up signal or a down signal that is a pulse signal corresponding to the delay or advance of the phase of the first or second frequency-divided signal with respect to the reference signal, and supply of the up signal or the down signal. Receiving the variable frequency dividing circuit in response to the supply of the up signal.
The dithering is performed by outputting a frequency division ratio switching control signal for controlling the variable frequency dividing circuit to be set to the second frequency division ratio in response to the supply of the down signal. And a dithering control unit that controls

[0029]

Next, an embodiment of the present invention will be described with reference to FIG.
Referring to FIG. 1, which is similarly denoted by a block with common reference characters / numerals attached to common components, the PLL circuit of this embodiment shown in FIG. A common PLL circuit which receives a supply of a common reference frequency signal R to the PLL circuit of FIG. 1 and outputs an oscillation signal PO by operating the center frequency in phase synchronization with the reference frequency signal R when a modulation control unit described later does not operate. PLL unit 1
And an up signal UP or a down signal DN (hereinafter, an up signal UP / down signal DN), which are outputs of the PFD 11 described later instead of the conventional modulation circuit 3 and are pulse signals, respectively.
And a dithering control unit 2 that controls the dithering, which is a frequency modulation of a predetermined frequency bandwidth, by outputting a switching control signal CC for switching the frequency division ratio of the DIV 15.

The PLL section 1 includes a reference signal R and an oscillation signal PO.
Is compared with a divided signal D obtained by dividing the signal by a predetermined dividing ratio, and an up signal UP or a down signal DN (hereinafter referred to as an up signal UP / down signal DN), which is a pulse signal of a pulse number corresponding to the comparison result, is output. A phase comparison circuit (hereinafter referred to as PFD) 11 to be supplied to a charge pump circuit (hereinafter referred to as CP) 12 and a dithering control unit 2, and a DC voltage signal corresponding to the number of pulses of the supplied up signal UP / down signal DN. CP12 that generates a charge pump signal PC
Receiving the additional charge pump signal PS from the charge pump signal PC dithering controller 2, smoothing the charge pump signal PC and the additional charge pump signal PS to remove unnecessary high-frequency components, and setting a predetermined loop time constant. A low-pass filter (hereinafter, LPF) 13 for outputting a given oscillation control signal CO; a voltage-controlled oscillator (hereinafter, VCO) 14 whose frequency is controlled by the value of the oscillation control signal CO to output an oscillation signal PO; In response to the supply of the frequency division ratio switching signal CC from the dithering control unit 2, the basic frequency division ratio which is the frequency division ratio that generates the same frequency division signal as the predetermined reference signal frequency when the oscillation signal PO has the predetermined center frequency. A variable frequency divider (hereinafter referred to as DI) having a variable frequency division ratio that outputs a frequency divided signal D by controlling the frequency division ratio around the frequency division ratio
V) 15).

The dithering control unit 2 outputs the up signal UP
/ Latch circuit 2 that latches and temporarily holds each first pulse of down signal DN and outputs frequency division ratio switching control signal CC
1 and a charge pump circuit (CP) 22 that outputs an additional charge pump signal PS that is a DC voltage signal in accordance with the value of the division ratio switching control signal CC.

The latch circuit 21 receives an up signal UP at a first input terminal and connects a second input terminal to a NOR gate G to be described later.
A NOR gate G1 connected to the output terminal of the NOR gate G1 and outputting a frequency division ratio switching control signal CC from the output terminal; receiving the down signal DN at the second input terminal and connecting the first input terminal to the output terminal of the NOR gate G1 And a connected NOR gate G2.

The CP22 has a source connected to a power supply, a gate supplied with a frequency division ratio switching control signal CC, and outputs an additional charge pump signal PS from a drain. The transistor CP22 has a source grounded and a drain connected to a transistor. N-channel type MO having the gate connected to the drain of P21 and the gate of transistor P21, respectively.
And an S transistor N21. This CP22
, The current supply capability in the case of charge and the current sink capability in the case of discharge are PLL
It is set smaller than the driving capability of the CP 12 of the unit 1.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 showing the waveforms of the respective parts in a time chart. First, the PFD 11 of the PLL unit 1 The phase comparison with the frequency-divided signal D fed back from the DIV 15 is performed. If the frequency-divided signal D lags behind the reference signal R in accordance with the comparison result, the up signal UP
On the contrary, when the frequency-divided signal D is ahead of the reference signal R, the down signal DN is output and supplied to the CP 12 and the dithering control unit 2. Here, the value of the up signal UP / down signal DN is represented as the number of pulses (hereinafter simply referred to as the number of pulses) corresponding to the phase difference in a predetermined unit sampling period. That is, when the phase difference is large, the number of pulses increases, and when the phase difference decreases, the number of pulses decreases. When there is no phase difference, that is, when the phase difference is 0, the number of pulses is 0 in both the up signal UP and the down signal DN. This state is the so-called PLL unit 1
(Hereinafter simply referred to as a locked state).

When the up signal UP is supplied, the CP 12 determines the value of the up signal UP, that is, a predetermined reference value corresponding to the number of pulses (here, 1/2 V for convenience of explanation).
A positive charge pump signal, which is a DC voltage signal having a positive polarity with respect to DD (power supply voltage). In other words,
This operation is charging from the power supply VDD to the charge pump signal line, that is, a charging operation. Conversely, when the down signal DN is supplied, the value of the down signal DN,
That is, a negative charge pump signal, which is a DC voltage signal having a negative polarity with respect to the reference value 0 V, is generated according to the number of pulses (hereinafter, each positive / negative charge pump signal is simply referred to as a charge pump signal PC). In other words, this operation is a discharge from the charge pump signal line to the ground, that is, a discharge operation. The operation so far is the same as the operation of the conventional PLL unit.

On the other hand, the latch circuit 21 of the dithering controller 2 receives the supplied up signal UP / down signal DN.
Of the plurality of pulses, ie, the first pulse
Latch the leading edge of the pulse. For example, when the up signal UP is supplied, the first pulse is latched, and the output terminal of the NOR gate G21 becomes L level. Therefore, the frequency division ratio switching control signal CC becomes L level. Conversely, when the down signal DN is supplied, the first pulse is latched and NO
The output terminal of the R gate G22 is at the L level, and the output terminal of the NOR gate G21 is at the H level. Therefore, the frequency division ratio switching control signal CC becomes H level.

The CP22 of the dithering control section 2 outputs an additional charge pump signal PS having a value corresponding to the level of the frequency division ratio switching control signal CC. For example, when the value of the division ratio switching control signal CC is at the L level corresponding to the up signal UP, the transistor P21 of the CP22 conducts,
Since the transistor N21 is in the cutoff state, the value of the additional charge pump signal PS becomes H level close to the level of the power supply VDD. Conversely, when the value of the frequency division ratio switching control signal CC is at the H level corresponding to the down signal DN, CP22
Transistor P21 is turned off and the transistor N21 is turned on, so that the value of the additional charge pump signal PS becomes L level close to the ground level.

On the input side of the LPF 13, the charge pump signal PC and the additional charge pump signal PS are combined to form a charge pump signal PCS, which is input to the LPF 13.
The LPF 13 receives the supplied charge pump signal PCS
And outputs an oscillation control signal CO to which unnecessary high-frequency components are removed and a predetermined loop time constant is given.
Supply to O14.

The VCO 14 generates an oscillation signal PO whose frequency is controlled by the voltage value of the supplied oscillation control signal CO, and outputs the oscillation signal PO to the outside.
Supply to IV15.

The DIV 15 divides the oscillation signal PO at a division ratio switched by a division ratio switching signal CC for adding (+) and subtracting (-) a predetermined ratio around a preset basic division ratio. The divided signal D is output. That is, when the frequency division ratio switching signal CC is at L level, a predetermined ratio is added from the basic frequency division ratio, and when the frequency division ratio switching signal CC is at H level, the predetermined ratio is subtracted from the basic frequency ratio.

For convenience of explanation, the numerical example used again in the conventional example, that is, the center frequency of the oscillation signal PO is set to 100 MHz
The operation will be described using z, the frequency of the reference signal R is 1 MHz, the basic division ratio of the DIV 15 is 100, and the frequency modulation (dithering frequency) width is ± 1 MHz.

Referring again to FIG. 2, first, the dithering control unit 2 is not operating as an initial state, and therefore,
It is assumed that the frequency of the oscillation signal PO is locked at a center frequency of 100 MHz, and the division ratio of the DIV 15 is set to 100, which is the basic division ratio. Therefore, the frequency of the frequency-divided signal D is 1 MHz, which is the same as the frequency of the reference signal R. Since there is no phase difference between the reference signal R and the frequency-divided signal D, the PFD 11 does not output any of the up signal UP and the down signal DN. That is, the number of pulses of the up signal UP / down signal DN is zero.

Next, it is assumed that at a certain time T1, the oscillation signal PO drops below the center frequency and becomes, for example, 99 MHz. In this case, since the DIV 15 supplies a frequency-divided signal 0.99 MHz corresponding to the basic frequency division ratio 100 to the PFD 11, the frequency-divided signal D is delayed in phase from the reference signal R, and the PFD 11 outputs, for example, four pulses as the up signal UP. Causes
It is supplied to the CP 12 and the dithering control unit 2. At this time, no down signal DN is generated. CP 12 outputs a positive charge pump signal PC in response to the supply of up signal UP.

Latch circuit 21 of dithering control unit 2
Latches the first pulse of the up signal UP, that is, the leading edge of the first pulse, thereby setting the frequency division ratio switching control signal CC to L level.

In response to the L level of the division ratio switching control signal CC, the DIV 15 adds 1 to the basic division ratio 100 to set the division ratio to 101. As a result, the divided signal D becomes about 99
/101=0.98 MHz, that is, lower than the frequency of the reference signal R. Therefore, the PFD 11 continues to output the up signal UP and supplies the up signal UP to the CP 12 and the dithering control unit 2. Further, the latch circuit 21 of the dithering control unit 2 continues to output the L-level frequency division ratio switching control signal CC.

The CP 22 of the dithering control unit 2 responds to the supply of the L-level frequency division ratio switching control signal CC by
A corresponding positive additional charge pump signal PS is output,
It is supplied to the PF 13 and is combined with the charge pump signal PC from the CP 12 on the input side, and is input to the LPF 13 as a combined charge pump signal PCS. The LPF 13 outputs an oscillation control signal CO corresponding to the supplied charge pump signal PCS and supplies the oscillation control signal CO to the VCO 14. Since both the charge pump signal PC and the additional charge pump signal PS have a positive polarity, the combined charge pump signal PCS also has a positive polarity, and as described above, the charge pump signal PC has a higher driving capability. The oscillation control signal CO (the voltage thereof) is increased mainly in accordance with the charge pump signal PC. As the oscillation control signal CO rises, the VCO 14
The frequency of the oscillation signal PO is increased.

In this way, the frequency of the oscillation signal PO increases, and exceeds the center frequency of 100 MHz to 101 MHz.
The above operation is continued until the dead area of the nearby PFD 11 is reached. When the frequency of the oscillation signal PO reaches the dead zone of 101 MHz, the PFD 11 stops supplying the up signal UP, but the latch circuit 21 continues to hold the up signal UP and changes the frequency division ratio switching control signal CC to L. Keep holding on to the level. Therefore, the CP 22 continues to output the positive additional charge pump signal PS as before. As a result, the LPF 13 outputs the positive additional charge pump signal PS.
Further raises the oscillation control signal CO, and according to the rise of the oscillation control signal CO, the VCO 14
Increase the frequency of

As a result, the frequency of the oscillation signal PO becomes 101
When the frequency exceeds the upper limit of the dead zone in MHz, the PFD 11 starts to output the down signal DN and supplies the down signal DN to the CP 12 and the latch circuit 21 of the dithering control unit 2 (T3). CP1
2 outputs a negative charge pump signal PC in response to the supply of the down signal DN.

The latch circuit 21 latches the first pulse of the down signal DN, that is, the leading edge of the first pulse, and thereby sets the frequency division ratio switching control signal CC to the H level.

In response to the H level of the division ratio switching control signal CC, the DIV 15 subtracts 1 from the basic division ratio 100 to set the division ratio to 99. As a result, the divided signal D becomes about 10
1/99 = 1.02 MHz, that is, higher than the frequency of the reference signal R. Therefore, the PFD 11 continues to output the down signal DN, and the CP 12 and the latch circuit 21
Continue to supply. Further, the latch circuit 21 continues outputting the H-level frequency division ratio switching control signal CC.

The CP 22 of the dithering control unit 2 responds to the supply of the H-level frequency division ratio switching control signal CC by
A corresponding negative additional charge pump signal PS is output,
It is supplied to the PF 13 and is combined with the negative charge pump signal PC from the CP 12 on the input side, and is input to the LPF 13 as a negative combined charge pump signal PCS. LPF13
Outputs an oscillation control signal CO that falls in response to the supplied negative charge pump signal PCS, and supplies the oscillation control signal CO to the VCO 14. As the oscillation control signal CO falls, the VCO 14
The frequency of the oscillation signal PO is decreased.

In this way, the above operation is continued until the frequency of the oscillation signal PO falls and reaches the dead zone of the PFD 11 near the center frequency exceeding 100 MHz and 99 MHz. When the frequency of the oscillation signal PO reaches the above-mentioned dead zone of 99 MHz, the PFD 11 stops supplying the down signal DN, but the latch circuit 21 continues to hold the down signal DN and sets the frequency division ratio switching control signal CC to H level. Keep holding on to the level. Therefore, the CP 22 continues to output the negative additional charge pump signal PS as before. Accordingly, the LPF 13 further lowers the oscillation control signal CO in accordance with the negative additional charge pump signal PS, and the VCO 14 lowers the frequency of the oscillation signal PO in accordance with the decrease in the oscillation control signal CO.

As a result, the frequency of the oscillation signal PO becomes 99M.
Hz below the lower limit of the dead zone, the PFD 11
Starts outputting the up signal UP and supplies it to the CP 12 and the latch circuit 21 of the dithering control unit 2 (T4). C
P12 outputs the positive charge pump signal PC in response to the supply of the up signal UP, and outputs the oscillation signal P from the VCO 14.
The frequency of O is increased again.

By repeating the above operation, the oscillation signal PO is dithered with a desired frequency width of 99 to 101 MHz.
As a result, as described in the related art, 100 MHz
Energy of clock noise concentrated in
The spectrum is spread to 01 MHz, and the spectrum level of clock noise can be reduced.

Referring to FIG. 3 showing the operation of the present embodiment in a graph of time versus oscillation frequency and a spectrum diagram, the operating characteristics of the present embodiment vary depending on the driving capability of CP 12 and CP 22 of dithering control unit 2. 3 (A),
3B shows a graph and a spectrum diagram of time vs. oscillation frequency when the driving capability is high, and FIGS. 3C and 3D show a graph and a spectrum diagram of time vs. oscillation frequency when the driving capability is low. When the driving capability of CP12 and CP22 is high, the dithering cycle is short, and when the driving capability is low, that is, the dithering period is long. On the other hand, in each case, the spectral characteristics are almost the same,
Therefore, the noise reduction effect is almost the same, and it can be said that the switching timing is appropriate. From this, it can be said that there is little deviation from the appropriate switching timing due to the change in the driving ability of these CPs 12 and 22, that is, there is almost no influence on the noise reduction effect.

Here, for convenience of explanation, each frequency of the noise spectrum (300 MHz, 500 MHz,...)
・) The levels of the components are displayed collectively at the frequency of the fundamental wave.

As described above, in the present embodiment,
The dithering control unit outputs the up signal output from the PFD /
Since the first pulse of the down signal is latched and the latch timing of the first pulse is used as the frequency division ratio switching timing, the analog circuit such as the LPF required in the conventional PLL circuit or the frequency division ratio switching timing by simulation is used. A complicated adjustment is not required, and a circuit such as a counter for setting a timing is not required, so that the circuit scale can be reduced.

Next, referring to FIG. 4, which shows a second embodiment of the present invention in which components common to those in FIG. The difference of this embodiment from the first embodiment is that the PL
In place of the L unit 1, a PLL unit 1A from which the CP 12 is deleted is provided.

Therefore, the input signal to the LPF 13 is only the additional charge pump signal PS. As is clear from the description of the first embodiment, the driving capability of the CP 22 is LP
If F13 can be driven sufficiently, additional charge pump signal PS
Only the operation can be sufficiently performed.

In this embodiment, since the CP 12 is unnecessary, the circuit scale can be reduced as compared with the first embodiment.
That is, the required area when integrated circuits can be reduced.

[0061]

As described above, in the PLL circuit of the present invention, when the oscillation signal has the lower limit and the upper limit of the frequency modulation width, the oscillation signal is divided by the first and second division ratios, respectively. A variable frequency dividing circuit that variably divides the frequency of each of the first and second frequency-divided signals so as to be equal to the frequency of the reference signal; and a pulse signal corresponding to the phase comparison between the reference signal and the frequency-divided signal. A phase detection circuit (PFD) that outputs an up signal or a down signal, and sets a first frequency division ratio in response to the supply of the up signal, and a second frequency division ratio in response to the supply of the down signal And a dithering control unit for controlling dithering by outputting a frequency division ratio switching control signal for controlling to set the first pulse to the first pulse of the up signal / down signal output by the PFD. 1 pal Since the latch timing of which a division ratio switching timing, there is an effect that ensures optimal switching timing is obtained.

The LP required by the conventional PLL circuit is
This eliminates the need for an analog circuit such as F and complicated adjustment of the division ratio switching timing by simulation, and also eliminates the need for a circuit such as a counter for timing setting, thereby reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit according to the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the PLL circuit according to the present embodiment.

FIG. 3 is a graph of time versus oscillation frequency and a spectrum diagram illustrating an example of an operation in the PLL circuit of the present embodiment.

FIG. 4 is a block diagram illustrating a PLL circuit according to a first embodiment of the present invention.

FIG. 5 is a graph of an oscillation frequency versus time and a spectrum diagram showing an example of an operation in a normal PLL circuit.

FIG. 6 is a block diagram illustrating an example of a conventional PLL circuit.

FIG. 7 is a time chart showing an example of an operation in a conventional PLL circuit.

FIG. 8 is a graph and a spectrum diagram of an oscillation frequency with respect to time showing an example of an operation in a conventional PLL circuit.

[Explanation of symbols]

 1, 1A PLL section 2 dithering control section 3 modulation circuit 11 PFD 12, 22 CP 13 LPF 14 VCO 15 DIV 21 latch circuit 31 modulation counter G21, G22 NOR gate P21, N21 transistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 BB08 CC01 CC24 CC38 CC41 CC53 DD32 DD42 GG09 HH10 KK26 KK32 KK39 PP03 QQ08 RR18

Claims (7)

[Claims]
1. An oscillation signal of a predetermined clock signal frequency is generated from a reference signal of a constant frequency, and the oscillation signal is subjected to dithering, which is frequency modulation of a predetermined frequency width, to thereby obtain a noise spectrum width of the clock signal. In a phase locked loop (hereinafter, PLL) circuit that spreads noise and lowers the spectrum level, the oscillation signal is divided by a first division ratio when the oscillation signal has a lower limit frequency of the frequency modulation width. A second frequency-divided signal obtained by dividing the frequency of the first frequency-divided signal by a second frequency division ratio when the frequency of the first frequency-divided signal is equal to the frequency of the reference signal and the oscillation signal has the upper limit frequency of the frequency modulation width; A variable frequency dividing circuit for performing frequency division so that the frequency of the reference signal becomes equal to the frequency of the reference signal; and performing a phase comparison between the reference signal and the first or second frequency dividing signal. Receiving a supply of the up signal or the down signal, and a phase detection circuit that outputs an up signal or a down signal that is a pulse signal corresponding to the delay or advance of the phase of the first or second frequency-divided signal with respect to the reference signal; The variable frequency dividing circuit is set to the first frequency dividing ratio in response to the supply of the up signal, and the variable frequency dividing circuit is set to the second frequency dividing ratio in response to the supply of the down signal. A dithering control unit that controls the dithering by outputting a frequency division ratio switching control signal that controls the dithering.
2. The phase detection circuit that performs the phase comparison in response to the supply of the reference signal and the first or second frequency-divided signal and outputs the up signal or the down signal corresponding to the phase comparison result. A main charge pump circuit that outputs a main charge pump signal that is a DC signal for performing charging / discharging of a DC voltage corresponding to the value of the up signal or the down signal; and removing unnecessary high-frequency components of the main charge pump signal. A low-pass filter that outputs an oscillation control signal by giving a predetermined loop time constant; a voltage-controlled oscillation circuit that outputs an oscillation signal having a frequency corresponding to the voltage / current value of the oscillation control signal; Divides the oscillation signal at the first or second frequency division ratio by a frequency division ratio switching control signal supplied from the dithering control unit. Serial first or PL having the variable divider for outputting a second divided signal
The PLL circuit according to claim 1, further comprising an L unit.
3. The method according to claim 1, wherein the dithering control section controls a first signal of each of the up signal or the down signal including a plurality of pulses.
2. The PLL circuit according to claim 1, further comprising a latch circuit that captures and holds (latches) a pulse and outputs the frequency division ratio switching control signal.
4. The dithering control unit includes an additional charge pump circuit that outputs an additional charge pump signal that is a DC signal for performing charging / discharging of a DC voltage according to a level of the frequency division ratio switching control signal. The PLL circuit according to claim 1, wherein:
5. A charge pump circuit, wherein the dithering control unit outputs a charge pump signal which is a DC signal for charging / discharging a DC voltage in accordance with a level of the frequency division ratio switching control signal. The phase detection circuit that performs the phase comparison in response to the supply of the reference signal and the first or second frequency-divided signal and outputs the up signal or the down signal corresponding to the phase comparison result; A low-pass filter for removing an unnecessary high-frequency component of the charge pump signal and providing a predetermined loop time constant to output an oscillation control signal; and outputting an oscillation signal having a frequency corresponding to a voltage / current value of the oscillation control signal. A voltage-controlled oscillation circuit, a division ratio switching control signal receiving the oscillation signal and receiving the oscillation signal from the dithering control unit. PL having a variable divider which divides by the first or second division ratio to output the first or the second divided signal by
The PLL circuit according to claim 1, further comprising an L unit.
6. The latch circuit receives a supply of the up signal at a first input terminal and connects a second input terminal to a second NOR terminal to be described later.
A first NOR gate connected to an output terminal of the gate and outputting the frequency division ratio switching control signal from the output terminal; receiving the down signal at a second input terminal and connecting the first input terminal to the first NOR gate; Second NO connected to the output of the gate
The P according to claim 3, further comprising an R gate.
LL circuit.
7. An additional charge pump circuit, comprising: a first P-channel MOS transistor having a source connected to a power supply, a gate receiving the division ratio switching control signal, and outputting an additional charge pump signal from a drain; 5. The PL according to claim 4, further comprising an N-channel second MOS transistor having a source connected to ground, a drain connected to the drain of the first MOS transistor, and a gate connected to the gate of the first MOS transistor.
L circuit.
JP17556899A 1999-06-22 1999-06-22 PLL circuit Expired - Fee Related JP3434734B2 (en)

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US7113047B2 (en) 2004-06-09 2006-09-26 Fujitsu Limited Clock generator and its control method
US7413413B2 (en) 2004-07-20 2008-08-19 York International Corporation System and method to reduce acoustic noise in screw compressors
WO2009146344A1 (en) * 2008-05-30 2009-12-03 Motorola, Inc. Method and apparatus for reducing spurs in a fractional-n synthesizer
US8031015B2 (en) 2004-02-27 2011-10-04 Sanyo Electric Co., Ltd. Phase-locked loop circuit

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JP4879240B2 (en) 2008-09-16 2012-02-22 株式会社リコー Oscillation circuit, DC-DC converter, and semiconductor device
CN107612306A (en) * 2017-08-25 2018-01-19 惠科股份有限公司 Eliminate electromagnetic interference devices and methods therefor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8031015B2 (en) 2004-02-27 2011-10-04 Sanyo Electric Co., Ltd. Phase-locked loop circuit
US7113047B2 (en) 2004-06-09 2006-09-26 Fujitsu Limited Clock generator and its control method
US7413413B2 (en) 2004-07-20 2008-08-19 York International Corporation System and method to reduce acoustic noise in screw compressors
WO2009146344A1 (en) * 2008-05-30 2009-12-03 Motorola, Inc. Method and apparatus for reducing spurs in a fractional-n synthesizer
US7786772B2 (en) 2008-05-30 2010-08-31 Motorola, Inc. Method and apparatus for reducing spurs in a fractional-N synthesizer

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