JP2000357853A - Electric structure and formation method for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow easy re-working by jointing a second conductor to an uncoated surface of a first conductor mechanically and electrically, and jointing the second conductor to a second substrate mechanically and electrically. SOLUTION: Two pads 16 are provided on a surface 13 of a first substrate 12, and a first conductor 14 is formed on each of the pads 16. The first conductor 14 and an upper surface 13 are washed and roughened in a plasma processing, and the first conductor 14 and the upper surface 13 are coated with a material 18 such as photo-sensitized resin. The material 18 is irradiated with the light of appropriate wavelength using a photo-mask to form an uncoated surface 26. A second conductor 52 is mechanically and electrically connected to the surface 26 while the second conductor 52 is mechanically and electrically connected to a second substrate 42 through a pad 46, for easy re-working.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an electrical structure for reducing distortion caused by heat when soldering to a substrate and an associated manufacturing method. The first substrate can include a chip or a module. The second substrate can include a chip carrier or a circuit board. Thus, the present invention includes the coupling of chips and chip carriers, chips and circuit boards, and modules and circuit boards.

[0002]

2. Related Art A well-known method of bonding a chip to a chip carrier is to connect the chip to the chip carrier by C4 solder balls.
pse ChipConnection) method. C4 solder ball is
Coupled to pads on the chip, the C4 solder balls are connected to the chip carrier by using solder joints at solderable locations on the chip carrier. C4 solder balls have any composition known in the art and generally comprise a high lead / tin weight ratio, such as 90/10 or 97/3, of an alloy of lead and tin.
Another C4 solder ball composition is a 50/50 weight ratio lead / indium alloy.

[0003] When the above structures are heated or cooled, the solder joints are susceptible to distortion caused by differences in the coefficient of thermal expansion between the chip and the chip carrier. For example, chips typically include silicon and have a coefficient of thermal expansion ("CTE") of about 3-6 ppm / C (ppm represents parts per million). The chip carrier is generally a laminate comprising alumina or a laminate comprising organic material. The CTE of the alumina chip carrier is about 6 ppm / ° C,
CTE of organic chip carrier is about 6-24ppm / ℃
Range. The thermal stresses and consequent strains caused by CTE mismatch during thermal cycling cause solder joint fatigue failure, and consequently, loss of reliability as assessed by the number of achievable cycles to fatigue failure. May cause.

[0004] Prior art methods of reducing the effect of CTE mismatch on fatigue life are described in US Pat. No. 5,656,862, in which the space between the chip and the chip carrier is reduced by CTE.
4. Filling the material that encapsulates the interconnect structure that joins the chip to the chip carrier, including the solder balls. The encapsulation material typically has a thickness of about 2
It has a CTE of 4-40 ppm / ° C and moves the entire structure as a single composite structure during thermal cycling. Due to the high stiffness of the encapsulant, the encapsulant can absorb thermal stresses that would otherwise act at the solder joint. Materials that can be used for this purpose are approximately 10 ⁶ ps
Hysol 45121 having i rigidity. A problem with the use of encapsulants is that conditions such as contamination or crushing of the encapsulant do not allow the encapsulant to properly adhere to the interconnect structure. As a result, the encapsulant separates, exposing the interconnect structure, thereby rendering the encapsulant less capable of reducing thermal stress. Another difficulty is that the high stiffness of the encapsulant needed to effectively release the thermal stress unfortunately results in high mechanical stresses on the interconnect structure, thereby resulting in structural integrity of the interconnect structure It may weaken the sex. As the stiffness of the encapsulant decreases, the mechanical stress on the interconnect structure increases,
The ability of the encapsulant to absorb shock and vibration is increased.
Another point to consider is that the encapsulant makes it impossible to rework the structure to correct problems that occur during the life cycle of the chip-to-chip carrier structure and during the testing phase. is there.

Another prior art method of reducing the effect of CTE mismatch on fatigue life is disclosed in US Pat. No. 5,564,111.
No. 3 discloses the method. In this patent, the first
A method of bonding a chip to a substrate by fusing a truncated sphere of a solder bump with a truncated sphere of a second solder bump is disclosed. This fusion is performed after the first process and before the second process. The first process is to form a first solder bump and connect to the chip,
The surface of the first solder bump to be coated with a non-conductive resin that is liquid at room temperature before the first solder bump is cured, and this resin layer is cured to be fused with the second solder bump. And removing a part of the resin layer so as to expose the resin layer. After the first process, fusion is performed by reflowing the first solder bump and the second solder bump at a temperature at which both the first solder bump and the second solder bump melt and fuse. Next, the second solder bump is bonded to the substrate by a second process.
Unfortunately, this method is not practical for reworking the chip-substrate structure to correct problems that occur during the life cycle of the structure and during the testing phase. Rework is difficult because both the first and second solder bumps are melted by applying heat to separate the fused first and second solder bumps. When the chip and the substrate are separated, the melted solder flows out of the resin layer, leaving a partially or completely empty resin shell attached to the chip. The resulting chip configuration cannot be reworked at a practical cost, thus rendering the chip unusable.

[0006]

There is a need for a thermal stress reduction method that facilitates rework, eliminates the need for encapsulation material, or allows for the use of less rigid encapsulation material. is there.

[0007]

SUMMARY OF THE INVENTION The present invention provides a first electrical structure of a first substrate coupled to a second substrate. A first conductor is mechanically and electrically coupled to the first substrate. A portion of the surface of the first conductor is coated with a non-soldering, non-conductive coating material such that the uncoated surface remains. A second conductor is mechanically and electrically coupled to the uncoated surface of the first conductor by surface bonding. The melting point of the second conductor is lower than the melting point of the first conductor. However, the melting point is defined as the lowest temperature at which a substance melts. A second conductor is mechanically and electrically coupled to the second substrate.

The present invention provides a second electrical structure on a first substrate coupled to a second substrate. A first conductor is mechanically and electrically coupled to the first substrate. A portion of the surface of the first conductor is coated with a non-soldering, non-conductive coating material such that the uncoated surface remains.
The electrical structure also includes means for mechanically and electrically coupling the second conductor to the first conductor by surface bonding.
The coupling means also includes means for applying a temperature to the first conductor and the second conductor, the temperature being lower than the melting point of the first conductor and higher than the melting point of the second conductor. A second conductor is mechanically and electrically coupled to the second substrate.

The present invention is a method of forming an electrical structure, comprising: a first substrate; a first conductor mechanically and electrically coupled to the first substrate; Providing a first structure comprising a coating of a conductive material, wherein a portion of the surface of the first conductor is non-solderable such that an uncoated surface of the first conductor remains. Providing a second structure including a second substrate and a conductive bump mechanically and electrically coupled to the second substrate, the conductive bump being coated with a non-conductive material; Contacting the second structure with the first structure so as to contact the uncoated surface of the first conductor; and reflowing the conductive bump without melting any portion of the first conductor. Let the uncoated surface of the first conductor be Forming a second conductor overlying; cooling the first structure and the second structure to solidify the second conductor and forming a second conductor on the uncoated surface of the first conductor; Mechanically and electrically bonding the conductor to the first conductor by surface bonding.

The present invention is a method of forming a solder pillar, comprising a structure having an attachment pad, a solder body in contact with the pad, and a retractable object having a solderable surface in contact with the solder body. ), Heating the structure to a temperature above the melting point of the solder body, and forming solder columns from the solder body while soldering the solder body to both the pad and the solderable surface. Providing the pullable with the pad until the solder pillar cools, and separating the retractable from the solder pillar after the solder pillar has solidified.

The present invention has the advantage of extending the fatigue life of an electrical structure (ie, reducing the number of thermal cycles before fatigue failure occurs) by reducing the thermal strain of solder joints in the structure.

The present invention has the advantage that no encapsulant is required or the required rigidity of the encapsulant is reduced.

The present invention has the advantage that it can be easily reworked to correct problems that occur during the life cycle of the electrical structure and during the testing phase. This reworkability is to facilitate the surface adhesion between the first and second conductors by applying heat at a temperature that melts the second conductor but does not melt the first conductor. It is because it can be eliminated. The ability to rework the electrical structure without causing irreparable or costly damage also increases the practicality of directly mounting the chip on the circuit card, thereby eliminating the need for a chip carrier. Thus, the substrate of the present invention can include either a chip carrier or a circuit card.

The present invention has the advantage of providing a practical method of forming a solder pillar by forming the length and shape of the solder pillar using the movement of the retractable object.

[0015]

1 to 8 illustrate process steps according to a first preferred embodiment of the present invention. FIG. 1 shows a front sectional view of a first structure 10 having two pads 16 on an upper surface 13 of a first substrate 12. On each pad 16 is a conductor 14. Although two pads 16 and two associated first electrical conductors 14 are shown, the first structure 10 may include any number of pads 1
6 and an equal number of first conductors 14 placed on the same. The first substrate 12 can include a chip or a module. Each first conductor 14 may include a solder bump, such as a solder bump formed by a known process, such as a controlled collapsed chip connection ("C4"). If the substrate 12 includes a module, each first conductor 14 may include a ball of a ball grid array ("BGA").
Each first conductor 14 comprises a compatible solder, such as an alloy of lead and tin with a melting point of the alloy that clearly exceeds the melting point of the eutectic alloy. For example, each first conductor 14 may have a lead / tin ratio of about 327-330 ° C. and a weight ratio of 90/10 by weight. In contrast, the weight ratio is about 63
/ 37 eutectic lead / tin has a melting point of about 183 ° C.
Each first conductor 14 can have any suitable shape and size that is a property of the size and shape of the solder bumps or balls of the BGA module. For example, each first conductor 14 can be a truncated sphere having a diameter of about 0.13 mm (5 mils) and a height of about 0.10 mm (4 mils).

FIG. 1 shows a first conductor 14 and an upper surface 13 covered by a coating of a material 18. The coating of material 18 includes a non-soldering, non-conductive material such as polyimide or a photosensitive resin. One example of a compatible polyimide is DuPont PI5878 material. An example of a suitable photosensitive resin is Taiyo PSR4000-
SP50 material. The polyimide layer can be formed by any suitable method known in the art, such as spin coating or spray coating. Material 1
Prior to forming the coating of FIG. 8, the upper surface 13 and the first conductor 14 are cleaned and roughened using standard techniques such as plasma treatment, and are applied to the upper surface 13 and the first conductor 14. Material 18
Enhance the surface adhesion of the coating. Materials 1 such as polyimide
For case 8, FIG. 2 shows the result of applying radiation 32 from laser 30 to remove a portion of the coating of material 18 to form uncoated surface 20. This laser ablation (ab
The process may also remove a small amount of material (eg, about 0.0063 mm (quarter mil) high) from each first conductor 14. As an alternative to applying laser ablation, FIG. 3 illustrates that a portion of the coating of material 18 and some of the material of each first electrical conductor 14 are ground so that a flat 3 shows the result of forming an uncoated surface 22. In the case where the coating of the material 18 is a photosensitive resin, FIG.
3 shows the uncoated surface 24 formed as a result of adding light 36 of the appropriate wavelength from light source 34 to the photosensitive coating of FIG. After exposure, the photosensitive material is removed where it is not needed, i.e. the uncoated surface 24. The uncoated surface 26 of FIGS. 7 and 8 (discussed below) can be formed using the method used to form the uncoated surface 26 (eg, laser ablation, as shown in FIGS. 2, 3 and 4, respectively). Irrespective of grinding or photolithography), an uncoated surface of the first conductor 14 is shown. The uncoated surface 26 is cleaned, roughened using standard techniques such as plasma treatment to enhance subsequent surface adhesion with the conductive bumps 44, as described below with respect to FIGS. Can be

FIG. 5 shows a front sectional view of a second structure 40 having two pads 46 on an upper surface 43 of a second substrate 42. A conductive bump 44, such as a C4 eutectic solder bump in the form of a pre-cleaned solder ball, is disposed on each pad 46. Although two pads 46 and their associated two conductive bumps 44 are shown, the second structure 40 can include as many conductive bumps 44 disposed on any number of pads 46. . 1 of FIG.
If the substrate 12 includes a chip, the second substrate 42 may include a chip carrier or a circuit card. When the first substrate 12 in FIG. 1 is a module, the second substrate 4
2 may include a circuit card. The first structure and the second
Other structural combinations with this structure are also possible. The melting point of the conductive bump 44 is lower than the melting point of the first conductor 14 (see FIG. 1). For example, if the first conductor 14 is 90/1
Lead / tin alloy with a weight composition of 0 (melting point 327-330 ° C)
In this case, the conductive bumps 44 can include a eutectic 63/37 lead / tin alloy (melting point 183 ° C.), so that the difference in melting points exceeds 140 ° C. Further, the case where the conductive bump 44 includes an alloy having a composition having a melting point higher than the eutectic point is also included in the scope of the present invention. The melting point of each of the conductive bumps 44 and the associated first conductors 14 is the same as that of the common bumps in which the associated first conductors 14 remain solid at the same time that the conductive bumps 44 melt and reflow. The relationship must be such that the conductive bump 44 and its associated first conductor 14 can be heated to a temperature. The conductive bump 44 has a diameter of about 0.025 to about 1.0 mm (1 mm).
-40 mils) and any suitable shape and size, such as a truncated sphere.

FIG. 6 shows the conductive bumps 44 and the upper surface 43 covered with a coating of a material 48 such as a cured photosensitive resin. In FIG. 6, any of the methods for forming the uncoated surface of the first conductor 14, such as laser ablation, grinding, and photolithography as described above with reference to FIGS. 2, 3, and 4, respectively. The uncovered surface 49 of each conductive bump 44 can be formed. Material 4
Prior to forming the coating of 8, the upper surface 43 is cleaned and roughened using standard techniques such as plasma treatment and the material 4
8 and the upper surface 43 can be strengthened. The coating of the material 48 of FIG. 6 is optional and serves to force the conductive bump material 44 to move substantially upward as shown by arrow 50, rather than laterally, during reflow. Thus, by preventing the lateral movement of the conductive bump material 44, the coating material 48 prevents the conductive bump 44 from being lowered during reflow.

FIG. 7 shows a first structure 1 with each first conductor 14 placed on a corresponding conductive bump 44.
0 is placed on the second structure 40. The uncoated surface 26 of each first conductor 14 first covers all exposed surfaces of each first conductor 14 and then
Forming in any suitable manner known in the art, such as removing portions of the coating by methods such as laser ablation, grinding, photolithography, etc. as described above for FIG. 2, FIG. 3, or FIG. Can be. Alternatively, each first conductor 14 is only partially coated first to form an associated uncoated surface 26 such that a portion of the initial coating need not be subsequently removed. Can also. Although each conductive bump 44 is shown as uncoated, the conductive bump 44 may optionally be coated as described above in FIG.

FIG. 8 shows the completed electrical structure 60 of the process of the first preferred embodiment. This electric structure 60
Is formed as a result of reflowing the conductive bumps 44 of FIG. 7 at a temperature at which the conductive bumps 44 melt and the first conductor 14 does not melt. In practice, the reflow temperature must be high enough to reflect impurities that may be present in the conductive bumps 44 and changes in furnace temperature. For example, impurities in the conductive bumps 44 may generally increase the melting point of the conductive bumps 44 by 20 ° C. or more, and the temperature change of the furnace may be 10 ° C. to 15 ° C. Thus, if the conductive bumps 44 are made of a eutectic mixture of lead and tin, the impurity-free melting point of about 183 ° C. should be at least about 215-220 ° C., taking into account the aforementioned impurities and furnace temperature variations. This means that a reflow temperature is required. A reflow temperature of about 220 ° C. melts the first conductor 14 at 327-330 ° C. 9
It is compatible with including a 0/10 lead / tin mixture, thereby ensuring that the first conductor 14 does not melt during reflow. Note that this reflow temperature must be low enough that the coating of material 18 remains cured during the reflow process. For example, polyimide generally remains cured up to about 375 ° C, which is well above the reflow temperature of about 220 ° C in the example above. Also, the second substrate includes a fusible organic chip carrier (e.g., a substrate including glass fibers impregnated with epoxy and having a copper layer therebetween) and is therefore destroyed at temperatures as low as about 25C. In that case, reflow at a temperature as low as 220 ° C. is advantageous. In contrast, ceramic
Chip carriers are much hotter (about 13
70 ° C). After reflow, the electrical structure 60 cools, thereby solidifying the second conductor 52. In the cooled electrical structure 60, each first conductor 14 and its corresponding second conductor 52 are mechanically and electrically coupled by surface bonding at the uncoated surface 26.

FIG. 8 shows each of the reflowed conductive bumps 4.
4 shows a second conductor 52 formed by reference numeral 4. The height ΔY ₁ of the second conductor 52 in FIG. 8 is substantially equal to the height ΔY of the corresponding conductive bump 44 in FIG. The present invention maximizes ΔY ₁ to distribute the thermal shear stress and the associated strain between the first substrate 12 and the second substrate 42 that occur during thermal cycling over the highest possible height. Try to. The reflowed conductive bump material 44 has a second
There is a tendency to adhere to the material of the first conductor 14 instead of the upper surface 43 of the substrate 42. In existing techniques, ΔY ₁ is much smaller than ΔY because the reflowed conductive bump material 44 redistributes along the surface 15 of the first conductor 14. In the present invention, ΔY ₁ is not much different from ΔY, except for a slight reduction due to lateral movement of reflowed conductive bump material 44 in direction 70 by two related actions. First, the coating of the material 18 is applied to the uncoated surface 2 of the reflowed conductive bump material 44.
6 to prevent adhesion to the first conductor 14. Second
In addition, the non-solderability of the coating of material 18 prevents the reflowed conductive bump material 44 from adhering to the coating of material 18. Together, the two effects described above prevent the conductive bump material 44 from escaping from the location it occupied before reflow. Material 48 on conductive bumps 44
(See FIG. 6), the coating of material 48 serves to limit lateral movement of reflowed conductive bump material 44. This results in a larger ΔY ₁ than when there is no coating of the material 48, as described above with reference to FIG. In addition, the coating of material 18 of FIG. 8 also serves to prevent reflowed conductive bump material 44 from contacting pad 16. This is important if the conductive bump material contains tin. Tin pad 16
Includes a material such as copper, chromium, gold, etc., the ball limiting of the pad 16 near the first conductor 14.
It can have destructive effects on metallurgy (BLM). When the pad 16 receives the action of tin, the pad 16 is likely to separate from the first substrate 12. The coating of material 18 can have any thickness, such as about one-half mil, that allows the coating of material 18 to serve the aforementioned purposes. The advantage of using a coating of material 18 is even greater if the surface area of the coating of material 18 significantly exceeds the surface area of uncoated surface 26, such as at least about ten times or more.

It should be noted that each second conductor 52 is mechanically and electrically coupled to the corresponding first conductor 14 by surface adhesion at the uncoated surface 26. This feature that there is no fusion between the second conductor 52 and the corresponding first conductor 14 due to melting is that the first conductor 14 is reflowed by the corresponding conductive bump 44. Due to not melting during

FIG. 8 shows a first substrate 12 and a second substrate 4.
An optional encapsulant 5 such as anhydrous epoxy with silica filler, which can fill the space between the two
4 is also shown. The encapsulation material 54 fills the space injected by capillary action and the first conductor 14
To various surfaces including both the first and second conductors 52. The various surfaces to which the encapsulant 54 adheres can be cleaned and roughened prior to bonding using standard techniques such as plasma treatment to enhance the bond. As described above in the "Related Art" section, such encapsulants mechanically mechanically position portions of electrical structure 60 such that electrical structure 60 moves as one composite structure during thermal cycling. Join. That is, the encapsulation material 54 absorbs thermal shear stress. The effectiveness of the encapsulant 54 in reducing thermal stress increases as the stiffness of the encapsulant increases. However, the need to use encapsulant 54 increases as the separation distance between first substrate 12 and second substrate 42 increases. Second conductor 5
Increasing the separation using a height of two reduces the required stiffness of the encapsulant 54, thereby causing the first conductor 14 and the second Mechanical stress applied to the conductor 52 is reduced. In addition, reducing the stiffness of the encapsulant increases the ability of the encapsulant to absorb shock and vibration. Furthermore, if the height ΔY ₁ is high enough to maintain thermal stress in one direction at an acceptable level, it is possible to eliminate the encapsulant material 54 at all.
Thus, encapsulant 54 enhances or eliminates the role of ΔY ₁ in mitigating thermal shear stress.
As described above in the “Related Technology” section, the electrical structure 60
If it becomes necessary to correct problem 2 during the life cycle of the device and during the testing phase, the encapsulant
Is desirably omitted. Without the encapsulant 54, the electrical structure 60 can be easily reworked. In the present invention, the reworkability depends on the melting point of the first conductor 14 and the second melting point.
This is achieved by heating the electrical structure 60 to a temperature between the melting points of the respective conductors 52 and then separating the first structure 10 from the second structure 40. The first conductors 14 and the corresponding second conductors 52 are only surface bonded at the uncoated surface 26, so that the first conductors 14 correspond to the corresponding second conductors. 52, easily separated without damage. This is significantly different from the invention of U.S. Pat. No. 5,641,113 in which two solder bumps are fused as described above in the "Related Art" section. When deciding whether to use an encapsulant, the user must weigh the reworkability and the improvement in thermal stress reduction.

By forming a substantial height ΔY ₁ of the second conductor 52, the first preferred embodiment of the present invention provides for the first substrate 12 and the second substrate 42 of FIG. Parts along the structural coupling path between, especially the pads 16 and 4
6. Reduce the unit thermal shear stress and associated strain at 6. Thermal stress occurs during the thermal cycle, and the first substrate 12
Due to a CTE mismatch between the second substrate and the second substrate. As described above, the first substrate 12 can include a chip or module, and the second substrate 42 can include a chip carrier, module, or circuit card. The chip typically comprises silicon having a typical CTE of about 3-6 ppm / ° C. Alumina chip
The CTE of the carrier is about 6 ppm / ° C, and the CTE of the organic chip carrier ranges from about 6-24 ppm / ° C. Circuit cards generally have a C of about 14-22 ppm / ° C.
Has TE. To overcome the effects of CTE mismatch, ΔY ₁ needs to be at least about 50% of the height of first conductor 14 (ie, ΔY in FIG. 7). ΔY
A typical minimum value for ₁ is about 3 mils.

FIGS. 9 to 16 illustrate process steps according to a second preferred embodiment of the present invention. FIG. 9 shows that pads 116 are formed on the upper surface 113 of the first substrate 112.
A front cross-sectional view of a first structure 110 having a. A first conductor 114 is on the pad 116. The first substrate 112 can include a chip or a module. The first conductor 114 can include a solder post, such as a C4 solder post. First conductor 114
Include suitable solders, such as alloys of lead and tin, such that the melting point of the alloy is higher than the melting point of the eutectic alloy. For example,
The first conductor 114 has a melting point of about 327 to 330 ° C.
It may have a lead / tin weight ratio of 90/10.
In contrast, a eutectic lead / tin with a weight ratio of about 63/37 has a melting point of about 183 ° C. First conductor 114
Can have any suitable cylindrical shape and size. For example, first conductor 114 may have a height of about 1.3 mm to about 2.2 mm (about 50 mils to about 87 mils).
In the range of about 0.51 mm to about 0.56 mm (about 20 mils to about 22 mils). This height is significantly higher than the height of the first conductor 114 in the first embodiment of FIGS. The effect of reducing the thermal stress increases as the height of the first conductor 114 increases, but the thermal stress performance can be increased at any height exceeding the height of the standard C4 solder ball. improves. The above height / diameter ratio β of the first conductor 114
(Eg, 87/22, 50/20, etc.) are typical, but smaller or larger β values can be used. β should not be so large as to impair the ability of the first conductor 114 to withstand mechanical stress, shock, and vibration. Therefore, β
Is determined by factors such as the material of the first conductor 114, the stiffness of the encapsulation material if an encapsulation material is used, the temperature to which the first conductor 114 is exposed during its lifetime. Regarding the lower limit, if the value of β is too low,
This limits the ability of the first conductor 114 to move laterally (ie, in a direction perpendicular to its height), thus reducing its ability to reduce thermal stress. Thus, values of β of about 1 or less may be too small for some applications to be effective. The actual lower limit of β depends on the field of application, including the dependence on the material of the first conductor 114.

FIG. 9 illustrates a first conductor 114 and an upper surface 113 covered by a coating of a material 118. The coating of material 118 includes a non-solderable, non-conductive material such as polyimide or photosensitive resin. This second
The coating of material 118 of the preferred embodiment of FIGS.
Has the same properties and functions as the coating of the material 18 of the first preferred embodiment described above. Prior to forming the coating of material 118, the top surface 113 and the first conductor 114 are cleaned and roughened using standard techniques such as plasma treatment to provide a coating of the material 118 and the top surface 113 and the first surface. The surface adhesion with the conductor 114 can be enhanced.

FIG. 10 shows the result of removing a portion of the coating of material 118 to form an uncoated surface 126. The method of removing a portion of the coating of material 118 to form uncoated surface 126 includes laser ablation, grinding, and photolithography as described above with respect to FIGS. 2, 3, and 4, respectively, for the first preferred embodiment. And any other suitable method. The uncoated surface 126 can be cleaned and roughened using standard techniques to enhance subsequent surface adhesion with the conductive bump 144 as described below with respect to FIGS.

FIG. 11 shows the upper surface 14 of the second substrate 142.
3 shows a front sectional view of a second structure 140 having a pad 146 on 3. On the pads 146 are conductive bumps 144 such as C4 eutectic solder bumps in the form of pre-cleaned solder balls. Where the first substrate 112 of FIG. 9 includes a chip, the second substrate 142 may include a chip carrier or a circuit card. First substrate 11 in FIG.
If 2 is a module, the second substrate 142 can include a circuit card. The melting point of the conductive bump 144 is lower than the melting point of the first conductor 114 (see FIG. 9). For example, if the first conductor 114 has a 90/10 weight composition of lead /
When a tin alloy (melting point 327-330 ° C.) is included, the conductive bump 144 is made of a eutectic 63/37 lead / tin alloy (melting point 18
3 ° C.) so that the difference in melting points is about 15
It reaches 0 ° C. The case where the conductive bump 144 includes an alloy having a composition having a melting point higher than the eutectic point is also included in the scope of the present invention. The melting points of the conductive bumps 144 and the first conductors 114 are determined by melting the conductive bumps 144 and the first conductors 114 at the same time that the conductive bumps 144 are melted and reflowed. Must be able to be heated at a common temperature while they remain cured. The conductive bump 144 has a diameter of about 0.025 to
It can be of any suitable shape and size, such as a truncated sphere of about 1.0 mm (1-40 mils).

FIG. 12 shows a material 14 such as a cured photosensitive resin.
8 shows the conductive bumps 144 and the upper surface 143 covered by the eight coatings. In FIG. 12, the first conductor 11 is formed by laser ablation, grinding, photolithography, etc. as described above.
4 (see FIG. 9), the uncoated surface 149 of the conductive bump 144 can be formed. Material 148
Prior to forming a coating of material, the coating of material 148 and the upper surface 14
The top surface 143 can be cleaned and roughened using standard techniques such as plasma treatment to enhance surface adhesion with the third. The coating of material 148 of FIG. 12 is optional and serves to force the conductive bump material 144 to relocate substantially upward, as shown by arrow 150, rather than laterally.

FIG. 13 shows a second structure 14 having a first conductor 114 disposed on a conductive bump 144.
1 shows a first structure 110 located on the first zero. The uncoated surface 126 of the first conductor 114 first
Cover all exposed surfaces of conductor 114 of
2, 3 or 4 of the preferred embodiment of FIG.
Can be formed in any suitable manner known in the art, such as by removing portions of the coating by laser ablation, grinding, or photolithography as described above. Alternatively, first, the first conductor 114
Can be coated only partially so as to form an uncoated surface 126 so that a portion of the original coating does not need to be removed later. Although the conductive bumps 144 are shown uncoated, the conductive bumps 144 may optionally be coated according to the above description of FIG. Therefore, FIG.
FIG. 14 shows the structure of FIG.

FIG. 15 shows the electrical structure 160 after the process of the second preferred embodiment has been completed. This electric structure 1
60, the conductive bump 144 of FIG. 13 (or FIG. 14 if there is a coating of the material 148) is replaced with the conductive bump 144.
Are formed as a result of reflow at a temperature at which the first conductor 114 melts and the first conductor 114 does not melt. In practice, the reflow temperature is set according to the considerations set forth in the previous description of FIG. 8 for the first preferred embodiment.
It must be high enough to reflect any impurities that may be present in 44 and changes in furnace temperature. After the electric structure 160 is cooled after the reflow, the second conductor 1
52 solidifies. In the cooled electrical structure 160,
First conductor 114 and second conductor 152 are mechanically and electrically coupled by surface bonding at uncoated surface 126.

FIG. 15 shows a second conductor 152 formed from the reflowed conductive bump 144 of FIG. The reflowed conductive bump material 144 is applied to the first conductor 114 instead of the upper surface 143 of the second substrate 142.
It has the property of bonding to other materials. Therefore, material 118
The coating serves several purposes. The coating of material 118 removes the reflowed conductive bump material 144 except for the uncoated surface 126 so that the first conductor 114
To prevent adhesion to The non-solderability of the coating of material 118 is such that the reflowed bump material 144
8 serves to prevent adhesion to the coating. Further, the coating of material 118 may be applied to the reflowed conductive bump material 1
44 is prevented from contacting pad 116. This is shown in FIG.
This is important when the conductive bump material 144 includes tin, as described above with reference to FIG. The coating of material 118 may be about 0.
Any thickness, such as 013 mm (1/2 mil), can be used as long as the material 118 is capable of serving the above purpose. The advantage of using a coating of material 118 is that
The surface area of the coating of material 118 is the uncoated surface 12
Even larger than at least about 10 times the surface area of 6 would be even greater.

The second conductor 152 is bonded to the first conductor 11 by surface bonding on the uncoated surface 126.
Note that 4 is mechanically and electrically coupled. This feature of no melting fusion between the first conductor 152 and the first conductor 114 is due to the fact that the first conductor 114 does not melt while the conductive bump 144 is being reflowed. .

Due to the substantial height of the first conductor 114, portions along the structural coupling path between the first substrate 112 and the second substrate 142, particularly at the pads 116 and 146 of FIG. The unit thermal shear stress and its associated strain are greatly reduced. The cause of the thermal stress generated during the thermal cycle is the same as the first substrate 112 and the second substrate 14 described above with respect to the first substrate 12 and the second substrate 42 of FIG.
2 because of the CTE mismatch between the first substrate 112 and the second substrate 142. The electrical structure 160 does not depend on the height of the second conductor 152 for reducing thermal shear stress, as the effective height of the first conductor 114 causes the desired thermal stress reduction. Furthermore, the first
8 due to the effect of reducing thermal stress due to the substantial height of the conductor 114 of FIG.
Such encapsulation materials do not require thermal stress reduction.

FIG. 16 shows the first conductor 114 of FIG.
Is replaced by a tapered first conductor 115 having a side 120 in the form of a straight edge taper, forming an electrical structure 162. With the tapered shape, the first conductor 115 can be easily manufactured. The first conductor 115 can be manufactured by injection molding in which a first liquefied first conductor material is injected under pressure into a mold such as a steel mold, and then cooled and solidified. When removing the solidified first conductive material from the mold,
Due to the frictional contact between the first conductor 115 and the inner surface of the mold,
The first conductor material may be damaged. The first conductor 114 of FIG. 15 retains frictional contact until the first conductor 114 leaves the mold, so the first first conductor 115 of FIG. Conductor 114
Have a higher incidence of such damage. On the other hand,
The tapping of the tapered first conductor 115 only separates the frictional contact between the tapped first conductor 115 and the mold.

FIGS. 17 to 22 show a process for forming a solder pillar structure according to a third preferred embodiment of the present invention. By this process, the first conductor 11 shown in FIG.
A tapered or hourglass-shaped first conductor similar to 5 is formed. The first conductor formed by this process is the first conductor shown in FIGS. 9 to 10 and FIGS.
16 or the first conductor 115 in FIG. 17 to 19 and FIG.
FIGS. 0 to 22 each show an alternative way of implementing the process of the third preferred embodiment.

FIG. 17 shows a substrate 112 having a pad 116 mounted thereon and a solder body 17 in contact with the pad 116.
2 and a retractable object 174
The step of providing 0 is illustrated. Substrate 112 can include devices such as chips and modules. 9 to 10 and FIGS. 13 to 15
Of the first conductor 114 of FIG. 16 or the first conductor 11 of FIG.
5 includes a solid solder mass made of the same material as that of 5 (eg, a 90/10 weight ratio of lead / tin solder). FIG.
The retractable 174 includes a pin 180 and a non-solderable sleeve 182. Pin 180 includes a solderable surface 181 and a side 183. Non-solderable sleeve 182 surrounds pin 180 and is in contact with pin 180 at side surface 183. Retractable 174 is in contact with solder body 172 at solderable surface 181. Pin 180 may include a solderable material, such as copper, nickel, steel, and the like. Non-solderable sleeve 182 may include a non-solderable material, such as polyimide, a photoimageable epoxy material, or chrome. Pin 180 and non-solderable sleeve 182 each have a higher melting point than the melting point of solder body 172.

The heating step causes the solder body structure 2 to reach a final temperature above the melting point of the solder body 172 and below the melting points of the pins 180 and the non-soldering sleeve 182.
Heat 00. The heating step is, in particular, the solder body 20
0 can be placed in a furnace and the furnace heated. The heating melts the solder body 172, and the solder body 172 is soldered to the pins 180 at the solderable surface 181 and also to the pads 116. Non-solderable surface 182 serves to prevent molten solder from adhering to side surface 183 of pin 180. Therefore, when the side surface 183 of the pin 180 cannot be soldered,
The non-soldering sleeve 182 is unnecessary and can be omitted. For example, the pin 180 is made of a non-solderable material with a sufficiently high melting point, such as aluminum or chrome, on which a thin adhesive layer of solderable material, such as copper, including a solderable surface 181 is provided. When covered, the non-soldering sleep 182 is unnecessary.

After the heating step, the steps performed are as follows: with solder body 172 remaining soldered to both pad 116 and solderable surface 181, solder body 1
Pullable object 17 from 72 until a solder pillar is formed 17
4 in the direction of 187 from the pad 116. The resulting solder pillar 190 is shown in FIG. The speed and acceleration of the retractable 174 must be controlled so that the solder body 172 can maintain the solder connection described above. Solder pillar 19 in FIG.
The curvature of the zero tapered edge 191 is less susceptible to thermal and mechanical stress than for a straight edge tapered surface. The curvature of the tapered edge 191 of the solder post 190 is caused by surface tension at the edge 191 that pulls the molten solder at the edge 191 in a radially inward direction 198. The details of the curvature of the edge 191 include the dependence on the surface tension characteristics of the specific material used for the solder post 190, the height (H) of the solder post, and the pad 1
16, including the lateral extension of the solder pillars (D _pad ) at 16 and the lateral extension of the solder pillars at the solderable surface 181 of the pin 180 (D _pin ). . The tapered shape of the edge 191 in FIG. 18 is a result of D _pin / D _pad ≪1. In contrast, the edges of FIG. 21 described below show an hourglass-shaped edge 193 as a result of a relationship similar to D _pin ≒ D _pad . If D _pad and D _pin are constant, edge 19
The radius of curvature of 1 increases as H increases.
Therefore, when H becomes large enough, the edge 191
Approaches a straight edge similar to the surface 120 of FIG.
The attainable maximum value of H is limited by the amount of material in the solder body 172 of FIG. The ratio of D _pin / D _pad is a positive number whose upper limit is at least one. Similarly, the ratio (R) of the area of the solderable surface 181 to the area of the pad 116 is a positive number whose upper limit is at least one. The upper limit of D _pin / D _pad and the aforementioned upper limits of R and H are determined by the spacing between adjacent pads 116 on substrate 112. This is because the solder bodies 172 on adjacent pads 116 must remain isolated to be insulated. Otherwise, the electronic structures on adjacent pads 116 may be electrically shorted.

After the solder pillars 190 are formed, the cooling of the solder pillars 190 is performed by any appropriate method. Solder pillar 19
As a cooling method of 0, there is a method of transferring the solder body structure from a furnace to a cooling environment such as a room temperature environment. Another method of cooling the solder pillars 190 is to remove the solder pillars 190 from the heating source, such as by turning the furnace "off," and cool the solder pillars 190 without substantially moving them.

The final step is to pull the retractable 174 away from the solder post 190 after the solder post 190 has solidified. The detaching step mechanically pulls the retractable 174 from the solder post 190 when the temperature drops slightly below the melting temperature of the solder post 190 (eg, only about 15 ° C. below the melting temperature of the solder post 190). Can be done by The resulting solder pillar structure 220 is shown in FIG.

FIGS. 20 to 22 show the solder body structure 210.
3 shows a process of a third preferred embodiment of the present invention. 20 to 22 are similar to FIGS. 17 to 19 described above for the process of the solder body structure 200. The main structural difference is the retractable object 174 including the pin 180 of FIG.
However, in FIG. 20, the retractable object 1 including the plate 186 is shown.
76. Plate 186
Is a solderable surface 185 similar to the solderable surface 181 of the pin 180 of FIG.
84. The above surface configuration of the plate 186 covers the copper plate with the optically imageable material and (the solderable surface 18
Plate 186) (via a mask that protects each part of 5)
The surface is selectively exposed to ultraviolet light, and the unexposed photoimageable material is developed away to remove the copper coating on solderable surface 185 such that the exposed surface constitutes non-solderable surface 184. And can be formed by a standard method. Another method of forming plate 186 is to deposit a solderable material on a plate made of a high melting point non-soldering material. Many materials, such as aluminum and chrome, are suitable for the plate of non-soldering material. The solderable metal may have the solderable metal deposited by a well-known process, such as sputtering, at the location of the solderable surface 185 on a non-solderable plate including, for example, copper. The melting point of the plate 186 must be higher than the melting temperature of the solder body 172.

A distinctive feature of plate 186 is that, for a substrate having a corresponding plurality of pads 116, a single plate 18 having a plurality of solderable surfaces 185.
6 can be used. On the other hand,
In FIG. 17, a plurality of pins 180 are required for a substrate having a corresponding plurality of pads 116.

The step of heating the solder body structure 210 of FIG. 20 is similar to the step of heating the solder body structure 200 of FIG. As with the non-solderable sleeve 182 of FIG. You. The molten solder of the solder body 172 causes the solder body 172 to be soldered to the plate 186 at the solderable surface 185.

The step performed after the heating step is to remove the solder body 1 from the solder body 172 until a solder pillar is formed.
72 is to pull the retractable object 176 away from the pad 116 in the direction 188 while leaving a solder connection to both the pad 116 and the solderable surface 185. The resulting solder pillar 192 is shown in FIG. The speed and acceleration of the retractable 176 must be controlled so that the solder body 172 can maintain the solder connection described above. Hourglass-shaped edge 1 of solder pillar 192
The curvature of 93 is less susceptible to thermal and mechanical stresses than a straight edge tapered surface. Solder pillar 192
Of the hourglass edge 193 is caused by surface tension at the edge 193 that pulls the molten solder radially inwardly 199 at the edge 193 portion. The details of the curvature of the edge 193 include the solder pillar 19
2 include a dependence on the surface tension properties of the particular material used and a dependence on the relative values of the mechanical form factors described above in the description of the corresponding geometric factors with respect to FIG. Specifically, since the geometric relationship of D _plate ≒ D _pad is satisfied (see FIG. 21 for definitions of D _plate and D _pad ), the edge 193 has an hourglass shape instead of a tapered shape. The edge 191 in FIG. 18 and the edge 193 in FIG.
Respectively correspond to H, D _pad and D _pin in FIG.
Note that it can have a tapered shape (curved or straight) or an hourglass shape according to the relationship between H and D _pad and D _{plate in} FIG. D
_{The plate} / D _pad ratio is a positive number with an upper limit of at least 1 according to the analogous description of the upper limit of D _pin / D _{pad with} respect to FIG. Similarly, the ratio (R ₁ ) of the area of the solderable surface 185 to the area of the pad 116 is a positive number having an upper limit of at least one. The constraints on R ₁ and the height H of the solder pillars in FIG. 21 are the same as described above for R and H, respectively, with respect to FIG.

After the solder pillars 192 have been formed, the cooling of the solder pillars 192 is performed by any suitable method, such as the method described above for the cooling step of FIG.

After the solder pillars 192 have solidified, a final step is taken to separate the retractable 176 from the solder pillars 192. This detaching step can be performed by chemically removing any portion of the metal plate 186, including the solderable surface 185, thereby eliminating the bond between the solder post 192 and the metal plate 186. The remaining amount of metal plate 186 after chemical removal can be removed mechanically. The resulting solder column structure 230 is shown in FIG.

In summary, the following matters are disclosed regarding the configuration of the present invention.

(1) A first substrate, a first conductor mechanically and electrically coupled to the first substrate, and the first conductor so that an uncoated surface of the first conductor remains. A non-soldering non-conductive coating material, wherein a portion of the surface of the first conductor is coated with a non-soldering non-conductive material; A second conductor that is mechanically and electrically coupled to the first conductor by surface bonding and has a melting point lower than the melting point of the first conductor; and a mechanical and electrical connection to the second conductor. A second substrate coupled to the electrical structure. (2) The electric structure according to (1), wherein the first conductor includes a solder bump. (3) The electrical structure according to (2), wherein the height of the second conductor is at least about 50% of the height of the solder bump. (4) The electrical structure of (2), wherein the area of the coated surface of the first conductor is at least about 10 times the area of the uncoated surface of the first conductor. . (5) The above (1), wherein the first conductor includes a solder pillar.
An electrical structure according to claim 1. (6) The height of the solder pillar is at least about 1.3 mm.
The electrical structure of claim 5, wherein the solder pillars have a height / diameter ratio of at least about 2.5. (7) The second conductor is approximately 1% of the outer surface of the solder pillar.
The electrical structure according to (5), wherein the electrical structure covers less than 0%. (8) The electric structure according to (5), wherein the solder pillar is tapered. (9) The electric structure according to the above (5), wherein the solder pillar has a tapered shape having a curved edge. (10) The electric structure according to the above (5), wherein the solder pillar has an hourglass shape. (11) The above (1), wherein the second substrate contains an organic material.
An electrical structure according to claim 1. (12) The electrical structure according to (1), wherein the second substrate includes a ceramic material. (13) further comprising a second non-soldering non-conductive coating material, wherein a part of the surface of the second conductor is coated with the second non-soldering non-conductive coating material;
The electrical structure of (1) above, wherein the remaining uncoated surface of the second conductor is mechanically bonded to and in electrical contact with the uncoated surface of the first conductor. (14) The electrical structure according to (13), wherein the second non-soldering non-conductive coating material comprises polyimide. (15) The electric structure according to (13), wherein the second non-soldering non-conductive material includes a cured photosensitive resin. (16) a first substrate, a first conductor mechanically and electrically coupled to the first substrate, and a non-conductive non-solderable part of the surface of the first conductor. A non-soldering non-conductive coating material coated with a coating material, leaving an uncoated surface of the first electrical conductor, a second electrical conductor, and the coating of the first electrical conductor; Means for mechanically and electrically coupling said second conductor to said first conductor by surface bonding on a surface that is not in contact with said first conductor and said second conductor. An electrical structure including means for applying a temperature lower than the melting point of the first conductor and not lower than the melting point of the second conductor; and a substrate mechanically and electrically coupled to the second conductor. . (17) a first substrate, wherein a part of the surface of the first conductor is coated with a coating of a non-soldering non-conductive material so that an uncoated surface of the first conductor remains; Providing a first structure including a first conductor mechanically and electrically coupled to the first substrate, and a coating of a non-soldering, non-conductive material; Providing a second structure including a conductive bump mechanically and electrically coupled to a second substrate, wherein the conductive bump contacts the uncovered surface of the first conductor. Arranging the second structure in contact with the first structure, and reflowing the conductive bump without melting any part of the first conductor; Second conductor covering the uncoated surface of the conductor of Forming, cooling the first and second structures, solidifying the second conductor, and bonding the second conductor by surface bonding at the uncoated surface of the first conductor. Mechanically and electrically coupling said conductor to said first conductor. (18) The method according to (17), wherein the first conductor includes a solder bump. (19) The second layer formed in the reflow step
The method of claim 18, wherein the conductor has a height of at least about 2 mils. (20) further comprising a step of filling a space between the first substrate and the second substrate with an encapsulating material;
The method according to (18), wherein the encapsulating material encapsulates the first conductor and the second conductor. (21) The method according to (1), wherein the first conductor includes a solder pillar.
The method according to 7). (22) prior to the step of placing the second structure in contact with the first structure, removing a portion of the non-soldering non-conductive material coating from the first conductor; The method of claim 17, further comprising forming an exposed surface of the first conductor, wherein the uncoated surface in the placing step comprises the exposed surface. (23) The method according to (22), wherein the removing step includes a step of laser ablating a portion of the coating material from the first conductor. (24) The method according to (17), wherein the coating of the non-soldering non-conductive material comprises polyimide. (25) The method according to (17), wherein the coating of the non-soldering non-conductive material comprises a cured photosensitive resin. (26) The electrical structure of (17), wherein the non-solderable non-conductive coating material does not melt during the reflow step. (27) The method according to (17), wherein the first substrate includes a chip, and the second substrate includes an electronic carrier. (28) The first substrate includes a module, and the second substrate includes a module.
The method according to (17), wherein the substrate includes a circuit card. (29) A method for forming a solder pillar structure, comprising: a substrate having a mounted pad; a solder body in contact with the pad; and a retractable object having a solderable surface in contact with the solder body. Providing a solder body structure; heating the solder body to a temperature above the melting point of the solder body and below the melting point of the retractable object; and providing the solder body to both the pad and the solderable surface. Separating the retractable object from the pad until a solder pillar is formed from the solder body while being soldered; cooling the solder pillar; and after the solder pillar has solidified, the solder pillar Separating the retractable material from the material. (30) The method of (29) above, wherein the retractable object includes a pin in a non-solderable sleeve, and the pin includes the solderable surface. (31) The method according to (29), wherein the retractable object includes a plate having the solderable surface. (32) The above (2), wherein the area of the solderable surface is larger than 0% and smaller than about 5% of the surface area of the pad.
The method according to 9). (33) The method according to (2), wherein the area of the solderable surface is between about 95% and about 100% of the surface area of the pad.
The method according to 9).

[Brief description of the drawings]

FIG. 1 is a front sectional view showing a first structure according to a first preferred embodiment of the present invention.

FIG. 2 shows the structure of FIG. 1 after a portion of the coating of the material of the first structure has been removed by laser ablation.

FIG. 3 shows the structure of FIG. 1 after a portion of the coating of the material of the first structure has been removed by grinding.

FIG. 4 shows the structure of FIG. 1 after removing a portion of the photosensitive coating of the material of the first structure.

FIG. 5 is a front sectional view of a second structure according to the first preferred embodiment of the present invention;

6 shows the structure of FIG. 5 with a coating of material on the conductive bumps of the second structure.

FIG. 7 shows a second embodiment according to the first preferred embodiment of the present invention.
FIG. 4 is a front sectional view showing a state where the first structure is arranged on the structure of FIG.

FIG. 8 is a diagram showing the structure of FIG. 7 after reflowing the conductive bump of the second structure.

FIG. 9 is a front sectional view showing a first structure according to a second preferred embodiment of the present invention.

FIG. 10 shows the structure of FIG. 9 after removing a portion of the coating of the material of the first structure.

FIG. 11 shows a second embodiment according to the second preferred embodiment of the present invention.
It is a front sectional view showing the structure of.

FIG. 12 shows the structure of FIG. 11 with a coating of material on the conductive bumps of the second structure.

FIG. 13 is a front sectional view showing a state where a first structure is disposed on a second structure according to a second preferred embodiment of the present invention;

FIG. 14 shows the structure of FIG. 13 with a coating of material.

FIG. 15 is a view showing the structure of FIG. 13 after reflowing the conductive bump of the second structure.

FIG. 16 is a diagram showing the structure of FIG. 15 having a tapered first conductor in place of the first conductor.

FIG. 17 is a top view illustrating a solder body structure with pins according to a third preferred embodiment of the present invention.

FIG. 18 is a view showing the structure of FIG. 17 after the solder structure is heated and the pins are drawn.

FIG. 19 shows the structure of FIG. 18 after the pins have been separated.

FIG. 20 is a diagram showing the structure of FIG. 17 in which pins are replaced with plates.

21 shows the structure of FIG. 20 after the solder body structure has been heated and the plate has been drawn.

FIG. 22 shows the structure of FIG. 21 after the plate has been separated and removed.

[Explanation of symbols]

 Reference Signs List 10 first structure 12 first substrate 14 conductor 16 pad 18 coating material 42 second substrate 44 conductive bump 46 conductive pad 48 coating material 52 second conductor 54 encapsulation material 60 electrical structure 110 1 structure 112 1st substrate 114 1st conductor 115 1st conductor 116 pad 118 covering material 140 2nd structure 142 2nd substrate 144 conductive bump 146 pad 148 covering material 160 electrical structure 174 Retractable Object 176 Retractable object 180 Pin 182 Sleeve 186 Plate 192 Solder post

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Miguel Angel Himales United States 13811 Newark Valley, NY South Main Street 119 (72) Inventor Cynthia Susan Milkovich United States 13850 Vestal Castleman, NY Road 520 (72) Inventor Mark Vincent Pearson 13901 Binghamton, NY Hospital Hill Road 65

Claims (33)

[Claims] A first substrate; a first substrate mechanically and electrically coupled to the first substrate;
And a part of the surface of the first conductor is coated with a non-soldering non-conductive material so that an uncoated surface of the first conductor remains. A conductive coating material, and mechanically and electrically coupled to the first conductor by surface bonding at the uncoated surface of the first conductor, the melting point being greater than the melting point of the first conductor; An electrical structure comprising: a second conductor having a low resistance; and a second substrate mechanically and electrically coupled to the second conductor. 2. The method according to claim 1, wherein the first conductor includes a solder bump.
The electrical structure according to claim 1. 3. The electrical structure of claim 2, wherein the height of the second conductor is at least about 50% of the height of the solder bump. 4. The electricity of claim 2, wherein the area of the coated surface of the first conductor is at least about 10 times the area of the uncoated surface of the first conductor. Construction. 5. The electrical structure according to claim 1, wherein said first conductor comprises a solder post. 6. The method of claim 1, wherein the height of the solder pillar is at least about 1.3.
The electrical structure of claim 5, wherein the solder pillar has a height / diameter ratio of at least about 2.5 mm. 7. The electrical structure of claim 5, wherein said second conductor covers less than about 10% of an outer surface of said solder pillar. 8. The method according to claim 5, wherein said solder pillar is tapered.
An electrical structure according to claim 1. 9. The electrical structure of claim 5, wherein said solder pillar is tapered with curved edges. 10. The electrical structure according to claim 5, wherein said solder posts are hourglass-shaped. 11. The electrical structure according to claim 1, wherein said second substrate comprises an organic material. 12. The electrical structure according to claim 1, wherein said second substrate comprises a ceramic material. 13. A second non-soldering non-conductive coating material further comprising a second non-solderable non-conductive coating material, wherein a portion of the surface of the second conductor is coated with the second non-solderable non-conductive coating material. The electrical structure of claim 1, wherein the remaining uncoated surface of the second conductor is mechanically bonded and in electrical contact with the uncoated surface of the first conductor. 14. The electrical structure according to claim 13, wherein said second non-solderable non-conductive coating material comprises polyimide. 15. The electrical structure of claim 13, wherein said second non-solderable non-conductive material comprises a cured photosensitive resin. 16. A first substrate, and a first substrate mechanically and electrically coupled to the first substrate.
A portion of the surface of the first conductor is coated with a non-soldering non-conductive coating material, and the uncoated surface of the first conductor remains. A non-conductive coating material; a second conductor; and mechanically and electrically connecting the second conductor to the first conductor by surface bonding at the uncoated surface of the first conductor. Means for applying a temperature lower than the melting point of the first conductor and not lower than the melting point of the second conductor to the first conductor and the second conductor. An electrical structure comprising: a substrate mechanically and electrically coupled to the second conductor. 17. A first substrate, wherein a portion of the surface of the first conductor is coated with a coating of a non-soldering non-conductive material such that an uncoated surface of the first conductor remains. Providing a first structure comprising: a first conductor mechanically and electrically coupled to the first substrate; and a coating of a non-soldering non-conductive material; and a second substrate. Providing a second structure comprising: a conductive bump mechanically and electrically coupled to the second substrate; and the uncovered surface of the first conductor comprising: Disposing the second structure in contact with the first structure so as to make contact, and reflowing the conductive bump without melting any part of the first conductor; A second covering the uncoated surface of the first conductor; Forming a conductor; cooling the first structure and the second structure, solidifying the second conductor, and bonding the first conductor to the uncoated surface of the first conductor by surface bonding. Mechanically and electrically coupling said second conductor to said first conductor. 18. The method of claim 17, wherein said first conductor comprises a solder bump. 19. The method of claim 18, wherein said second conductor formed in said reflow step has a height of at least about 2 mils. 20. The method according to claim 20, further comprising the step of: filling a space between the first substrate and the second substrate with an encapsulation material, wherein the encapsulation material is provided between the first conductor and the second 19. The method of claim 18, wherein said conductor is encapsulated. 21. The method of claim 17, wherein said first conductor comprises a solder post. 22. Removing a portion of the non-soldering non-conductive material coating from the first conductor prior to the step of placing the second structure in contact with the first structure. 18. The method of claim 17, further comprising: forming an exposed surface of the first conductor, wherein the uncoated surface in the placing step comprises the exposed surface. 23. The removing step includes laser ablating a portion of a coating material from the first conductor.
23. The method according to claim 22. 24. The method of claim 17, wherein said coating of a non-solderable non-conductive material comprises polyimide. 25. The method of claim 17, wherein said coating of a non-soldering non-conductive material comprises a cured photosensitive resin. 26. The non-soldering non-conductive coating material does not melt during the reflow step.
An electrical structure according to claim 1. 27. The method of claim 17, wherein said first substrate comprises a chip and said second substrate comprises an electronic carrier. 28. The method according to claim 17, wherein said first substrate comprises a module and said second substrate comprises a circuit card. 29. A method of forming a solder pillar structure, comprising: a substrate having a mounted pad; a solder body in contact with the pad; and a retractable object having a solderable surface in contact with the solder body. Providing a solder body structure comprising: a step of heating the solder body to a temperature higher than the melting point of the solder body and lower than the melting point of the retractable object; and Removing the retractable object from the pad until a solder pillar is formed from the solder body while being soldered to both; cooling the solder pillar; and after the solder pillar has solidified, Separating said retractable material from the solder pillars. 30. The method of claim 29, wherein said retractable includes a pin in a non-soldable sleeve, said pin including said solderable surface. 31. The method according to claim 29, wherein said retractable object comprises a plate having said solderable surface. 32. The method of claim 29, wherein the area of the solderable surface is greater than 0% and less than about 5% of the surface area of the pad. 33. The method of claim 29, wherein the area of the solderable surface is between about 95% and about 100% of the surface area of the pad.