JP2000349205A - Laminated carrier board and package integrate circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen a mother board in size by a method wherein a recess is provided in the top surface of a laminated carrier board, and a capacitor is mounted in the recess. SOLUTION: A laminated carrier board 2 sandwiched in between an integrated circuit 1 and a mother board 6 is rectangular and composed of laminated boards which are each composed of a core board, a through electrode which penetrates through the core board, and exposed electrodes 20 which cover each end of the through-electrode that is exposed on the front and rear of the core board. A board 7 whose center part is cut out by laser processing is bonded to the top surface of the laminated carrier board 2, by which a recess 30 is provided in the top surface of the carrier board 2. As mentioned above, the recess 30 where a capacitor 3 is mounted is provided in the uppermost layer of the carrier board 2, so that an outside-attached capacitor can be dispensed with, where the capacitor is usually mounted direct on the mother board 6 so as to protect an integrated circuit against malfunction caused by a change in a voltage supplied to it. Therefore, a mother board can be reduced in dimensions dispensing with an outside-attached capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated carrier substrate and a package integrated circuit using the same, and more particularly, to a laminated substrate sandwiched between a motherboard and an integrated circuit mounted on the motherboard. The present invention relates to a laminated carrier substrate capable of reducing the size of a motherboard by providing a concave portion on the upper surface of a mold carrier substrate and providing a capacitor in the concave portion, and a package integrated circuit using the same.

[0002]

2. Description of the Related Art Conventionally, downsizing of electronic devices and electric devices,
With the progress of thinning, integrated circuits such as IC chips are becoming smaller and thinner. Also,
2. Description of the Related Art As integrated circuits have become smaller and more sophisticated, there has been an increasing demand for carrier substrates having high wiring density and high reliability. A general conventional carrier substrate sandwiched between a motherboard and an integrated circuit mounted thereon has a through hole penetrating the carrier substrate, and input / output terminals provided around or below the integrated circuit. Through the through hole, the integrated circuit and the motherboard are electrically connected. Further, a high-density carrier substrate manufactured by laminating a plurality of boards having holes called inner via holes and electrically connecting the holes between the respective layers as appropriate has been proposed.

In particular, in recent years, in order to reduce heat generation of an integrated circuit such as a CPU, the driving voltage of the integrated circuit is reduced to 5%.
Although it is about to be changed from V to 3.3 V, if the voltage is changed to change the driving voltage of the integrated circuit from 5 V to 3.3 V while the voltage flowing on the motherboard is kept at 5 V, a malfunction due to the voltage fluctuation will occur. May occur. Therefore, there is a movement to mount an external capacitor on a motherboard around an integrated circuit in order to solve the malfunction caused by the voltage fluctuation. Also, a power supply bypass capacitor is mounted around an integrated circuit on a motherboard.

[0004]

However, when an external capacitor or a power supply bypass capacitor is mounted in order to prevent a malfunction due to a variation in the voltage supplied to the integrated circuit, the size of the motherboard becomes large. , And miniaturization becomes difficult. Further, when the wiring pattern is routed, inductance is inevitably generated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to reduce the size of a motherboard by incorporating a capacitor in a carrier substrate.

[0006]

According to a first aspect of the present invention, there is provided a laminated carrier substrate having a motherboard having a plurality of board terminals and a plurality of input / output terminals.
It is sandwiched between the integrated circuit mounted on the motherboard,
A substrate having a plurality of through electrodes penetrating both front and back surfaces and a plurality of exposed electrodes covering the through electrodes exposed on both front and back surfaces, an exposed electrode on the top surface of the uppermost substrate and an exposed electrode on the back surface of the lowermost substrate, Are laminated in a state where they are electrically conductive, and a concave portion is provided in the center of the uppermost substrate.

A package integrated circuit according to the present invention, which solves the above-mentioned problems, comprises a motherboard having a plurality of board terminals and an integrated circuit having a plurality of input / output terminals and mounted on the motherboard. The laminated carrier substrate to be sandwiched is a substrate provided with a plurality of through electrodes penetrating both front and back surfaces and a plurality of exposed electrodes covering the through electrodes exposed on both front and back surfaces, and an exposed electrode on the surface of the uppermost substrate. A plurality of layers are laminated in a state where the exposed electrodes on the back surface of the lowermost substrate are electrically connected, and a concave portion is provided in the center of the uppermost substrate of the laminated carrier substrate, and a capacitor is provided in this concave portion. It is provided in a state of being electrically connected to the motherboard via the inside of the laminated carrier substrate.

[0008] The capacitors used in such a package integrated circuit are formed on both sides of a rectangular substrate.
A pair of external electrode layers provided on both the front and back surfaces so as to be electrically conductive, a front side first electrode layer integrally extending from the external electrode layer on the front side and one end side toward the center of the substrate, A front-side second electrode layer integrally extending from the external electrode layer on the other end side toward the substrate center, and a front-side dielectric sandwiched between the front-side first electrode layer and the front-side second electrode layer Body layers,
A backside lower electrode layer integrally extending from the backside and one end side external electrode layer toward the center of the substrate, and a backside first electrode integrally extending from the backside and one end side external electrode layer toward the center of the substrate. A second backside electrode layer integrally extending from the backside and the external electrode layer on the other end side toward the center of the substrate; and a backside first electrode layer and a backside second electrode layer. And a back side dielectric layer formed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is an oblique projection view in which each member such as an integrated circuit 1 used in the package integrated circuit according to the present invention is exploded, and FIG. 2 is an integrated circuit 1 used in the package integrated circuit according to the present invention. It is sectional drawing which decomposed | disassembled and represented each member. The laminated carrier substrate 2 sandwiched between the integrated circuit 1 and the motherboard 6 is rectangular, and as will be described in detail in a later embodiment, a core substrate 22 and the core substrate 22.
And a plurality of exposed electrodes 24 covering the through electrodes 23 exposed on both front and back surfaces of the core substrate 22.
A laminated carrier substrate according to the present invention, in which a plurality of substrates are laminated and a central portion is cut out by a laser processing method or the like to form a substrate 7 and joined to form a concave portion 30 on the upper surface. 2 can be obtained. Needless to say, the number of substrates whose central portions are cut off by a laser processing method or the like is not limited to one, and two or more substrates are laminated according to the thickness of the capacitor 3 mounted in the concave portion 30 and the depth of the concave portion 30 is determined. May be increased.

Since the laminated carrier substrate 2 needs to electrically connect the integrated circuit 1 and the capacitor 3 to the motherboard 6, as shown in FIG. 2, the exposed electrode 8 on the surface of the uppermost substrate 7 is formed. And the exposed electrode 20 on the back surface of the lowermost substrate 19 are electrically connected to each other, and are exposed on the concave portion 30 of the substrate 9 immediately below the uppermost substrate 7 (hereinafter, referred to as the immediately lower substrate 9). The exposed electrode 10 at the portion to be exposed and the exposed electrode 20 on the back surface of the lowermost substrate 19 are also electrically connected.

The shape of the recess 30 is not particularly limited.
The shape may be a circle, an ellipse, or the like, but it is preferable that the shape is the same as the shape of the capacitor 3 mounted in the recess 30 from the viewpoint of preventing useless voids in the recess 30. The integrated circuit 1 is fixed to the laminated carrier substrate 2 by solder balls 4, and similarly, the capacitor 3 is fixed to the laminated carrier substrate 2 by solder balls 4.

As described above, the carrier substrate 2 according to the present invention
The uppermost layer is provided with a concave portion 30 in which the capacitor 3 can be mounted. Therefore, in order to prevent a malfunction due to a fluctuation in the voltage supplied to the integrated circuit, the external portion directly mounted on the motherboard 6 is prevented. No additional capacitors or power supply bypass capacitors are required. Therefore, the size of the motherboard 6 can be reduced because these capacitors become unnecessary. Further, since the wiring pattern between these capacitors and the integrated circuit on the motherboard 6 is not routed, no inductance is generated.

Also, the laminated carrier substrate 2 according to the present invention.
The input / output terminals provided along the lower part and / or the periphery of the integrated circuit 1 while alleviating the impact on the motherboard 6 when the integrated circuit 1 is fixed to and mounted on the laminated carrier substrate 2 by the solder balls 4. 5 has a role of arranging them at equal intervals. Further, the laminated carrier substrate 2 has a heat radiation function, and also has a role of preventing expansion of the input / output terminals 5 due to heat from the integrated circuit 1.

Such a package type integrated circuit in which the laminated carrier substrate 2 and the capacitor 3 according to the present invention are collectively included in the spirit of the present invention. Such a package type integrated circuit is composed of a laminated carrier substrate 2
The integrated circuit 1 is mounted thereon and mounted on the motherboard 6. Of course, the packaged integrated circuit may be mounted on the motherboard 6 first, and then the integrated circuit may be mounted.

The capacitor 3 provided in the recess 30 may be a commonly used capacitor such as a wound capacitor or a multilayer capacitor. However, in order to reduce the size of the capacitor while maintaining or improving the capacity of the capacitor, Preferably, the capacitor is as follows. That is, as shown in FIG. 5, such a capacitor includes a dielectric layer on both front and back surfaces of a rectangular substrate 43 and electrode layers sandwiching the dielectric. More specifically, such a capacitor includes a pair of external electrode layers 44 to 47 on both front and back surfaces on one end side of a substrate 43, and each of the external electrode layers 44 to 47 provided on both front and back surfaces has a surface. And the back surface is electrically connected. Similarly, a pair of external electrode layers 48 to 5
1 and the external electrode layers 48 provided on both front and back sides.
To 51 are electrically connected between the front surface and the rear surface, respectively. As the substrate 43, polyimide, polyolefin, polyester, polyamide, polysulfone,
Substrates made of organic polymers such as polyether sulfone, polyphenylene oxide, polyphenylene sulfide, polycarbonate, aramid BT resin composite, and aramid epoxy composite; substrates made of inorganic compounds such as silicon and glass glaze; insulated metals (metal oxides) And the like can be used. Of these, polyimide (especially trade name "UPILEX") is a substrate made of polyimide because it is resistant to thermal expansion, has excellent moisture absorption resistance, chemical resistance, flexibility, etc. and is relatively inexpensive. Is preferred. Although the thickness of the substrate 43 is not particularly limited, the laminated carrier substrate 2 and the integrated circuit 1
In order to connect the two solder balls or the gold bumps having a thickness of about 75 μm, the distance between them is about 15 μm.
From the viewpoint that the capacitor 3 is sandwiched by this interval, it is preferably 50 μm or more and 200 μm or less, more preferably 75 μm or more and 150 μm or less. Hereinafter, for ease of explanation, a is added after the reference numeral of the external electrode layer on the front surface side, and b is added after the reference numeral of the external electrode layer on the rear surface side.

External electrode layers 44a-47a at one end of the surface
Among them, 45a, 46a, and 47a each have a front-side first electrode layer integrally extending toward the center of the substrate. A dielectric layer 52 is laminated on the front surface side first electrode layer. On the dielectric layer 52, 49a of the external electrode layers 48a to 51a on the other end side of the surface are disposed.
Surface-side second electrode layers 54, 55, and 56 electrically connected to 50a and 51a are provided. Thus, a capacitor is formed by the front-side first electrode layer, the dielectric layer 52, and the front-side second electrode layers 54 to 56. Needless to say, the front-side first electrode layer may be integrally extended from the left external electrode layer. In this case, the front-side second electrode layer is electrically connected to the right external electrode layer. become.

Similarly to the above, of the external electrode layers 44b to 47b on one end side of the back surface, the corresponding external electrode layer 44
The external electrode layer 44b in which a to 47a do not include the front-side first electrode layer includes the back-side first electrode layer integrally extending toward the center of the substrate. Further, among the external electrode layers 48b to 51b on the other end side on the back side, the external electrode layers 48a to 51a on the corresponding front side, which do not include the front side second electrode layer, are directed toward the center of the substrate. And a rear-surface-side second electrode layer 59 extending integrally. A dielectric layer 57 is sandwiched between the back-side first electrode layer and the back-side second electrode layer 59, thus forming a capacitor.

As described above, the external electrode layer, the dielectric layer, and the second electrode layer are provided on both sides of the substrate so as to be laminated on each other to form the capacitor, whereby the capacitor can be downsized. . . Such a capacitor is preferably provided in the concave portion 30 provided in the uppermost layer of the laminated carrier substrate 2 according to the present invention.
This is because, as shown in FIG. 2, a capacitor can be built in the packaged integrated circuit, and the size of the motherboard 6 can be reduced. Note that the capacitor 3 shown in FIG. 2 has a capacitor formed only on one surface of the substrate, but this is to facilitate understanding of the drawing.

In the above description, each of the front and back surfaces has two electrode layers and one dielectric layer. However, a plurality of dielectric layers may be provided so as to be sandwiched between the electrode layers. good. Further, the front side first electrode layer extending integrally from the external electrode layer 45a and the front side second electrode layer 54 corresponding thereto,
And a back side first extending integrally from the external electrode layer 48b.
As shown in the electrode layer and the corresponding back side second electrode layer 59, the capacitance may be increased by making the electrode layer L-shaped as long as it is not hindered by other electrode layers. Further, in the above description, four external electrode layers are provided at each end edge, three of which are provided with a capacitor on the front side and one with a capacitor on the back side, but the number of external electrode layers is arbitrary. Also, it is optional to provide a capacitor on any surface, and a person skilled in the art can appropriately select a capacitor according to the required capacitance and the like.

(Embodiment 1) Hereinafter, a method for manufacturing a multilayer laminated substrate will be described as an embodiment, but the following embodiment is used only for the purpose of illustration, and limits the scope of the invention described in the claims. Must not be used to (Method of Creating Laminated Carrier Substrate 2 (FIG. 3)) Preparation of Core Substrate 22 A thickness of 50 μm is formed on both sides of a 150 μm thick polyimide plate 22.
A polyethylene terephthalate film (hereinafter simply referred to as “PET film”) having a diameter of 200 μm is coated by a laser processing method using a CO ₂ laser, and the hole is filled with a conductive paste by a screen printing method. By curing, a through electrode 23 penetrating the polyimide substrate 22 was formed. Instead of the PET film, another film suitable for screen printing and capable of laser processing may be used.

The conductive paste contains 50% by weight of conductive metal powder, 40% by weight of epoxy resin, and 10% by weight of powder hardener. As the conductive metal powder, the average particle size is 3μ.
m silver powder (1% by weight), copper powder having an average particle size of 2.5 μm (6
9% by weight) Nickel powder with a central particle size of 5μm (30% by weight)
Was used. As the epoxy resin, bisphenol A (trade name “Epicoat 828”, obtained from Yuka Shell Epoxy) and a glycidyl ester-based flexible epoxy resin (tradename “Epicoat 871,” obtained from Yuka Shell Epoxy) are mixed. What was done was used. The ratio of each component of the conductive paste is not limited to this ratio,
It can be adjusted appropriately by a so-called person skilled in the art to be suitable for screen printing. The central particle size and component ratio of the conductive metal powder and each resin used when preparing the epoxy resin are not limited to those described above, and those skilled in the art can select and adjust so as to be suitable for screen printing.

Next, the PET film is peeled off from both sides of the polyimide substrate 22, and roughened copper foil having a thickness of 18 μm is attached to both sides of the polyimide substrate 22, and the temperature is 200 ° C. and the pressure is 50 kg / cm ³ for 4 hours. After performing the vacuum hot pressing, pattern etching was performed to form a core substrate 22 having exposed electrodes 24 made of copper on both sides thereof so as to cover the through electrodes 23. Note that a foil made of a conductive material can be used instead of the rough copper foil, and the thickness is not limited to 18 μm.

2. Preparation of Exterior Prepreg 25 Separately from the core substrate 22, both sides of a 150 μm thick polyimide plate 25 are coated with a 50 μm thick PET, and CO ₂
A hole having a diameter of 200 μm was formed by a laser processing method using a laser, and a conductive paste was filled into the hole by a screen printing method and cured, thereby forming a through electrode 23 penetrating the polyimide plate 25. The conductive paste is
The same conductive paste as that used for the core substrate 22 was used. Finally, a PET film is applied to the polyimide plate 2
By peeling from both surfaces of No. 5, two exterior prepregs 25 were prepared.

3. Core substrate 22 and external prepreg 25
The core substrate 2 is formed so that the exposed electrode 24 of the core substrate 22 and the through electrode 23 of the exterior prepreg 25 are electrically connected to each other.
2 is sandwiched between two exterior prepregs 25, whereby the core substrate 22 and the exterior prepreg 25 are sandwiched.
And a thickness of 1 on both sides of the exterior prepreg 25.
Attach 8μm copper foil, temperature 200 ℃, pressure 50kg
After vacuum hot pressing over 4 hours under the conditions of / cm ^3,
Exposed electrode 2 that covers the through electrode 23 by pattern etching
7 was prepared on both sides.

4. Preparation of uppermost substrate 7 and bonding with laminated substrate A substrate made of aramid epoxy composite having a thickness of 150 μm was coated on both sides with a PET film having a thickness of 50 μm, and a diameter of 200 μm was formed by a laser processing method using a CO ₂ laser.
A hole having a thickness of μm was formed, and the same conductive paste as described above was filled by a screen printing method and cured to form a through electrode. Next, the PET film was peeled off, and a 3 mm square substrate was cut from the center of the substrate by a laser processing method using a CO ₂ laser. Next, a copper foil having a thickness of 18 μm was attached to the cut surface of the substrate. This substrate is adhered to the laminated substrate as the uppermost substrate 7 and is heated in a vacuum hot press at a temperature of 200 ° C. and a pressure of 50 kg / c.
After heating and pressurizing for 4 hours under the condition of m ³ , pattern etching was performed, so that a depth of 150
A multilayer laminated carrier substrate 2 having a recess 30 of μm was prepared. In the laminated carrier substrate 2, as shown in FIG. 3, the exposed electrode 8 covering the through electrode 23 is exposed on the uppermost substrate 7, and the exposed electrode 10 is exposed in the concave portion 30.
In addition, although four layers of substrates are laminated on the above-mentioned laminated carrier substrate 2, it is needless to say that the number of core substrates 22 can be increased and more multilayer substrates can be laminated to form a laminated carrier substrate.

(Method of Making Capacitor 3 (FIG. 4)) A PET film having a thickness of 50 μm is coated on both sides of a polyimide plate 32 having a thickness of 100 μm, and a hole having a diameter of 200 μm is formed by a laser processing method using a CO ₂ laser. The conductive paste was filled by a screen printing method to form a through electrode (not shown). Thereafter, the PET film is peeled off,
A rough surface copper foil having a thickness of 18 μm is attached to both surfaces of the polyimide plate 32, and subjected to vacuum hot pressing at 200 ° C. under a pressure of 50 kg / cm ³ for 4 hours, followed by pattern etching. Next, a 10 μm-thick electrolytic copper plating is applied,
External electrode layers 11 to 18 are formed on both surfaces of the polyimide plate 32 by applying a 3 μm-thick nickel plating on the copper plating by electroless plating and further applying a 0.2 μm-thick electroless gold plating on the nickel plating. did.
These external electrode layers 11 to 18 are electrically connected between the front and back surfaces by through electrodes (not shown). The material of the external electrode layer is not limited to copper, nickel, and gold, and a conductive material such as chromium, silver, and platinum may be used. Those skilled in the art can also appropriately adjust the thickness of the external electrode layers 11 to 18.

Next, the polyimide plate 32 and each external electrode layer 1
Since a step due to plating is formed between the external electrode layers 1 to 18, an insulating polyimide resin 33 is applied to the vicinity of each of the external electrode layers 11 to 18 by a screen printing method in order to reduce the step. Curing was carried out for 1 hour under the condition of ° C. Next, a metal mask having a thickness of 0.2 mm is attached, aluminum is deposited by high frequency sputtering in a vacuum (1.0 × 10 ⁻³ Torr or less), and the external electrode layers 15 to 18 on one end side (left side in FIG. The lower electrode layers 34 to 37 having a thickness of 0.3 μm and electrically connected to the substrate were formed on one surface of the polyimide plate 32. Note that a metal mask is used for vapor deposition, but a mask made of a heat-resistant material or the like may be used instead. In addition, a polyimide resin is used as an insulating material to fill a step between each of the external electrode layers 11 to 18 and the polyimide plate 32. Instead of this, a thermosetting resin having heat resistance, an insulating inorganic compound Or the like may be used. The curing conditions (such as a temperature of 300 ° C.) are not limited to those described above, and it goes without saying that the curing temperature varies depending on the material.

Remove the metal mask and add another 0.2mm thick
Attach a metal mask of^-3To
rr or less) as shown in FIG.
So that it is provided in the center of the polyimide plate 32 in a strip shape.
0.3 μm stacked on the lower electrode layers 34 to 37.
m dielectric layer 38 of strontium titanate.
Done. After this, remove the metal mask and set the thickness to 0.2mm
Attach another metal mask of lower electrode layers 34 to 37
Was formed in a vacuum (1.0 × 10 ^-3Torr or less
Aluminum is deposited by high frequency sputtering in bottom)
The external electrode layers 11 on the other end side (right side in FIG.
0.3 μm thick upper electrode layer electrically connected to
39 to 42 were formed. As shown in FIG.
These upper electrode layers 39 to 42 are laminated on the dielectric layer 38.
Have been. Thus, the lower electrode layers 34 to 37,
The conductor layer 38 and the upper electrode layers 39 to 42 are made of polyimide.
By providing on the surface of the plate 32, the polyimide plate 32
Forming four capacitor elements on the surface,
It was created. Note that the opposing surface of each of these capacitor elements
Product (the area where the lower electrode layer and the upper electrode layer overlap)
0.6mm in total^TwoMet.

When the characteristics such as the capacitance of the capacitor 3 thus manufactured were measured, the dielectric constant of the dielectric layer 38 made of strontium titanate was 30 for each capacitor element, and the static electricity was 30. Electric capacity is 5
30 pF, dielectric loss tangent (tan δ) was 0.84, and insulation resistance was 1 × 10 ¹¹ Ω or more.

(Joining of Laminated Carrier Substrate 2 and Capacitor 3) The laminated carrier substrate 2 formed as described above has a thickness of about 100 μm in the recess 150 of 150 μm depth.
Was mounted, and the external electrode layers 11 to 18 formed on the back surface of the capacitor 3 and the exposed electrodes 10 were connected to form a package integrated circuit. Thereafter, the exposed electrodes 8 on the uppermost substrate 7 of the laminated carrier substrate 2 and the integrated circuit 1
And the input / output terminal 5 were connected. The exposed electrode 20 on the back surface of the laminated carrier substrate 2 and the board terminal 2 on the motherboard 6
1 was mounted on the motherboard 6 by mounting the package integrated circuit on which the integrated circuit 1 was mounted. Since the capacitor 3 is sandwiched between the laminated carrier substrate 2 and the integrated circuit 1, the number of capacitors directly mounted on the motherboard 6 can be reduced, and the size of the motherboard 6 can be reduced.

(Embodiment 2) (Method of manufacturing capacitor 3 (FIG. 5)) Example 1 was performed except that the capacitor 3 manufactured as follows was used.
A package integrated circuit was prepared in the same manner as described above. Note that the same laminated carrier substrate 2 as that described in Example 1 was used as the laminated carrier substrate 2.

1. Preparation The chromium having a thickness of 3 nm is sputtered on a polyimide substrate 43 having a thickness of 50 μm by a sputtering method, and then the copper having a thickness of 1 μm is deposited by an EB evaporation method in a vacuum (1.0 × 10 ⁻³ Torr or less). A 7 μm-thick electrolytic copper plating is applied, and a hole having a diameter of 0.4 mm is formed at a predetermined position near both ends of the polyimide plate 43. A 10 μm-thick copper through-hole plating is applied to the inner wall of the hole and the entire surface of the polyimide plate. gave.

2. Preparation of Each External Electrode Layer Both sides of this polyimide plate 43 are etched in an individual pattern, nickel plating is applied thereon by electroless plating to a thickness of 4 μm, and electroless gold plating is applied thereon to a thickness of 0.2 μm. Thereby, external electrode layers 44 to 51 having a predetermined shape were formed on the polyimide plate 43. These external electrode layers 44 to 51 also function as lower electrode layers. More specifically, among the external electrode layers 44a to 47a on one end side (the left side in FIG. 4A) of the surface, the external electrode layer 4
Etching and plating are carried out on a polyimide plate 43 so that 5a is L-shaped, and the external electrode layers 46a and 47a are rectangular, and are provided with a front-side first electrode layer integrally extending toward the center of the substrate. It was created by applying it to the surface. The external electrode layer 44 on one end of the surface
a and external electrode layer 4 on the other end of the surface (right side in FIG. 4a)
Nos. 8a to 51a do not have such an extended front-side first electrode layer, but were prepared by etching and plating. On the other hand, among the external electrode layers 48b to 51b on the other end side (the left side in FIG. 4B) of the back surface, the external electrode layer 48b extends integrally toward the substrate center so as to form an L-shape occupying most of the center of the substrate. It was prepared by performing etching and plating on the back surface of the polyimide plate 43 so as to include the exposed back side first electrode layer. Note that, as above,
Other external electrode layers 44b-47b, 49b-
51b is not provided with such an extended front surface side first electrode layer, but was formed by etching and plating.

3. Preparation of Dielectric Layer and Upper Electrode Layer on Front Side Next, a metal mask having a thickness of 0.2 mm is attached to the surface of the polyimide plate 43, and is placed in a vacuum (1.0 × 10 ⁻³ Torr or less).
The dielectric layer 52 made of dimethylol tricyclodecane diacrylate (hereinafter, referred to as “DCPA”) having a thickness of 0.3 μm is formed by EB vapor deposition on the external electrode layers 45 a to 47 a.
Laminated on top. Remove the metal mask and remove the external electrode layer 45
a and the external electrode layer 49a, between the external electrode layer 46a and the external electrode layer 50a, and between the external electrode layer 47a and the external electrode layer 51a. At 30 ° C. for 30 minutes. Then, another metal mask having a thickness of 0.2 mm is attached, aluminum is evaporated on the dielectric layer 52 by EB evaporation in a vacuum (1.0 × 10 ⁻³ Torr or less), and the external electrode layers 49 to 51 are respectively formed. Upper electrode layers 54, 55, and 56 having a thickness of 0.3 μm and electrically conducting were formed. Thus, the external electrode layers 44 to 51, the dielectric layer 52, and the upper electrode layers 54 to 56 are
Thus, three capacitor elements were formed on the surface of the polyimide plate 43.

4. Preparation of Dielectric Layer and Upper Electrode Layer on Back Side Next, a metal mask having a thickness of 0.2 mm is attached to the back side of the polyimide plate 43, and the thickness is reduced to 0.1 mm by EB vapor deposition in a vacuum (1.0 × 10 ⁻³ Torr or less). A dielectric layer 57 made of 3 μm DCPA was laminated on the external electrode layer 48b. After removing the metal mask, the external electrode layer 44b and the external electrode layer 48 are removed.
b, a polyimide resin 58 was applied by screen printing and cured at a temperature of 350 ° C. for 30 minutes.
Then, attach another metal mask with a thickness of 0.2mm,
Aluminum is deposited on the dielectric layer 57 by EB deposition in a vacuum (1.0 × 10 ⁻³ Torr or less), and the external electrode layer 44 is deposited.
An upper electrode layer 59 having a thickness of 0.3 μm which is electrically connected to the upper electrode layer 59 was formed. Thus, by providing the external electrode layer 48, the dielectric layer 57, and the upper electrode layer 59 on the back surface of the polyimide plate 43, a capacitor element was formed on the back surface of the polyimide plate 43, and the capacitor 3 was formed.

The external electrode layer 44b and the external electrode layer 48b, the external electrode layer 45a and the external electrode layer 49a, the external electrode layer 46a and the external electrode layer 50a, and the external electrode layer 47a and the external electrode layer 47a The facing areas of the capacitors formed with the layer 51a are 3.75 mm ² and 1.44, respectively.
mm ² , 0.6 mm ² , and 0.3 mm ² .

When the characteristics such as the capacitance of the capacitor 3 formed as described above were measured, the dielectric constant of the dielectric layers 52 and 57 made of DCPA was 3, and the external electrode layer 44b and the upper electrode layer 59 were formed. Has a capacitance of 330 pF and a dielectric loss tangent (tan).
δ) was 0.73, and the insulation resistance value was 1 × 10 ¹¹ or more. The capacitance of the capacitor element formed by the external electrode layer 45a and the upper electrode layer 54 is 128 pF, the dielectric loss tangent (tan δ) is 0.81, and the insulation resistance value is 1 ×.
It was 10 ¹¹ or more. External electrode layer 46a and upper electrode layer 5
5 has a capacitance of 53
The pF, the dielectric loss tangent (tan δ) was 0.84, and the insulation resistance value was 1 × 10 ¹¹ or more. The capacitance of the capacitor element formed by the external electrode layer 47a and the upper electrode layer 56 was 27 pF, the dielectric loss tangent (tan δ) was 0.89, and the insulation resistance was 1 × 10 ¹¹ or more.

(Joining of Laminated Carrier Substrate 2 and Capacitor 3) The capacitor 3 having a thickness of about 50 μm prepared as described above is connected to the laminated carrier substrate 2 at a depth of 150 μm.
m, and the external electrode layers 11 to 18 formed on the back surface of the capacitor 3 and the exposed electrodes 10 were connected to form a package integrated circuit. Thereafter, the exposed electrodes 8 on the uppermost substrate 7 of the stacked carrier substrate 2 were connected to the input / output terminals 5 of the integrated circuit 1. The exposed electrode 20 on the back surface of the laminated carrier substrate 2 and the board terminal 21 on the motherboard 6
Thus, the package integrated circuit on which the integrated circuit 1 was mounted was mounted on the motherboard 6. Since the capacitor 3 is sandwiched between the laminated carrier substrate 2 and the integrated circuit 1, the number of capacitors directly mounted on the motherboard 6 can be reduced, and the size of the motherboard 6 can be reduced.

In this embodiment, the dielectric layer is formed by depositing strontium titanate and dimethylol tricyclodecane diacrylate. However, other means for forming the dielectric layer include polyimide, polyurea, Polyamide, polyurethane, means for evaporating or vapor-depositing an organic compound such as polyparaxylene, means for evaporating an inorganic compound such as barium titanate, and the like, and not only evaporation, but also sputtering, a printing method, and the like. May be used. Further, the degree of vacuum at the time of performing the sputtering and the EB evaporation is set to 1.0 × 10 ⁻³ Torr or less, but the degree of the vacuum is not limited provided that the sputtering and the EB evaporation can be performed.

In this embodiment, a method of manufacturing a capacitor having a single dielectric layer has been described. However, the number of dielectric layers and each electrode layer is increased by sandwiching the dielectric layer between the external electrode layer and the upper electrode layer. As a result, a capacitor having desired characteristics such as electric capacity can be obtained. Further, the capacitor 3 mounted in the concave portion 30 of the multilayer carrier substrate 2
Is not limited to one, and a plurality of capacitors may be mounted in the concave portion 30 as long as the concave portion 30 and the exposed electrodes 10 exposed in the concave portion 30 have a margin.

[0041]

As described above, according to the present invention, the concave recess 30 is provided on the upper surface of the laminated carrier substrate 2 sandwiched between the motherboard 6 and the integrated circuit 1 mounted on the motherboard 6. The provision of the capacitor 3 in the recess 30 allows the motherboard 6 to be reduced in size, the multilayer carrier substrate 2 and such a capacitor 3, and the package integration in which the multilayer carrier substrate and the capacitor are integrated. A circuit is provided.

[Brief description of the drawings]

FIG. 1 is an oblique projection view in which members such as an integrated circuit 1 used in a package integrated circuit according to the present invention are disassembled.

FIG. 2 is an exploded cross-sectional view of members such as an integrated circuit 1 used in a package integrated circuit according to the present invention.

FIG. 3 is a cross-sectional view of the laminated carrier substrate 2.

FIG. 4A is a plan view of the capacitor 3 manufactured in Example 1, and FIG. 4B is a bottom view of the capacitor 3;

FIG. 5 is a plan view of the capacitor 3 formed in Example 2, and FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Integrated circuit 2 ... Laminated type carrier board 3 ... Capacitor 4 ... Solder ball 5 ... Input / output terminal 6 ... Motherboard 7 ... Top layer board 8 ... Exposed electrode 9 ... Immediate lower layer board 10 ... Exposed electrode 11-18 ... External electrode Layer 20 ... Exposed electrode 21 ... Board terminal 22 ... Core substrate (polyimide plate) 23 ... Through electrode 24, 27 ... Exposed electrode 25 ... Prepreg (polyimide plate) 30 ... Recess 32 ... Polyimide plate 33 ... Polyimide resin 34-37 ... Bottom Electrode layer 38 Dielectric layer 39-42 Upper electrode layer 43 Substrate (polyimide plate) 44-47 External electrode layer 48-51 External electrode layer 53 Polyimide resin 54-56 Front surface side second electrode layer ( Upper electrode layer) 52, 57: Dielectric layer 59: Backside second electrode layer (upper electrode layer)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Atsushi Katsube 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor Takanori Sugimoto 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A plurality of through-holes penetrating both front and back surfaces between a motherboard having a plurality of board terminals and an integrated circuit having a plurality of input / output terminals and mounted on the motherboard. A substrate provided with electrodes and a plurality of exposed electrodes covering the through electrodes exposed on both the front and back surfaces, in a state where the exposed electrodes on the surface of the uppermost substrate and the exposed electrodes on the back surface of the lowermost substrate are electrically connected. 2. The laminated carrier substrate according to claim 1, wherein a concave portion is provided at a center of an upper surface of the laminated carrier substrate. 2. A laminated carrier substrate having a plurality of board terminals and a plurality of input / output terminals and being sandwiched between an integrated circuit mounted on the motherboard, the laminated carrier substrate having both front and back surfaces. A substrate having a plurality of through electrodes penetrating through and a plurality of exposed electrodes covering the through electrodes exposed on both the front and back surfaces, an exposed electrode on the surface of the uppermost substrate and an exposed electrode on the back surface of the lowermost substrate. A plurality of layers are laminated in an electrically conductive state, and a concave portion is provided in the center of the uppermost substrate of the laminated carrier substrate, and a capacitor is provided in the concave portion through the laminated carrier substrate. A package integrated circuit that is mounted in electrical communication with the motherboard. 3. A pair of external electrode layers provided on both front and back surfaces of the rectangular substrate so as to be electrically conductive at both side edges of the rectangular substrate; A surface-side first electrode layer integrally extending toward the substrate; a surface-side second electrode layer integrally extending from the surface and the other end-side external electrode layer toward the substrate center; and the surface-side first electrode. A surface-side dielectric layer sandwiched between the layer and the surface-side second electrode layer; and a rear-surface-side first electrode layer integrally extending from the rear surface and one end-side external electrode layer toward the substrate center. A back side second electrode layer integrally extending from the back side and the external electrode layer on the other end side toward the center of the substrate; and between the back side first electrode layer and the back side second electrode layer. The capacitor according to claim 2, wherein the capacitor comprises a backside dielectric layer sandwiched therebetween. Package integrated circuit.