JP2000323620A - Semiconductor mounting board and manufacture thereof, and method of mounting semiconductor chip - Google Patents

Semiconductor mounting board and manufacture thereof, and method of mounting semiconductor chip

Info

Publication number
JP2000323620A
JP2000323620A JP11130654A JP13065499A JP2000323620A JP 2000323620 A JP2000323620 A JP 2000323620A JP 11130654 A JP11130654 A JP 11130654A JP 13065499 A JP13065499 A JP 13065499A JP 2000323620 A JP2000323620 A JP 2000323620A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
conductor
resin layer
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11130654A
Other languages
Japanese (ja)
Inventor
Takeshi Hozumi
猛 八月朔日
Hidetaka Hara
英貴 原
Hitoshi Aoki
仁 青木
Kensuke Nakamura
謙介 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP11130654A priority Critical patent/JP2000323620A/en
Publication of JP2000323620A publication Critical patent/JP2000323620A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

PROBLEM TO BE SOLVED: To manufacture and provide at low cost a semiconductor mounting board having functions of low electric resistance with a semiconductor chip and high mechanical connection, and further, to obtain a method of mounting semiconductor chip easy in processing and excellent in productivity. SOLUTION: A thermosetting insulation resin layer 16 softened by heating and reveals its adhesive property is formed on the surface of the side on which a semiconductor chip is equipped. At the same time, an independent conductive terminal 18 is formed on the part of the surface in which an electrode of the semiconductor chip is connected to a conductive wiring 12 of a wiring board. When packaging the semiconductor chip, the thermosetting insulation resin layer 16 is heated and softened, and the conductive terminal 18 is embedded and passed through the resin layer by pressing. Thus, the electrode of the semiconductor chip is connected to the conductive wiring 12.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップをフ
リップチップ接続により搭載する半導体搭載用基板、及
びその製造方法、さらには半導体チップの実装方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate for mounting a semiconductor chip by flip-chip connection, a method of manufacturing the same, and a method of mounting a semiconductor chip.

【0002】[0002]

【従来の技術】近年の電子機器の高機能化並びに軽薄短
小化の要求に伴い、電子部品の高密度集積化、さらには
高密度実装化が進んできており、これらの電子機器に使
用される半導体パッケージは、従来にも増して益々小型
化かつ多ピン化が進んできている。
2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages have been increasingly miniaturized and have more pins than ever before.

【0003】半導体パッケージはその小型化に伴って、
従来のようなリードフレームを使用した形態のパッケー
ジでは、小型化に限界がきているため、最近では回路基
板上にチップを実装したものとして、BGA(Ball
Grid Array)やCSP(Chip Sca
le Package)と言った、エリア実装型の新し
いパッケージ方式が提案されている。これらの半導体パ
ッケージにおいて、半導体チップの電極と従来型半導体
パッケージのリードフレームの機能とを有する、半導体
搭載用基板と呼ばれるプラスチックやセラミックス等各
種絶縁材料と、導体配線で構成される基板の端子との電
気的接続方法として、ワイヤーボンディング方式やTA
B(Tape Automated Bonding)
方式、さらにはFC(Frip Chip)方式などが
知られているが、最近では、半導体パッケージの小型化
に有利な、FC接続方式を用いたBGAやCSPの構造
が盛んに提案されている。
[0003] With the miniaturization of semiconductor packages,
In a package using a conventional lead frame, the miniaturization has reached its limit. Recently, a BGA (Ball (Ball)) has been used in which a chip is mounted on a circuit board.
Grid Array) and CSP (Chip Sca)
le Package), a new area mounting type packaging system has been proposed. In these semiconductor packages, various insulating materials such as plastics and ceramics, which are called semiconductor mounting substrates, having electrodes of a semiconductor chip and a function of a lead frame of a conventional semiconductor package, and terminals of a substrate composed of conductive wiring are provided. Electrical connection methods include wire bonding and TA.
B (Tape Automated Bonding)
A method, and furthermore, an FC (Flip Chip) method and the like are known. Recently, BGA and CSP structures using an FC connection method, which are advantageous for miniaturization of a semiconductor package, have been actively proposed.

【0004】このFC接続方式は一般に、半導体チップ
の電極にあらかじめ、電気メッキ法により接続用バンプ
を形成しておき、このバンプと基板上の端子を位置合わ
せして、熱圧着により接続するが、半導体チップの電極
にバンプを形成する工程が複雑で、バンプ製造コストが
掛かり、また、バンプ接続部分の耐湿信頼性を得るた
め、チップと基板との間隙に、アンダーフィルと呼ばれ
る絶縁樹脂を充填してバンプ接続部分を封止する必要が
あり、このアンダーフィルを充填し硬化させる工程が必
要となるため、製造工程が複雑で製造コストが高くなる
問題がある。
In this FC connection method, generally, connection bumps are formed on electrodes of a semiconductor chip in advance by electroplating, and the bumps and terminals on the substrate are aligned and connected by thermocompression bonding. The process of forming bumps on the electrodes of a semiconductor chip is complicated, the manufacturing cost of the bumps is high, and the gap between the chip and the substrate is filled with an insulating resin called underfill in order to obtain the moisture-proof reliability of the bump connection. It is necessary to seal the bump connection portion, and a step of filling and curing the underfill is required. Therefore, there is a problem that the manufacturing process is complicated and the manufacturing cost is increased.

【0005】そこで、アンダーフィルに代わり、半導体
チップと基板を電気的に接続しかつ機械的に接着する接
続材料として、異方導電シートを使用する方法が着目さ
れ検討されている。この異方導電シートには接着性が付
与されており、通常では、先に基板上に異方導電シート
を貼り合わせてから、半導体チップを搭載し、電気的接
続と機械的接続を同時に行なう。このような異方導電シ
ート方式は、半導体パッケージの小型化や低コスト化に
有効な手段として益々注目されてきており、以下のよう
な異方導電シートが提案されている。
Therefore, instead of underfill, a method of using an anisotropic conductive sheet as a connection material for electrically connecting and mechanically bonding a semiconductor chip and a substrate has been focused on and studied. The anisotropic conductive sheet is provided with an adhesive property. Usually, the anisotropic conductive sheet is pasted on a substrate, and then a semiconductor chip is mounted, and electrical connection and mechanical connection are simultaneously performed. Such an anisotropic conductive sheet system has been increasingly attracting attention as an effective means for reducing the size and cost of semiconductor packages, and the following anisotropic conductive sheet has been proposed.

【0006】図3は、従来より提案されている、異方導
電シートによる半導体チップ実装法の代表例を示す断面
図である。異方導電シート33は、熱可塑性や熱硬化性
の樹脂中に、導電性の微粒子35を分散させたものであ
る。熱圧着時に樹脂が流動して、接続端子である半導体
チップ31の電極34と半導体搭載用基板32の導体配
線との間に挟まれた、導電性の微粒子35によって厚さ
方向の電気的接続を得るもので、液晶ディスプレイパネ
ルとTCP(Tape Carrier Packag
e)の電気的接続などに使用されている。このような構
造の異方導電シートは、樹脂に導電性微粒子を分散させ
ると言う比較的簡単な工程で製造できることと、基板に
貼り合わせる際の位置合わせが比較的ラフに行えること
を特徴としている。しかしながら、電気的接続を、半導
体チップの電極と基板の端子との間に確率的に存在する
導電性微粒子によって得ているため、狭ピッチになるに
従い、導電性微粒子をより微小にし、より多く分散させ
ることが必要になる。これによって微粒子密度が高まる
結果、微粒子間距離が狭まり電気的絶縁性が低下する問
題と、微粒子と電極及び端子との接続面積が小さくなり
接続抵抗が上昇する問題、さらには微粒子コストの上昇
の問題などが生じる。
FIG. 3 is a cross-sectional view showing a typical example of a conventionally proposed semiconductor chip mounting method using an anisotropic conductive sheet. The anisotropic conductive sheet 33 is obtained by dispersing conductive fine particles 35 in a thermoplastic or thermosetting resin. The resin flows at the time of thermocompression bonding, and the electrical connection in the thickness direction is performed by the conductive fine particles 35 sandwiched between the electrodes 34 of the semiconductor chip 31 serving as connection terminals and the conductor wiring of the semiconductor mounting substrate 32. LCD panel and TCP (Tape Carrier Package)
e) is used for electrical connection and the like. The anisotropic conductive sheet having such a structure is characterized in that it can be manufactured by a relatively simple process of dispersing conductive fine particles in a resin, and that the alignment when bonding to a substrate can be performed relatively roughly. . However, since the electrical connection is obtained by the conductive fine particles that are stochastically present between the electrodes of the semiconductor chip and the terminals of the substrate, the conductive fine particles are made finer and more dispersed as the pitch becomes narrower. It is necessary to make it. As a result, the particle density is increased. As a result, the distance between the particles is reduced and the electrical insulation is reduced. The connection area between the particles and the electrode and the terminal is reduced to increase the connection resistance. And so on.

【0007】また最近では、図4に示されるような例が
提案されている。半導体チップにバンプを形成すること
なく、半導体チップと基板が電気的に接続しかつ機械的
に接着された半導体搭載基板である。表面に接着層46
を有する樹脂フィルム43にドリルやレーザによって微
小な貫通穴を明け、その後メッキや導電性ペースト印刷
などの方法により、貫通穴内部を導電体45で充填した
構造を有する。熱圧着時に接着層46が流動し、半導体
チップ41と半導体搭載用基板32を接着すると共に、
接続端子である半導体チップ41の電極44と半導体搭
載用基板の導体配線47との間に挟まれた部位の導電体
45によって、電気的接続を得るものである。このよう
な構造は、半導体チップの電極および基板の端子と導電
体が相対して配列されるので、電気的接続性に優れ、か
つ隣接する導電体部分における電気的絶縁性にも優れる
ことを特徴としている。
Recently, an example as shown in FIG. 4 has been proposed. A semiconductor mounting substrate in which a semiconductor chip and a substrate are electrically connected and mechanically bonded without forming a bump on the semiconductor chip. Adhesive layer 46 on the surface
The resin film 43 has a structure in which a minute through hole is made by a drill or a laser, and then the inside of the through hole is filled with a conductor 45 by a method such as plating or conductive paste printing. At the time of thermocompression bonding, the adhesive layer 46 flows to bond the semiconductor chip 41 and the semiconductor mounting substrate 32,
The electrical connection is obtained by the conductor 45 at a portion sandwiched between the electrode 44 of the semiconductor chip 41 as a connection terminal and the conductor wiring 47 of the semiconductor mounting substrate. Such a structure is characterized in that since the electrodes of the semiconductor chip and the terminals of the substrate and the conductor are arranged facing each other, the electrical connection is excellent and the electrical insulation between adjacent conductors is also excellent. And

【0008】しかしながら、高位置精度での微小な穴あ
け加工が要求されるため、レーザによる穴明け加工が必
要となり、レーザの欠点である低生産性及び高ランニン
グコストにより製造コストが高くなる問題がある。ま
た、微小穴への導電体形成は通常メッキで行なわれる
が、穴径が小さくなるほど均一なメッキが難しく、導電
体の高さにバラツキを生じ易く、接続時に電気的接続が
出来ないといった品質低下の問題がある。
However, since fine drilling with high positional accuracy is required, drilling with a laser is required, and there is a problem that the production cost is increased due to the low productivity and high running cost, which are the drawbacks of the laser. . In addition, although the formation of a conductor in a minute hole is usually performed by plating, as the hole diameter becomes smaller, uniform plating becomes more difficult, the height of the conductor tends to vary, and the quality is deteriorated such that electrical connection cannot be performed at the time of connection. There is a problem.

【0009】[0009]

【発明が解決しようとする課題】本発明は、従来のメッ
キバンプや異方導電シートにより、半導体チップと基板
とを電気的かつ機械的に接続する方法が有する、上記の
ような種々の問題点に鑑み、鋭意研究をした結果なされ
たものであり、半導体チップとの低い電気的抵抗及び強
い機械的接続の機能を有する半導体搭載用基板を、低コ
ストで製造提供することができ、さらに、容易で生産性
に優れた半導体チップの実装方法を提供することを目的
とする。
DISCLOSURE OF THE INVENTION The present invention has been made in view of the above-mentioned various problems that the conventional method for electrically and mechanically connecting a semiconductor chip and a substrate by plating bumps or anisotropic conductive sheets has. In view of the above, it has been made as a result of earnest research, and it is possible to manufacture and provide a semiconductor mounting substrate having a function of low electric resistance and strong mechanical connection with a semiconductor chip at low cost, and furthermore, It is an object of the present invention to provide a semiconductor chip mounting method excellent in productivity.

【0010】[0010]

【課題を解決するための手段】即ち本発明は、半導体チ
ップを搭載するための半導体搭載用配線基板であって、
半導体チップを搭載する側の面に、加熱によって軟化し
接着性を発現する熱硬化性絶縁樹脂層を形成すると共
に、該熱硬化性絶縁樹脂層表面の、半導体チップの電極
と配線基板の導体配線とを接続する部位に、独立した導
体端子が形成されており、かつ前記熱硬化性絶縁樹脂層
の加熱軟化時における溶融粘度が、200〜20000
ポイズの範囲であることを特徴とする半導体搭載用基板
である。
That is, the present invention relates to a wiring board for mounting a semiconductor for mounting a semiconductor chip,
A thermosetting insulating resin layer which is softened by heating and exhibits adhesiveness is formed on the surface on which the semiconductor chip is mounted, and the electrodes of the semiconductor chip and the conductor wiring of the wiring board on the surface of the thermosetting insulating resin layer. And an independent conductor terminal is formed at a portion where the thermosetting insulating resin layer has a melt viscosity of 200 to 20,000 at the time of softening by heating.
A semiconductor mounting substrate characterized by being in a poise range.

【0011】また本発明の第2は、導体配線を形成した
配線基板の半導体チップを搭載する側の面に、銅箔と加
熱によって軟化し接着性を発現する熱硬化性絶縁樹脂層
から成る2層シートを、加熱加圧して貼り合わせる工程
と、前記2層シートの銅箔をエッチングして導体端子を
形成する工程とからなることを特徴とする、前記半導体
搭載用基板の製造方法である。
A second aspect of the present invention is that a wiring board on which a semiconductor chip is mounted is formed of a copper foil and a thermosetting insulating resin layer which is softened by heating and exhibits adhesiveness. The method for producing a substrate for mounting a semiconductor, comprising: a step of bonding the layer sheets by applying heat and pressure; and a step of forming a conductor terminal by etching the copper foil of the two-layer sheet.

【0012】さらに、本発明の第3は、前記半導体搭載
用基板の導体端子と、半導体チップの電極とを対向させ
て位置合わせする工程と、半導体チップを裏面から加熱
しながら前記半導体搭載用基板に平行に押し付け、半導
体チップの電極を導体端子に接続させると共に、導体端
子を熱硬化性絶縁樹脂層に垂直に埋没貫通させ、導体端
子を配線基板の導体配線に接続させ、同時に半導体チッ
プを配線基板に接着させる工程と、からなることを特徴
とする半導体チップの実装方法である。
Further, a third aspect of the present invention is a step of aligning the conductor terminals of the semiconductor mounting substrate with electrodes of the semiconductor chip so as to face each other, and heating the semiconductor chip from the back surface thereof. , The electrodes of the semiconductor chip are connected to the conductor terminals, and the conductor terminals are buried vertically through the thermosetting insulating resin layer, and the conductor terminals are connected to the conductor wiring of the wiring board. Bonding a semiconductor chip to a substrate.

【0013】[0013]

【発明の実施の形態】以下、図面に基づき本発明を詳細
に説明する。図1は、本発明の半導体搭載用基板を得る
ための、代表的な製造方法を示す断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a typical manufacturing method for obtaining a semiconductor mounting substrate of the present invention.

【0014】まず、配線基板11と2層シート17とを
用意する(a)。配線基板11は、少なくとも絶縁樹脂
13と、半導体チップの電極を接続するための接続端子
と、実装用基板の端子に接続するための接続端子とを含
む導体配線12から成り、必要に応じて表面にソルダー
レジスト14を形成してあっても良い。また、導体配線
12の表面には、Au、Ni、Pd、In、Pb、Sn
などの金属及びこれらの合金の被膜を、無電解メッキも
しくは電解メッキにより設けてあっても良い。ポリイミ
ド樹脂やポリエステル樹脂等を絶縁層としたフレキシブ
ル配線基板や、エポキシ樹脂やフェノール樹脂等を絶縁
層としたリジット配線基板、さらには、Al23やAlN
等のセラミックスを絶縁層としたセラミックス配線基板
を用いることができる。
First, a wiring board 11 and a two-layer sheet 17 are prepared (a). The wiring board 11 includes a conductor wiring 12 including at least an insulating resin 13, a connection terminal for connecting an electrode of a semiconductor chip, and a connection terminal for connecting to a terminal of a mounting board. May be formed with a solder resist 14. Au, Ni, Pd, In, Pb, and Sn are formed on the surface of the conductor wiring 12.
A coating of a metal such as these and alloys thereof may be provided by electroless plating or electrolytic plating. A flexible wiring board having an insulating layer of polyimide resin or polyester resin, a rigid wiring board having an insulating layer of epoxy resin, phenol resin or the like, and further, Al 2 O 3 or AlN
A ceramic wiring substrate using a ceramic such as an insulating layer can be used.

【0015】2層シート17は、銅箔15と熱硬化性絶
縁樹脂層16の2層からなり、銅箔15の表面に、熱硬
化性絶縁樹脂ワニスを、後述の導体端子18と導体配線
12とに挟まれる部位の熱硬化性絶縁樹脂層16の厚さ
が、導体端子18の厚さに後述の表面処理19の厚さを
加えた厚さの、0.7〜1.5倍の範囲に入るように塗布
量を調整し、均一に塗布した後、乾燥して得ることがで
きる。上記の導体端子18と導体配線12とに挟まれる
部位の熱硬化性絶縁樹脂層16の厚さが、導体端子18
の厚さに表面処理19の厚さを加えた厚さの0.7倍よ
り小さいと、半導体チップの実装時に導体端子18が柱
となって、半導体チップと熱硬化性絶縁樹脂層16の間
に間隙ができて、半導体チップを接着することができ
ず、電気的信頼性が落ち易く、また1.5倍より大きい
と、導体端子18が熱硬化性絶縁樹脂層16を貫通でき
ず、導通が得られないといった問題を生じ易くなる。
The two-layer sheet 17 is composed of two layers, a copper foil 15 and a thermosetting insulating resin layer 16. A thermosetting insulating resin varnish is coated on the surface of the copper foil 15 with conductor terminals 18 and conductor wires 12 to be described later. The thickness of the thermosetting insulating resin layer 16 at a portion sandwiched by the above is in a range of 0.7 to 1.5 times the thickness of the conductor terminal 18 plus the thickness of a surface treatment 19 described later. It is possible to adjust the amount of coating so as to enter the coating, apply the coating uniformly, and then dry it. The thickness of the thermosetting insulating resin layer 16 at a portion sandwiched between the conductor terminal 18 and the conductor wiring 12 is the same as that of the conductor terminal 18.
When the thickness is smaller than 0.7 times the thickness obtained by adding the thickness of the surface treatment 19 to the thickness of the surface treatment 19, the conductor terminals 18 become pillars when the semiconductor chip is mounted, and the distance between the semiconductor chip and the thermosetting insulating resin layer 16 is reduced. In the case where the gap is formed, the semiconductor chip cannot be bonded and the electrical reliability is easily lowered, and if it is larger than 1.5 times, the conductor terminal 18 cannot penetrate the thermosetting insulating resin layer 16 and the conductive Is more likely to occur.

【0016】熱硬化性絶縁樹脂層16に用いる樹脂とし
ては、具体的には、エポキシ系樹脂、マレイミド系樹
脂、フッ素系樹脂、アクリル系樹脂、シリコーン系樹脂
などの樹脂を、1種または複数種混合して用いることが
できる。また、シート形成能に優れた熱可塑性樹脂を混
合して用いても良い。例えば、ポリアミド系樹脂、ポリ
エステル系樹脂、ポリイミド系樹脂、ウレタン系樹脂、
ポリスチレン系樹脂、合成ゴム系樹脂などである。
The resin used for the thermosetting insulating resin layer 16 may be, for example, one or more resins such as epoxy resin, maleimide resin, fluorine resin, acrylic resin, and silicone resin. They can be used in combination. Further, a thermoplastic resin having excellent sheet forming ability may be mixed and used. For example, polyamide resin, polyester resin, polyimide resin, urethane resin,
Polystyrene resin, synthetic rubber resin and the like.

【0017】熱硬化性絶縁樹脂層の樹脂に用いる硬化剤
としては、具体的にエポキシ樹脂の例を挙げると、潜伏
性硬化剤である、ジシアンジアミド、イミダゾール化合
物、有機酸ヒドラジド、ジアミノマレオニトリル、メラ
ミン誘導体、アミンイミド化合物、芳香族ジアゾニウム
塩、ジアリルヨードニウム塩、トリアリルスルホニウム
塩、トリアリルセレニウム塩、ケチミン化合物等を、1
種または複数種混合して用いることができる。これらの
接着性を有する樹脂に、着色料や、無機充填材、各種の
カップリング剤などを添加しても良い。
Specific examples of the curing agent used for the resin of the thermosetting insulating resin layer include epoxy resins, which are latent curing agents such as dicyandiamide, imidazole compounds, organic acid hydrazide, diaminomaleonitrile, and melamine. Derivatives, amine imides, aromatic diazonium salts, diallyliodonium salts, triallylsulfonium salts, triallylselenium salts, ketimine compounds, etc.
Species or a mixture of plural types can be used. Coloring agents, inorganic fillers, various coupling agents, and the like may be added to these adhesive resins.

【0018】次ぎに、導体配線12を形成した配線基板
11の、半導体チップを搭載する側の面に、2層シート
17を加熱加圧してラミネートする(b)。
Next, the two-layer sheet 17 is laminated on the surface of the wiring board 11 on which the conductor wiring 12 is formed, on the side on which the semiconductor chip is mounted, by heating and pressing (b).

【0019】続いて、銅箔15及びソルダーレジスト1
4の両面に、感光性レジスト膜を形成し、パターン露
光、レジスト現像、銅エッチング、及び感光性レジスト
剥離の各工程を経て、導体端子18を形成する(c)。
ここで、ソルダーレジスト14の面に形成する感光性レ
ジストは、導体配線12をエッチング液から保護する目
的で施されるものである。このエッチング法による導体
端子の形成は、メッキ法にあるような導体の高さのばら
つきをなくし、導通抵抗を低くかつ安定させる目的にか
なうものである。
Subsequently, the copper foil 15 and the solder resist 1
4, a photosensitive resist film is formed on both surfaces, and conductor terminals 18 are formed through the steps of pattern exposure, resist development, copper etching, and photosensitive resist peeling (c).
Here, the photosensitive resist formed on the surface of the solder resist 14 is applied for the purpose of protecting the conductor wiring 12 from an etchant. The formation of the conductor terminal by the etching method serves the purpose of eliminating the variation in the height of the conductor as in the plating method, and reducing and stabilizing the conduction resistance.

【0020】最後に、導体端子18に表面処理19を施
す(d)。これは銅の酸化を防止し、電気的接続性能を
高めるために成されるもので、Au、Ni、Pd、P
b、Sn、Inなどの金属及び合金を無電解メッキする
方法や、Pb−Sn合金であればフローソルダー法で行
なうこともできる。以上のようにして、本発明の半導体
搭載用基板が得られる。
Finally, a surface treatment 19 is applied to the conductor terminal 18 (d). This is performed to prevent oxidation of copper and to improve the electrical connection performance. Au, Ni, Pd, P
A method of electroless plating a metal or alloy such as b, Sn, In, or a Pb-Sn alloy by a flow solder method can also be used. As described above, the semiconductor mounting substrate of the present invention is obtained.

【0021】次に、本発明の半導体搭載用基板に半導体
チップを実装する方法について述べる。図2は、その代
表的な例を示す図である。
Next, a method of mounting a semiconductor chip on a semiconductor mounting board of the present invention will be described. FIG. 2 is a diagram showing a typical example.

【0022】まず、本発明による半導体搭載用基板22
を、ボンディング装置の基板受け台24の所定の位置に
置く。次いで、チップ吸着機構を有した加熱加圧ツール
23に、半導体チップ21を吸着固定し、半導体搭載用
基板22と半導体チップ21に予め形成されてある位置
決めマークを、画像認識装置により読み取り、導体端子
25と電極26を対向させ正確に位置合わせする。位置
合わせと同時に、半導体チップ21を、加熱加圧ツール
23を介して、熱硬化性絶縁樹脂層27の溶融粘度が、
200〜20000ポイズになる温度(50〜200
℃)に加熱する(a)。必要であれば基板受け台24に
ヒーターを内蔵させ、半導体搭載用基板22の方も加熱
して、熱硬化性絶縁樹脂層27を予め軟化させておいて
もよい。
First, the semiconductor mounting substrate 22 according to the present invention
Is placed at a predetermined position on the substrate receiving table 24 of the bonding apparatus. Next, the semiconductor chip 21 is suction-fixed to a heating / pressing tool 23 having a chip suction mechanism, and a positioning mark formed in advance on the semiconductor mounting substrate 22 and the semiconductor chip 21 is read by an image recognition device, and the conductor terminals are read. The electrode 25 and the electrode 26 are opposed to each other and accurately positioned. Simultaneously with the alignment, the melt viscosity of the thermosetting insulating resin layer 27 is set to
Temperature to become 200-20,000 poise (50-200
(A). If necessary, a heater may be built in the substrate receiving base 24, and the semiconductor mounting substrate 22 may be heated to soften the thermosetting insulating resin layer 27 in advance.

【0023】熱硬化性絶縁樹脂層27の軟化溶融粘度が
200ポイズを下回ると、絶縁樹脂のフローにより、導
体端子25が所望する位置からずれてしまったり、熱硬
化性絶縁樹脂層27の厚みが不均一になったりする。逆
に、軟化溶融粘度が20000ポイズを上回ると、加熱
加圧ツール23の所定圧では、導体端子25を熱硬化性
絶縁樹脂層27に埋没貫通させることが困難となり、導
体端子25と電極26との接続不良につながる。導体端
子25と電極26の材質の組み合わせによっては、より
高い接続性を得るために、超音波を併用することも可能
である。
When the softening melt viscosity of the thermosetting insulating resin layer 27 is less than 200 poise, the flow of the insulating resin causes the conductor terminals 25 to be displaced from a desired position or the thickness of the thermosetting insulating resin layer 27 to be reduced. It becomes uneven. Conversely, if the softening melt viscosity exceeds 20,000 poise, it becomes difficult to embed and penetrate the conductor terminal 25 into the thermosetting insulating resin layer 27 at a predetermined pressure of the heating and pressing tool 23, and the conductor terminal 25 and the electrode 26 Connection failure. Depending on the combination of the materials of the conductor terminal 25 and the electrode 26, it is also possible to use ultrasonic waves together in order to obtain higher connectivity.

【0024】次いで、加熱加圧ツール23を降下させ、
半導体チップ21を半導体搭載用基板22に対して平行
に押し付ける。導体端子25と電極26が接触した時点
で、一旦加熱加圧ツール23の降下を止め、半導体チッ
プ21の熱が導体端子25を介して熱硬化性絶縁樹脂層
27に伝達され、熱硬化性絶縁樹脂層27の温度が所望
する温度及び溶融粘度になったところで、1〜30kgf
/cm2での加圧を開始する。それによって、導体端子2
5が熱硬化性絶縁樹脂層27に垂直に埋没貫通し、その
底部が半導体搭載用基板22の接続端子である導体配線
28に接続される。さらに加圧状態のまま、熱硬化性絶
縁樹脂層27が熱硬化する温度に加熱して、所定の時間
だけ維持することで、半導体チップ21と半導体搭載用
基板22は熱硬化性絶縁樹脂層27によって固着される
(b)。さらにこのとき、超音波を併用すると、導体端
子25と電極26が合金接続され、機械的強度はさらに
増す。
Next, the heating and pressing tool 23 is lowered,
The semiconductor chip 21 is pressed in parallel to the semiconductor mounting substrate 22. When the conductor terminal 25 and the electrode 26 come into contact with each other, the descent of the heating / pressing tool 23 is stopped once, and the heat of the semiconductor chip 21 is transmitted to the thermosetting insulating resin layer 27 via the conductor terminal 25, and When the temperature of the resin layer 27 reaches the desired temperature and melt viscosity, 1 to 30 kgf
Start pressurization at / cm 2 . Thereby, the conductor terminal 2
5 is vertically buried and penetrates the thermosetting insulating resin layer 27, and the bottom thereof is connected to the conductor wiring 28 which is a connection terminal of the semiconductor mounting substrate 22. Further, the semiconductor chip 21 and the semiconductor mounting substrate 22 are heated to a temperature at which the thermosetting insulating resin layer 27 is thermoset in the pressurized state and maintained for a predetermined time, so that the thermosetting insulating resin layer 27 is formed. (B). Further, at this time, when ultrasonic waves are used in combination, the conductor terminals 25 and the electrodes 26 are alloy-connected, and the mechanical strength is further increased.

【0025】このとき用いる熱硬化性絶縁樹脂層27
は、室温では固形であり、軟化溶融温度まで加熱すれば
導体端子25を埋没貫通させることができ、さらに高温
に加熱することにより、熱硬化すると同時に半導体チッ
プ21と半導体搭載用基板22を接着できるものであ
る。熱硬化性絶縁樹脂層27の熱硬化しない軟化溶融温
度は、50℃から200℃の範囲のものが良い。50℃
より低い軟化溶融温度の熱硬化性絶縁樹脂では、シート
表面にタックが生じ、作業性が著しく低下する。また、
200℃を越える軟化溶融温度の熱硬化性絶縁樹脂にお
いては、導体端子が熱硬化性絶縁樹脂層を貫通し、導体
間を接触させ電気的導通をはかる際、貫通する前に熱硬
化が進行する可能性があり、接続不良を起こす。一方、
熱硬化開始温度は、上記の軟化溶融温度より10℃以上
高いことが重要となる。これ以下の温度差であると温度
制御が難しく、前記同様な接続不良につながる。以上の
ようにして、半導体チップ21は半導体搭載用基板22
に電気的かつ機械的に実装される(c)。
The thermosetting insulating resin layer 27 used at this time
Is a solid at room temperature, and can be buried and penetrated by heating the conductor terminal 25 when heated to the softening and melting temperature, and furthermore, by heating to a high temperature, the semiconductor chip 21 and the semiconductor mounting substrate 22 can be simultaneously bonded while being thermally cured. Things. The softening and melting temperature at which the thermosetting insulating resin layer 27 does not thermoset is preferably in the range of 50 ° C to 200 ° C. 50 ℃
In the case of a thermosetting insulating resin having a lower softening / melting temperature, tack occurs on the sheet surface, and workability is significantly reduced. Also,
In the thermosetting insulating resin having a softening and melting temperature exceeding 200 ° C., when the conductor terminal penetrates the thermosetting insulating resin layer and makes contact between the conductors for electrical conduction, the thermosetting proceeds before penetrating. May cause poor connection. on the other hand,
It is important that the thermosetting start temperature is higher than the softening and melting temperature by 10 ° C. or more. If the temperature difference is smaller than this, it is difficult to control the temperature, which leads to the same connection failure as described above. As described above, the semiconductor chip 21 is mounted on the semiconductor mounting substrate 22.
(C).

【0026】[0026]

【実施例】以下、実施例により更に具体的に説明する
が、本発明はこれによって何ら限定されるものではな
い。
EXAMPLES The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the invention is limited thereto.

【0027】実施例1 厚さ18μmの圧延銅箔(FX-BSH-35,三井金属鉱業(株)
製)に、エポキシ系樹脂ワニスを塗工、乾燥させ、銅箔
と厚さ40μmの熱硬化性絶縁樹脂層からなる2層シー
トを得た。この2層シートを、ポリイミド樹脂を絶縁層
としたフレキシブル配線基板の、半導体チップを搭載す
る側の面にラミネートした。得られた基材に対して、ド
ライフィルムラミネート、露光、現像、銅箔エッチン
グ、ドライフィルム剥離の各工程を経て、直径100μ
mの円柱状の導体端子が形成された半導体搭載用基板を
製造した。この時、導体端子と導体配線間の熱硬化性絶
縁樹脂層の厚さは、導体端子の0.7倍であった。
Example 1 Rolled copper foil having a thickness of 18 μm (FX-BSH-35, Mitsui Kinzoku Mining Co., Ltd.)
Was coated with an epoxy resin varnish and dried to obtain a two-layer sheet composed of a copper foil and a thermosetting insulating resin layer having a thickness of 40 μm. The two-layer sheet was laminated on a surface of a flexible wiring board using a polyimide resin as an insulating layer, on a side on which a semiconductor chip was mounted. The obtained substrate was subjected to dry film lamination, exposure, development, copper foil etching, and dry film peeling steps to obtain a diameter of 100 μm.
A semiconductor mounting substrate on which a m-shaped cylindrical conductor terminal was formed was manufactured. At this time, the thickness of the thermosetting insulating resin layer between the conductor terminal and the conductor wiring was 0.7 times the conductor terminal.

【0028】得られた半導体搭載用基板をボンディング
装置の基板受け台におき、半導体チップを吸着固定した
上側ツールとの位置合わせの後、基板受け台と上側ツー
ルを80℃に加熱した。この温度において、上記熱硬化
性絶縁樹脂層の溶融粘度は2000ポイズであり、熱硬
化反応は起こっていなかった。その後の10kgf/cm2
圧力での圧着により、導体端子は上記の熱硬化性絶縁樹
脂層を垂直に埋没貫通し、フレキシブル配線基板の配線
導体と接触した。さらにその後、加圧を続けた状態で、
ボンディング装置の基板受け台と上側ツールの温度を1
80℃で1分間保持し、半導体搭載用基板と半導体チッ
プを固着させた。導通抵抗は、2mΩ/導体端子1個で
あり、−50/125℃、500サイクル中で導通抵抗
値の変化はほとんどみられなかった。
The obtained substrate for mounting a semiconductor was placed on a substrate holder of a bonding apparatus, and after positioning with the upper tool on which the semiconductor chip was fixed by suction, the substrate holder and the upper tool were heated to 80 ° C. At this temperature, the melt viscosity of the thermosetting insulating resin layer was 2000 poise, and no thermosetting reaction occurred. By subsequent pressure bonding at a pressure of 10 kgf / cm 2 , the conductor terminal vertically penetrated and penetrated the thermosetting insulating resin layer, and came into contact with the wiring conductor of the flexible wiring board. After that, while continuing to pressurize,
Set the temperature of the board holder and upper tool of the bonding machine to 1
The substrate was held at 80 ° C. for 1 minute to fix the semiconductor mounting substrate and the semiconductor chip. The conduction resistance was 2 mΩ / one conductor terminal, and there was almost no change in the conduction resistance value at −50 / 125 ° C. and 500 cycles.

【0029】実施例2 厚さ70μmの電解銅箔(VLP,三井金属鉱業(株)製)
に、エポキシ系樹脂ワニスを塗工、乾燥させ、銅箔と厚
さ80μmの熱硬化性絶縁樹脂層からなる2層シートを
得た。この2層シートを、ポリイミド樹脂を絶縁層とし
たフレキシブル配線基板の、半導体チップを搭載する側
の面にラミネートした。なお、フレキシブル配線基板の
導体配線における、導体端子と接合する箇所には、予め
6Sn/4Pbはんだを、5μmの厚みでコートしてお
いた。得られた基材に対して、ドライフィルムラミネー
ト、露光、現像、銅箔エッチング、ドライフィルム剥離
の各工程を経て、直径100μmの円柱状の導体端子が
形成された半導体搭載用基板を製造した。さらに、導体
端子の露出した表面に、無電解6Sn/4Pbはんだメ
ッキ処理を施した。この時、導体端子と導体配線間の熱
硬化性絶縁樹脂層の厚さは、導体端子の0.8倍であっ
た。
Example 2 Electrolytic copper foil having a thickness of 70 μm (VLP, manufactured by Mitsui Kinzoku Mining Co., Ltd.)
Then, an epoxy-based resin varnish was applied and dried to obtain a two-layer sheet composed of a copper foil and a thermosetting insulating resin layer having a thickness of 80 μm. The two-layer sheet was laminated on a surface of a flexible wiring board using a polyimide resin as an insulating layer, on a side on which a semiconductor chip was mounted. In addition, 6Sn / 4Pb solder was previously coated with a thickness of 5 μm on a portion of the conductor wiring of the flexible wiring board which is to be joined to the conductor terminal. The obtained substrate was subjected to dry film lamination, exposure, development, copper foil etching, and dry film peeling steps to produce a semiconductor mounting substrate on which cylindrical conductive terminals having a diameter of 100 μm were formed. Further, the exposed surfaces of the conductor terminals were subjected to electroless 6Sn / 4Pb solder plating. At this time, the thickness of the thermosetting insulating resin layer between the conductor terminal and the conductor wiring was 0.8 times the conductor terminal.

【0030】得られた半導体搭載用基板をボンディング
装置の基板受け台におき、半導体チップを吸着固定した
上側ツールとの位置合わせの後、基板受け台と上側ツー
ルを150℃に加熱した。この温度において、上記熱硬
化性絶縁樹脂層の溶融粘度は900ポイズであり、熱硬
化反応は起こっていなかった。その後の12kgf/cm2
圧力での圧着により、導体端子は上記の熱硬化性絶縁樹
脂層を垂直に埋没貫通し、フレキシブル配線基板の配線
導体と接触した。さらにその後、加圧を続けた状態で、
ボンディング装置の基板受け台と上側ツールの温度を、
200℃で1分間保持し、半導体搭載用基板と半導体チ
ップを固着させた。さらに、260℃に加熱することに
より、導体配線と導体端子の間をはんだによりろう付け
し、接合を強化した。導通抵抗は、4mΩ/導体端子1
個であり、−50/125℃、1000サイクル中で導
通抵抗値の変化はほとんどみられなかった。
The obtained substrate for mounting a semiconductor was placed on a substrate holder of a bonding apparatus, and after positioning with a upper tool to which semiconductor chips were fixed by suction, the substrate holder and the upper tool were heated to 150 ° C. At this temperature, the melt viscosity of the thermosetting insulating resin layer was 900 poise, and no thermosetting reaction had occurred. By subsequent compression bonding under a pressure of 12 kgf / cm 2 , the conductor terminal vertically penetrated and penetrated the thermosetting insulating resin layer, and came into contact with the wiring conductor of the flexible wiring board. After that, while continuing to pressurize,
Adjust the temperature of the board holder and upper tool of the bonding machine.
The temperature was maintained at 200 ° C. for 1 minute to fix the semiconductor mounting substrate and the semiconductor chip. Furthermore, by heating to 260 ° C., soldering was performed between the conductor wiring and the conductor terminal by soldering to strengthen the bonding. The conduction resistance is 4 mΩ / conductor terminal 1
And there was almost no change in the conduction resistance value at −50 / 125 ° C. for 1000 cycles.

【0031】比較例1 エポキシ系樹脂ワニスに、Au/Ni/樹脂コア(粒径
約5μm)からなる導電性微粒子を、3wt%撹拌混合
しフィルム成形して、異方導電シートを作製した。この
異方導電シートを実施例で用いたものと同じフレキシブ
ル配線板の、半導体チップを搭載する側の面に、70
℃,5kgf/cm2の条件で仮圧着した。このようにして作
製した異方導電シート付半導体搭載用基板を、ボンディ
ング装置の基板受け台におき、Auスタッドバンプ付半
導体チップを吸着固定した、上側ツールとの位置合わせ
の後、前記の異方導電シート付半導体搭載用基板とAu
スタッドバンプ付半導体チップとを、170℃,20kg
f/cm2の条件で圧着し、固着させた。半導体搭載用基板
の導体配線と半導体チップのバウプが、導電性微粒子を
介して接触した。
Comparative Example 1 Conductive fine particles composed of Au / Ni / resin core (particle size: about 5 μm) were mixed with an epoxy resin varnish by stirring at 3 wt% to form a film to prepare an anisotropic conductive sheet. The same flexible wiring board as that used in this example was attached to the surface of the same flexible wiring board on which the semiconductor chip was mounted.
Temporary pressure bonding was performed at 5 ° C. and 5 kgf / cm 2 . The semiconductor mounting substrate with the anisotropic conductive sheet manufactured in this manner is placed on a substrate receiving table of a bonding apparatus, and the semiconductor chip with the Au stud bump is fixed by suction. Semiconductor mounting board with conductive sheet and Au
170 ° C, 20kg with a semiconductor chip with stud bumps
It was crimped under the condition of f / cm 2 and fixed. The conductor wiring of the semiconductor mounting substrate and the bow of the semiconductor chip contacted each other via the conductive fine particles.

【0032】実施例1,2、および比較例1における、
半導体チップ実装後の評価結果を、まとめて表1に示し
た。この結果から、本発明の半導体搭載用基板を用いる
ことにより、従来の異方導電シートを用いる実装方法に
比較して、端子1個あたりの導通抵抗や、TC試験(温
度サイクル試験)における抵抗値の上昇が大幅に低減さ
れ、TC試験における断線不良の発生は殆どなくなり、
本発明の半導体搭載用基板が極めて優れたものであるこ
とが分かる。
In Examples 1 and 2 and Comparative Example 1,
Table 1 summarizes the evaluation results after mounting the semiconductor chip. From these results, the use of the semiconductor mounting substrate of the present invention makes it possible to compare the conduction resistance per terminal and the resistance value in a TC test (temperature cycle test) as compared with the conventional mounting method using an anisotropic conductive sheet. Is significantly reduced, the occurrence of disconnection failure in the TC test is almost eliminated,
It can be seen that the semiconductor mounting substrate of the present invention is extremely excellent.

【0033】[0033]

【表1】 [Table 1]

【0034】[0034]

【発明の効果】以上詳述したように、本発明によれば、
半導体チップとの電気的及び機械的接続の機能に優れた
半導体搭載用基板を、低コストで製造提供することがで
き、さらに、容易で生産性に優れた実装方法をも提供す
ることができる。
As described in detail above, according to the present invention,
A semiconductor mounting substrate having excellent electrical and mechanical connection functions with a semiconductor chip can be manufactured and provided at low cost, and an easy and highly productive mounting method can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による半導体搭載用基板の、代表的な
製造方法を示す断面図である。
FIG. 1 is a sectional view showing a typical method for manufacturing a semiconductor mounting substrate according to the present invention.

【図2】 本発明による半導体搭載用基板を用いた実装
方法の、代表的な例を示す断面図である。
FIG. 2 is a cross-sectional view showing a typical example of a mounting method using a semiconductor mounting substrate according to the present invention.

【図3】 従来の導電性微粒子を分散した異方導電シー
トを用いた、半導体チップ実装方法の代表例を示す断面
図である。
FIG. 3 is a cross-sectional view showing a typical example of a semiconductor chip mounting method using a conventional anisotropic conductive sheet in which conductive fine particles are dispersed.

【図4】 従来の貫通穴に導電体を充填した樹脂フィル
ムを用いた、半導体チップ実装方法の代表例を示す断面
図である。
FIG. 4 is a sectional view showing a typical example of a semiconductor chip mounting method using a conventional resin film in which a through hole is filled with a conductor.

【符号の説明】[Explanation of symbols]

11 配線基板 12,28,36,47 導体配線 13 絶縁樹脂 14 ソルダーレジスト 15 銅箔 16,27 熱硬化性絶縁樹脂層 17 2層シート 18,25 導体端子 19 表面処理 21,31,41 半導体チップ 22,32,42 半導体搭載用基板 23 加熱加圧ツール 24 基板受け台 26,34,44 電極 33 導電性微粒子を分散した異方
導電シート 35 導電性微粒子 43 貫通穴を導電体で充填した樹
脂フィルム 45 導電体 46 接着層
DESCRIPTION OF SYMBOLS 11 Wiring board 12, 28, 36, 47 Conductor wiring 13 Insulating resin 14 Solder resist 15 Copper foil 16, 27 Thermosetting insulating resin layer 17 Two-layer sheet 18, 25 Conductor terminal 19 Surface treatment 21, 31, 41 Semiconductor chip 22 , 32, 42 Semiconductor mounting substrate 23 Heating and pressurizing tool 24 Substrate pedestal 26, 34, 44 Electrode 33 Anisotropic conductive sheet in which conductive fine particles are dispersed 35 Conductive fine particles 43 Resin film in which through holes are filled with conductive material 45 Conductor 46 Adhesive layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 謙介 東京都品川区東品川2丁目5番8号 住友 ベークライト株式会社内 Fターム(参考) 5E319 AA03 AB05 BB20 CC01 CD04 5F044 KK02 KK03 KK04 KK07 KK13 KK17 KK18 KK19 KK21 PP16 PP17 PP19  ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kensuke Nakamura 2-5-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite Co., Ltd. F-term (reference) 5E319 AA03 AB05 BB20 CC01 CD04 5F044 KK02 KK03 KK04 KK07 KK13 KK17 KK18 KK19 KK21 PP16 PP17 PP19

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップを搭載するための半導体搭
載用配線基板であって、半導体チップを搭載する側の面
に、加熱によって軟化し接着性を発現する熱硬化性絶縁
樹脂層を形成すると共に、該熱硬化性絶縁樹脂層表面
の、半導体チップの電極と配線基板の導体配線とを接続
する部位に、独立した導体端子が形成されており、かつ
前記熱硬化性絶縁樹脂層の加熱軟化時における溶融粘度
が、200〜20000ポイズの範囲であることを特徴
とする半導体搭載用基板。
1. A semiconductor mounting wiring board for mounting a semiconductor chip, wherein a thermosetting insulating resin layer which is softened by heating and exhibits adhesiveness is formed on a surface on a side on which the semiconductor chip is mounted. In the surface of the thermosetting insulating resin layer, an independent conductor terminal is formed at a portion connecting the electrode of the semiconductor chip and the conductor wiring of the wiring board, and when the thermosetting insulating resin layer is softened by heating. Wherein the melt viscosity is in the range of 200 to 20,000 poise.
【請求項2】 導体端子の厚さが、その直下に形成され
た熱硬化性絶縁樹脂層の厚さの、0.7〜1.5倍の範囲
であることを特徴とする、請求項1記載の半導体搭載用
基板。
2. The method according to claim 1, wherein the thickness of the conductive terminal is in the range of 0.7 to 1.5 times the thickness of the thermosetting insulating resin layer formed immediately below the conductive terminal. The substrate for mounting a semiconductor according to the above.
【請求項3】 導体配線を形成した配線基板の半導体チ
ップを搭載する側の面に、銅箔と加熱によって軟化し接
着性を発現する熱硬化性絶縁樹脂層から成る2層シート
を、加熱加圧して貼り合わせる工程と、前記2層シート
の銅箔をエッチングして導体端子を形成する工程とから
なることを特徴とする、請求項1または請求項2記載の
半導体搭載用基板の製造方法。
3. A two-layer sheet comprising a copper foil and a thermosetting insulating resin layer which is softened by heating and exhibits adhesiveness is heated and heated on the surface of the wiring board on which the semiconductor chip is mounted on which the conductive wiring is formed. 3. The method of manufacturing a semiconductor mounting substrate according to claim 1, comprising a step of pressing and bonding, and a step of forming conductor terminals by etching the copper foil of the two-layer sheet.
【請求項4】 請求項1記載の半導体搭載用基板の導体
端子と、半導体チップの電極とを対向させて位置合わせ
する工程と、半導体チップを裏面から加熱しながら前記
半導体搭載用基板に平行に押し付け、半導体チップの電
極を導体端子に接続させると共に、導体端子を熱硬化性
絶縁樹脂層に垂直に埋没貫通させ、導体端子を配線基板
の導体配線に接続させて、同時に半導体チップを配線基
板に接着させる工程と、からなることを特徴とする半導
体チップの実装方法。
4. A step of aligning the conductor terminals of the semiconductor mounting substrate according to claim 1 with electrodes of the semiconductor chip so as to face each other, and heating the semiconductor chip from the back surface in parallel with the semiconductor mounting substrate. Pressing, the electrodes of the semiconductor chip are connected to the conductor terminals, the conductor terminals are vertically buried and penetrated in the thermosetting insulating resin layer, and the conductor terminals are connected to the conductor wiring of the wiring board, and at the same time, the semiconductor chip is connected to the wiring board. Bonding the semiconductor chip.
【請求項5】 半導体チップを裏面から加熱しながら、
導体端子を熱硬化性絶縁樹脂層に垂直に埋没貫通させる
際における、該熱硬化性絶縁樹脂の溶融粘度が、200
〜20000ポイズの範囲であることを特徴とする、請
求項4記載の半導体チップの実装方法。
5. While heating the semiconductor chip from the back surface,
When the conductor terminal is buried vertically through the thermosetting insulating resin layer, the melt viscosity of the thermosetting insulating resin is 200.
The method for mounting a semiconductor chip according to claim 4, wherein the range is in the range of 20,000 poise.
JP11130654A 1999-05-11 1999-05-11 Semiconductor mounting board and manufacture thereof, and method of mounting semiconductor chip Pending JP2000323620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11130654A JP2000323620A (en) 1999-05-11 1999-05-11 Semiconductor mounting board and manufacture thereof, and method of mounting semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11130654A JP2000323620A (en) 1999-05-11 1999-05-11 Semiconductor mounting board and manufacture thereof, and method of mounting semiconductor chip

Publications (1)

Publication Number Publication Date
JP2000323620A true JP2000323620A (en) 2000-11-24

Family

ID=15039428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11130654A Pending JP2000323620A (en) 1999-05-11 1999-05-11 Semiconductor mounting board and manufacture thereof, and method of mounting semiconductor chip

Country Status (1)

Country Link
JP (1) JP2000323620A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696764B2 (en) 2002-01-24 2004-02-24 Nec Electronics Corporation Flip chip type semiconductor device and method of manufacturing the same
JP2012243862A (en) * 2011-05-17 2012-12-10 Kyocera Corp Electronic device and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696764B2 (en) 2002-01-24 2004-02-24 Nec Electronics Corporation Flip chip type semiconductor device and method of manufacturing the same
JP2012243862A (en) * 2011-05-17 2012-12-10 Kyocera Corp Electronic device and manufacturing method therefor

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