JP2000322896A - Flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by setting the gate voltage of a memory MOS on reading to a value which is detained by clamping a normal power supply voltage being supplied from the outside at most to the sum of the absolute value of the threshold voltage of an N-type depletion MOS and the gate voltage of the N-type depletion MOS. SOLUTION: The drain and source of an N-type depletion MOS 21 are connected in series between a normal power supply voltage Vcc supplied from the outside and a clamp voltage output node VCL, and output Vb of a gate bias circuit 22 is applied to the gate. The clamp voltage output node VCL becomes the sum of the absolute value of Vth of the N-type depletion MOS 21 and the output Vb of the gate bias circuit 22. With the value of the clamp voltage output node VCL, a current sense type sense amplifier circuit senses the presence or absence of a memory MOS current, and assures the data of the memory MOS in write state. Further, the consumption power is that of the gate bias circuit 22 only.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-power-supply flash memory mounted on a single-chip microcomputer or the like.

[0002]

2. Description of the Related Art In a flash memory operated by a single power supply,
Injecting electrons into the floating gate to raise the threshold voltage Vth of the memory MOS is called erasing.
Reducing th is referred to as writing (this definition may be reversed). In the read operation, the magnitude of the current of the memory MOS selected by the address decoder is converted into a logical output by the sense amplifier circuit. At this time, "H" is output if the memory MOS is in the erase state, and "L" is output if the memory MOS is in the write state. In the read operation, in order to maintain data reliability, the voltage for driving the gate of the memory MOS needs to be a voltage that does not cause word line disturbance, and in order to increase the current of the memory MOS,
In other words, it is desirable to use as high a voltage as possible in order to realize high-speed operation.

Conventionally, an operational amplifier circuit has been used to generate the memory cell drive voltage. FIG.
FIG. 12 schematically shows a configuration of a read voltage generation circuit using an operational amplifier circuit also shown in FIG. This read voltage generation circuit includes a reference voltage generation circuit 51, a first constant voltage generation circuit 52, and a second constant voltage generation circuit 53.

The reference voltage generation circuit 51 is a circuit that generates a certain reference voltage Vref independent of the power supply voltage and temperature.

The first constant voltage generating circuit 52 generates a reference voltage V
ref is used as a reference voltage to set the output circuit to clamp voltage Vr.
This is a circuit for performing negative feedback control on efA. Specifically, NMOS
A source follower circuit constituted by Q1 and a feedback resistor circuit (ladder resistor circuit) 54 is provided as an output circuit, has an operational amplifier OP1, receives a reference voltage Vref at a non-inverting input terminal (+) of the operational amplifier OP1, and receives the reference voltage Vref. The feedback signal from the output circuit is received at the inverting input terminal (−) of the
Control the conductance of Q1. Clamp voltage Vre
fA is the division ratio of the feedback resistor circuit 54 and the reference voltage Vref.
And a constant voltage determined by This clamp voltage VrefA does not logically depend on the power supply voltage Vcc. Further, the first constant voltage generation circuit 52 recognizes the fluctuation of the reference voltage Vref due to the process variation by the feedback resistance circuit 54.
Is adjusted by adjusting.

The second constant voltage generating circuit 53 is a circuit that performs negative feedback control of the output circuit to the clamp voltage VfixA using the clamp voltage VrefA as a reference voltage. More specifically, a source follower circuit including an NMOS Q2 and feedback resistors R1 and R2 is provided as an output circuit, has an operational amplifier OP2, and receives a clamp voltage VrefA at a non-inverting input terminal (+) of the operational amplifier OP2.
The inverting input terminal (-) of the operational amplifier OP2 receives a feedback signal from the output circuit, and the output of the operational amplifier OP2 causes N
It controls the conductance of MOSQ2. The clamp voltage VfixA is a constant voltage determined by the voltage division ratio of the feedback resistors R1 and R2 and the clamp voltage VrefA. This clamp voltage VfixA is logically the power supply voltage Vc
does not depend on c.

The clamp voltage VfixA is stored in a memory MO
By using it as the drive voltage for S, it is possible to perform a read operation at a voltage as high as possible below the word line disturb voltage.

On the other hand, an operational amplifier requires a bias current, and a constant DC current always flows during a read operation (about several mA). Therefore, there is a problem that power consumption does not decrease even in a low power consumption mode such as a subactive mode.

FIG. 6 shows a schematic configuration of a conventional current-voltage conversion type sense amplifier circuit (hereinafter referred to as an IV conversion type sense amplifier circuit). It comprises a load PMOS 61, a detection inverter 62, and a gate bias circuit 63, and is connected to Y selectors 110 and 111, a selection MOS 102, and a memory MOS 101. At the time of a read operation, the source potential control circuit 104 applies GND to the source of the memory MOS 101.
Supply potential. When the memory MOS 101 is in the erased state, the current of the memory MOS 101 becomes very small and the load P
The potential of the node c divided by the MOS 61 and the memory MOS 101 becomes higher than the logical threshold voltage VLT of the detection inverter 62, and the detection inverter 62 outputs the GND potential level “0”. On the other hand, the memory MO
When S101 is in the write state, the memory MOS 10
1 becomes large, the potential of the node c becomes lower than the logical threshold voltage VLT of the detection inverter 62, and the detection inverter 62 becomes at the power supply voltage potential level “1”.
Is output.

The driving potential (clamp voltage VfixA in FIG. 5) of the memory MOS 101 is theoretically the power supply voltage Vcc.
In practice, the power supply voltage Vcc is output when the power supply voltage Vcc falls below the clamp voltage. In a low voltage region where Vcc is equal to or lower than the clamp voltage, the drive voltage of the memory MOS becomes Vcc, and the current of the memory MOS 101 in the written state decreases. Therefore, there is a possibility that the reading speed is deteriorated or erroneous reading is performed.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a single-power-supply flash memory capable of reducing power consumption.

[0012]

In the flash memory according to the present invention, at the time of normal reading, the gate drive voltage generation circuit of the memory MOS is changed to the normal power supply voltage supplied from outside by the Vth of the N-type depletion MOS.
, And a DMOS clamp circuit that clamps the absolute value of the gate voltage of the N-type depletion MOS to the sum or less. The absolute value of Vth of N-type depletion MOS and N
The sum value of the gate voltage of the depletion type MOS is Vth of the memory MOS in the erased state and the memory M in the written state.
The upper limit is set to a value such that the memory MOS does not cause word line disturbance. On the other hand, at the time of verifying after erasing and verifying after writing, verifying is performed using the current verifying power supply after erasing and the current verifying power supply after writing. In addition, the sense amplifier circuit at the time of normal reading includes the memory M in the written state.
If Vth of the OS is equal to or lower than the gate drive voltage of the memory MOS and Vth of the memory MOS in the erased state is equal to or higher than the gate drive voltage of the memory MOS, a normal value is output. In other words, the presence or absence of the current of the memory MOS is detected. A high-speed current sense type sense amplifier circuit is used. On the other hand, during verification after writing and verification after erasing, the memory MO
An existing IV conversion type sense amplifier circuit capable of monitoring the write level and erase level of S is used.

The DMOS clamp circuit has a function of generating a gate drive voltage for driving the gate of the memory MOS from a power supply voltage Vcc supplied from the outside. Further, it has a function of clamping the gate drive voltage to a constant voltage even when the external power supply voltage Vcc fluctuates. Further, the current sense type sense amplifier circuit has a function of detecting presence / absence of a memory MOS current, converting it to a voltage level, and outputting a logical value “H” or “L”.

[0014]

(Embodiment 1) FIG. 1 schematically shows a read circuit of the present invention. A power supply 105 for normal reading, a power supply 106 for verification after writing, and a power supply 107 for verification after erasing are connected to a power supply terminal of a word line driving level shift circuit 109 via a changeover switch 108. The memory MOS 101 is connected to the word line WL, and the source of the memory MOS 101 is connected to the source potential control circuit 1.
04. The drain of the memory MOS 101 is connected to the sub-bit line SBL, and is connected to the bit line BL via the selection MOSs 102 and 103. The bit line BL is connected to an IV conversion type sense amplifier circuit 112 and a current sense type sense amplifier circuit 113 via Y selectors 110 and 111. The two types of sense amplifier circuits are controlled by a data line initialization signal PRE, a sense amplifier start signal SAC, and a mode switching signal MODC, and output the output as SOUT via a switch 114.

At the time of verifying after erasing and verifying after writing, the gate of the memory MOS 101 is driven by the verifying power supply 107 after erasing and the verifying power supply 106 after writing in the same manner as in the prior art, and the IV conversion type sense is performed. The erasing level and the writing level are set using the amplifier circuit 112.

On the other hand, at the time of normal reading, the gate of the memory MOS 101 is driven by the normal reading power supply 105, and data is read using the current sense type sense amplifier circuit 113.

FIG. 2 shows the configuration of the normal read power supply 105 in FIG. In this circuit, the drain and source of an N-type depletion MOS 21 are connected in series between a normal power supply voltage Vcc supplied from the outside and a clamp voltage output node VCL, and the output Vb of the gate bias circuit 22 is applied to the gate thereof. Is done. Clamp voltage output node VCL
Is the sum of the absolute value of Vth of the N-type depletion MOS 21 and the output Vb of the gate bias circuit 22.
For example, when the Vth of the N-type depletion MOS 21 is −
When 3.0V and Vb are 0.5V, VCL becomes 3.5V.

The value of the clamp voltage output node VCL depends on the characteristic that the current sense type sense amplifier circuit senses the presence or absence of the memory MOS current and the write state of the memory MO.
By guaranteeing the data of S, the memory MO in the erased state
S is set between Vth of S and Vth of the memory MOS in the written state, and the upper limit is set to a value that does not cause the memory MOS to perform an erase operation.

Further, the clamp voltage output node VCL
Only the power consumption of the gate bias circuit 22 is generated at the time of generation of the data, and the power consumption can be reduced by suppressing the power consumption of the gate bias circuit 22.

FIG. 3 shows the configuration of the gate bias circuit 22 shown in FIG. PMOS31,
32 performs an exclusive operation. When the PMOS 31 is turned on, both voltages of the capacitor 33 become Vcc, and the capacitor 33 is discharged. Next, when the PMOS 32 is turned on, the PMOS 3
2. The charging current of the capacitor 33 flows toward GND via the NMOS 34, thereby
The source-to-source potential Vb is established. When the PMOS 32 is turned off and the PMOS 31 is turned on, the operation returns to the initial state, and the capacitor 33 is set in the discharging mode to turn off the charging current. Here, since the gate-source potential Vb of the NMOS 34 once established does not have a leak path except for being pulled out by the sub-threshold current of the NMOS 34, the discharge time constant is
It becomes sufficiently longer than the width of the operation clock CLK. Therefore, the potential can be maintained by intermittently supplying the charging current of the capacitor 33 by the operation clock. This circuit has no DC path from Vcc to GND and consumes most of the current when switching the operation clock CLK. Therefore, the lower the operation clock is, the more effective the power consumption is. For example, the current consumed by the gate bias circuit in the low power consumption mode of the microcomputer is as small as about several tens nA.

The IV conversion type sense amplifier circuit 1 shown in FIG.
FIG. The IV conversion type sense amplifier circuit includes a first data line initializing circuit 81, a second data line initializing circuit 82, a voltage clamp circuit 83 for keeping the drain voltage of the memory MOS constant, a data detecting section 84, an eraser. It comprises a load PMOS 85 for later verification, a load PMOS 86 for verification after writing, and data line discharge NMOSs 87 and 88. FIG. 9 shows the operation timing. At the time of verification after writing and erasing, an initial setting signal IVPRE is generated with one shot pulse from the rise of the start signals IVSAC and SAC, and the first data line initializing circuit 81 and the second data line initializing circuit 82 use the data line Initialize IN. At the fall of IVPRE, the initially set precharge current is turned off, and a current is generated from the load PMOS 86 during verification after writing, and from the load PMOS 85 to memory MOS during verification after erasure. At this time, a node d determined by a voltage dividing ratio of the operating resistance of the memory MOS and the operating resistance of the load PMOS.
Is converted to a logical output by the data detection unit 84.
After that, when IVSAC and SAC fall and the Belphi operation ends, the data line discharge NMOS 8
7, 88 are turned on to pull out the potential of the data line. Also,
The data line discharge NMOSs 87 and 88 also perform a discharge operation in the normal read mode, and pull out the potential of the data line after the end of the read.

FIG. 10 shows current characteristics of the load PMOS and the memory MOS of the IV conversion type sense amplifier circuit at the time of writing and erasing. The load PMOS operates as a load resistor,
At this time, since the sense amplifier power supply voltage is clamped to a certain voltage, it is fixed to a certain current value. on the other hand,
The memory MOS has a square-curve characteristic because the source is connected to GND and the drain is clamped to a certain value by the voltage clamp circuit 83. This characteristic moves parallel to the left when a write operation is performed, and moves parallel to the right when an erase operation is performed. The IV conversion type sense amplifier circuit is "L" when the current value of the memory MOS is equal to or less than the current value of the load PMOS.
And outputs “H” when the current value of the memory MOS is equal to or larger than the current value of the load PMOS. Therefore, V of the memory MOS
When setting th to the write level, the write level + ΔV (ΔV is the load PMO
The write operation may be performed as arbitrarily set because it depends on the S size, and the point at which the output of the IV conversion type sense amplifier circuit switches from “L” to “H” may be monitored. Similarly, when Vth of the memory MOS is set to the erase level, the word line potential is set to the erase level + ΔV
Erase operation is performed, and the point at which the output of the IV conversion type sense amplifier circuit switches from “H” to “L” may be monitored. As described above, by using the IV conversion type sense amplifier circuit, the write level and the erase level can be set to arbitrary values.

The current sense type sense amplifier circuit 1 shown in FIG.
FIG. The current sense type sense amplifier circuit includes a voltage clamp circuit 41 for keeping the drain voltage of the memory MOS constant, a data detection unit 42, a memory MOS current amplification unit 43, and a data line initialization PMOS 44. FIG. 7 shows the operation timing. At the time of the normal read operation, the mode switching signal MODC becomes “H”, and the initialization signal CPRE is generated by one shot pulse from the rise of the start signal CSAC, and the data line initialization PMOS 4
In step 4, the data line IN is initialized. At the fall of CPRE, the initial setting precharge current is turned off,
A current corresponding to the erase state flows through the path a. This current is amplified by the memory MOS current amplifying section 43 and the data detecting section 4
The data is converted to a logical output by 2. If the memory MOS is in the erased state, no current is generated in the path a, so that the node b
And the NMOS 45 to the GND level. Therefore, the output OUT outputs “L”. If the memory MOS is in the write state, a current is generated in the path a, amplified by the memory MOS current amplifying unit 43, and the level of the node b becomes close to the power supply voltage Vcc. Therefore, the output OUT outputs “H”. Further, even if the memory MOS current in the written state decreases in the low voltage region, normal operation can be expected because the memory MOS current amplifier 43 amplifies the current. As described above, the present sense amplifier can detect the presence / absence of the memory MOS current, and the Vth of the memory MOS in the write state and the Vth of the memory MOS in the erase state can be detected.
If the potential is between th, stable operation can be expected.

(Embodiment 2) FIG. 11 shows an example of mounting the flash memory of Embodiment 1 on a microcomputer. The microcomputer 1101 has a flash memory 1
102, a central processing unit 1106, a random access memory 1107, a timer 1108, a serial 1109, and the like are built in, and a single power supply voltage Vcc supplied from outside is used as an operation power supply. In the normal read operation of the flash memory 1102, the power supply voltage Vcc is clamped by the normal read power supply 105 to a voltage between Vth of the memory MOS in the write state and Vth of the memory MOS in the erase state, and is used as the power supply of the word driver 109. The gate of the memory MOS in the memory cell array 1104 is driven. Further, in the normal read operation, data is output to the data bus 1105 by the current sense type sense amplifier circuit 113 for detecting the presence or absence of the memory MOS current. According to the present embodiment,
Low consumption of microcomputer program execution,
Low voltage operation becomes possible.

[0025]

According to the present invention, a read operation of a flash memory which realizes low power consumption from a low voltage such as Vcc = about 2.2 V to a high voltage such as Vcc = about 5.5 V can be realized. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a configuration of a normal read power supply in FIG. 1;

FIG. 3 is a configuration of a gate bias circuit in FIG. 2;

FIG. 4 is a configuration of a current sense type sense amplifier circuit in FIG. 1;

FIG. 5 shows a configuration of a conventional normal read power supply.

FIG. 6 is a schematic diagram of a conventional current-voltage conversion type sense amplifier circuit.

FIG. 7 is a timing chart in FIG. 4;

8 is a configuration of an IV conversion type sense amplifier circuit in FIG.

FIG. 9 is a timing chart in FIG. 8;

FIG. 10 shows current characteristics of a load PMOS and a memory MOS in FIG.

11 is a schematic diagram showing an application of the embodiment of FIG. 1 to a microcomputer.

[Explanation of symbols]

101: memory MOS, 102, 103: selection MOS,
104: source potential control circuit, 105: power supply for normal reading, 106: power supply for verification after writing, 107
... power supply for verification after erasing, 108, 114 ... changeover switch, 109 ... level shift circuit, 110, 11
1 Y selector, 112 IV conversion type sense amplifier circuit, 113 current sense type sense amplifier circuit, WL word line, SBL sub bit line, BL bit line, DL
Data line, 21 ... N-type depletion MOS, 22 ... Gate bias circuit, 31, 32 ... PMOS, 33 ... Capacitance, 34 ... NMOS, 41 ... Voltage clamp circuit, 42 ...
Data detector 43, memory MOS current amplifier 44
Data initialization PMOS, 51 ... reference voltage generation circuit, 52
.., A first constant voltage generating circuit, 53, a second constant voltage generating circuit, 54, a feedback resistor circuit, 61, a load PMOS, 62,.
Inverter for detection, 63 ... gate bias circuit, 81 ...
A first data line initialization circuit, 82 a second data line initialization circuit, 83 a voltage clamp circuit, 84 a data detection unit, 85 a verifying load PMOS after erase, 86
... Verification load PMOS after writing, 87, 8
8 Data line discharge NMOS 1101 Microcomputer 1102 Outline of normal read circuit of flash memory 1103 Power supply voltage Vcc 1104
... memory cell array, 1105 ... data bus, 1106
... Central processing unit, 1107 ... Random access memory,
1108: timer, 1109: serial.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeyuki Hashimoto 3-2-1 Sachimachi, Hitachi City, Ibaraki Prefecture Inside Hitachi Engineering Co., Ltd. (72) Inventor Junichi Kono 3-1-1 Sachimachi, Hitachi City, Ibaraki Prefecture No. 1 Inside Hitachi, Ltd. Hitachi Plant (72) Inventor Hiroyuki Kida 3-1-1 Kochicho, Hitachi City, Ibaraki Pref. Inside Hitachi Plant Hitachi Plant F-term (reference) 5B025 AD03 AD06 AD06 AE06

Claims (4)

[Claims] A single power supply voltage supplied to an external power supply terminal is used as an operation power supply, and a gate drive voltage of a memory MOS at the time of reading is changed from a normal power supply voltage supplied from the outside to Vth of an N-type depletion MOS. And a voltage clamped to be equal to or less than a sum of an absolute value of the gate voltage of the N-type depletion MOS and a gate voltage of the N-type depletion MOS. 2. The method according to claim 1, wherein the N-type depression M
A flash memory having a gate bias circuit for setting a gate voltage of an OS. 3. The method according to claim 1, wherein the N-type depression M
The sum of the absolute value of Vth of the OS and the gate voltage of the N-type depletion MOS is equal to the Vt of the memory MOS in the erased state.
a flash memory having a voltage between h and Vth of a memory MOS in a written state. 4. The device according to claim 1, further comprising two types of sense amplifier circuits having different characteristics and sense amplifier switching means.
A flash memory, wherein a verify mode after erasure, a verify mode after write, and a normal read mode are selectively used.