JP2000311905A - Manufacturing composite semiconductor device - Google Patents

Manufacturing composite semiconductor device

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Publication number
JP2000311905A
JP2000311905A JP12092599A JP12092599A JP2000311905A JP 2000311905 A JP2000311905 A JP 2000311905A JP 12092599 A JP12092599 A JP 12092599A JP 12092599 A JP12092599 A JP 12092599A JP 2000311905 A JP2000311905 A JP 2000311905A
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Prior art keywords
substrate
semiconductor chip
solder paste
semiconductor device
frame
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Pending
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JP12092599A
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Japanese (ja)
Inventor
Eigo Fukuda
永吾 福田
Original Assignee
Nippon Inter Electronics Corp
日本インター株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051Forming additional members, e.g. dam structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]

Abstract

PROBLEM TO BE SOLVED: To downsize a composite semiconductor device by reducing the spacing 2 mm or less between adjacent semiconductor chips mounted on a substrate to realize high density mounting.
SOLUTION: Solder paste 8 is printed inside partition walls 5 or semiconductor chip housing frames 7 in a grid formed in advance by screen printing, etc., on a substrate 1, and individual semiconductor chips 9 are laid and secured on the solder paste 8. Since on jig such as carbon jig is used, the spacing between adjacent semiconductor chips can be set to 2 mm or less, without being limited by the partition wall thickness, as was the case in prior art.
COPYRIGHT: (C)2000,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】本発明は、複合半導体装置の製造方法に関し、特に基板に特別の治具を使用することなく複数の半導体チップを搭載・固着する複合半導体装置の製造方法に関するものである。 [0001] The present invention relates to a method of manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a composite semiconductor device mounted and fixed a plurality of semiconductor chips without using a special jig substrate.

【0002】 [0002]

【従来の技術】図7は従来の方法により製作された複合半導体装置に用いる基板の平面図である。 BACKGROUND ART FIG. 7 is a plan view of a substrate used for the composite semiconductor device fabricated by the conventional method. 図において、 In the figure,
1は半導体チップ2を搭載する基板である。 1 is a substrate for mounting a semiconductor chip 2. この基板1 The substrate 1
上に複数の半導体チップ2が、その隣接間隔tを2mm 2mm plurality of semiconductor chips 2, the adjacent interval t on
程度にし、縦、横に整列した状態で搭載・固着されている。 The extent, vertically, are mounted and fixed in a state of being aligned laterally. なお、上記基板1は、銅合金板あるいは絶縁板の表面に導体層を形成したものからなり、また、隣接する半導体チップ2同士は、その裏面側で同電位になるように搭載・固着されている。 Incidentally, the substrate 1 is made of those forming a conductor layer on the surface of the copper alloy plate or an insulating plate, also between the semiconductor chips 2 adjacent, at its rear side are mounted and fixed to the same potential there.

【0003】上記のように基板1上に半導体チップ2を搭載・固着させる方法として従来では次のような方法を採用している。 [0003] adopts the following method in the art as a method for mounting, fixing the semiconductor chip 2 on the substrate 1 as described above. すなわち、図8に示すように、仕切り壁の厚さPを2mm程度とした多数のマス目を形成したカーボン治具3を基板1の外周に被せ、各マス目3a内にはそれぞれチップ状のソルダ4と半導体チップ2を挿入する。 That is, as shown in FIG. 8, covered with carbon jig 3 forming a large number of squares and the partition wall thickness P of about 2mm on the outer periphery of the substrate 1, respectively chip-like in the each square 3a inserting the solder 4 and the semiconductor chip 2.

【0004】次いで、上記の基板1を炉内を通過させるか、あるいは熱板上に載せ、ソルダ4を溶融させて各半導体チップ2を基板1上に固着させるようにしている。 [0004] Then, so that to fix either passes through the furnace the substrate 1 described above, or placed on a hot plate, each semiconductor chip 2 with solder 4 is melted on the substrate 1.
上記のような方法を採用する場合、カーボン治具の強度的な問題等で仕切り壁Pの厚さは2mm以下にはできない。 When employing such a method, the thickness of the partition wall P in strength problems like carbon jig can not be a 2mm or less. このため、必然的に基板1に整列させて搭載・固着させる半導体チップ2の隣接間隔tも2mm以下とすることができなかった。 Therefore, adjacent interval t inevitably semiconductor chip 2 to be mounted and fixed aligning the substrate 1 could not even be a 2mm or less.

【0005】 [0005]

【発明が解決しようとする課題】従来の方法では、マス目状のカーボン治具を使用するため、仕切り壁の強度を考慮しなければならず、最終的に基板に搭載・固着させる半導体チップの隣接間隔を2mm以下とすることができなかった。 In THE INVENTION Problems to be Solved by conventional methods, for using the grid-like carbon jig, it is necessary to consider the strength of the partition walls, and finally the semiconductor chip to be mounted and fixed to the substrate adjacent interval could not be 2mm or less. このため、高密度実装化並びに複合半導体装置の小型化を図ることができなかった。 Therefore, it was not possible to reduce the size of the high-density mounting and the composite semiconductor device.

【0006】 [0006]

【発明の目的】本発明は上記のような課題を解決すたためになされたもので、基板上に搭載する半導体チップの隣接間隔を2mm以下とすることができ、このため高密度実装化と複合半導体装置の小型化を図ることができる複合半導体装置の製造方法を提供することを目的とするものである。 THE INVENTION An object of the present invention has been made in order to have to solve the above problems, the distance between the adjacent semiconductor chips to be mounted on the substrate can be 2mm or less, and therefore high-density packaging and composite it is an object to provide a method for manufacturing a composite semiconductor device capable of reducing the size of the semiconductor device.

【0007】 [0007]

【課題を解決するための手段】本発明は上記のような課題を解決すたためになされたもので、第1の発明は、基板上に、レジスト枠をレジストにより印刷する工程と、 The present invention SUMMARY OF] has been made in order that solve the aforementioned problems, the first invention includes the step of printing on a substrate, a resist frame by a resist,
次いで、前記レジスト枠内にソルダペーストを印刷する工程と、次いで、前記ソルダペーストの上に半導体チップを載置する工程と、次いで、前記基板を加熱し、前記ソルダペーストを溶かして前記半導体チップを基板上にソルダ付けする工程とを含むことを特徴とするものである。 Then, a step of printing a solder paste into the resist frame, then a step of placing the semiconductor chip on the solder paste, then heating the substrate, the semiconductor chip by dissolving the solder paste it is characterized in that a step of attaching solder on the substrate.

【0008】第2の発明は、前記レジスト枠が少なくともその一部に、溶融した余分なソルダペーストが流出するための切欠部が形成されている仕切り壁であることを特徴とするものである。 A second invention, in the resist frame at least partially, is characterized in that a partition wall notch for extra solder paste melt flows out are formed.

【0009】第3の発明は、前記レジスト枠がマス目状の半導体チップ収納枠であることを特徴ものである。 A third invention is characterized in that the resist frame is square-shaped semiconductor chip housing frame.

【0010】第4の発明は、前記マス目状の半導体チップ用収納枠の線幅が2mm以下であることを特徴とするものである。 [0010] A fourth invention, the line width of the grid-shaped semiconductor chip for receiving frame is characterized in that it is 2mm or less.

【0011】第5の発明は、前記基板が熱伝導度の良好な導体板であることを特徴とするものである。 [0011] The fifth invention is characterized in that the substrate is a good conductor plate of the heat conductivity.

【0012】 [0012]

【実施例】以下に本発明の実施例を、図を参照して説明する。 Examples of EXAMPLES The invention will now be described with reference to FIG. 図1は本発明に使用する基板の平面図であり、図2は図1におけるA−A断面図である。 Figure 1 is a plan view of a substrate used in the present invention, FIG 2 is an A-A sectional view in FIG. 図において、基板1は熱伝導度の良好な導体板から形成され、例えば銅合金板から成り、絶縁層を介して図示を省略した導体パターンが形成されている。 In the figure, the substrate 1 is formed from a good conductor plate of the heat conductivity, for example, a copper alloy sheet, the conductor pattern (not shown) through an insulating layer is formed. なお、絶縁板上に導体層を形成したものであっても良い。 Incidentally, it may be made by forming a conductive layer on an insulating plate.

【0013】上記の基板1上にレジストにより各半導体チップの四隅に対応する仕切り壁5を縦、横に形成する。 [0013] forming the partition wall 5 corresponding to the four corners of the semiconductor chip by a resist on the substrate 1 of the vertical and the horizontal. 該仕切り壁5の高さは10〜20μmであり、スクリーン印刷等の手段により印刷形成する。 The height of the partition wall 5 is 10 to 20 [mu] m, formed by printing by means of screen printing. また、上記の仕切り壁5は、隣接する仕切り壁5との間に間隙6が形成されるように形成する。 Further, the partition wall 5 above is formed such that a gap 6 is formed between the partition wall 5 adjacent. なお、上記の仕切り壁5は、 In addition, the partition wall 5 of the above,
図6に示すようにマス目状の半導体チップ用収納枠7をレジストにより形成するようにしても良い。 The grid-shaped semiconductor chip for receiving frame 7 may be formed by the resist as shown in FIG. 次いで、上記のレジストが硬化した後、仕切り壁5で囲まれた内部、あるいはマス目状の半導体チップ用収納枠7の内部にソルダペースト8をスクリーン印刷する。 Then, after the resist is cured, the solder paste 8 is screen-printed inside surrounded by the partition wall 5, or in the interior of the square-shaped semiconductor chip housing frame 7. この時のソルダペストの高さ寸法をQ、仕切り壁5あるいは前記半導体チップ用収納枠5の高さ寸法をS、その幅をRとすると、本実施例ではQ=100μm、R=0.5〜1m The height of Sorudapesuto at this time Q, the height of the partition wall 5 or the semiconductor chip for receiving frame 5 S, when the width of the R, in the present embodiment Q = 100μm, R = 0.5~ 1m
m、S=10〜20μmとした。 m, was S = 10~20μm.

【0014】次いで、各ソルダペースト8の上に半導体チップ9を載せる。 [0014] Then, place the semiconductor chip 9 on each solder paste 8. この場合、後述する理由により半導体チップ9はソルダペースト上に正確に位置決めして載せる必要はない。 In this case, the semiconductor chip 9 for reasons to be described later does not need to put exactly positioned on the solder paste.

【0015】次いで、上記の基板1を図示を省略した台の上に載せて炉内を通過させるか、若しくは熱板の上で加熱してソルダペースト8を溶かす。 [0015] Then, melt the solder paste 8 is heated on the put on a table which is not shown the substrate 1 of the above or pass through the furnace, or hot plate. この時、溶融時のソルダペースト8の表面張力により図4に示すように自動的に仕切り壁5内あるいはマス目状の半導体チップ用収納枠7内の中心位置に半導体チップが位置決めされる。 At this time, the semiconductor chip is positioned at the center position in the automatic partition wall 5 or in a grid-like semiconductor chip for receiving frame 7 as shown in FIG. 4 by the surface tension of the solder paste 8 during melting.

【0016】すなわち、溶融したソルダペースト8の拡りは上記仕切り壁5あるいは上記収納枠7で規制される範囲内で拡り、半導体チップ9の裏面はソルダペースト8と最も大きな面積で接するようになるので、上記仕切り壁5あるいは上記収納枠7の囲いの中で自己整列されることになる。 [0016] That is, 拡Ri the solder paste 8 was melted 拡Ri within regulated by the partition wall 5 or the housing frame 7, in contact with the largest area backside the solder paste 8 of the semiconductor chip 9 since, it will be self-aligned within the enclosure of the partition wall 5 or the housing frame 7. このため、半導体チップ9はソルダペースト8上に特に位置決めして載せる必要はない。 Thus, the semiconductor chip 9 is not required to put in particular positioned on the solder paste 8.

【0017】なお、隣接する仕切り壁5の間に間隙6を形成することにより、この間隙6を介して余分なソルダペースト8と気泡が外側に流れ出すため、ピンホール等が形成され難くなる。 [0017] Incidentally, by forming the gap 6 between the partition wall 5 adjacent, excess solder paste 8 and the bubble through the gap 6 is for flowing the outside, such as pinholes are less likely to be formed.

【0018】 [0018]

【発明の効果】以上説明したように本発明は、基板にスクリーン印刷等により予め設けた仕切り壁あるいはマス目状の半導体チップ用収納枠内にソルダペーストを印刷し、このソルダペースト上に個々の半導体チップを載置・固定するようにしたので、概略次のような効果がある。 The present invention described above, according to the present invention is a solder paste was printed in advance provided with a partition wall or grid-shaped semiconductor chip accommodating frame by screen printing or the like on a substrate, the individual on the solder paste since the semiconductor chip to be mounted and fixed, advantages can be summarized below. (1)カーボン治具のような治具を使用しないので、従来のように仕切り壁の厚さで制限されることなく隣接する半導体チップの間隔を2mm以下とすることができる。 (1) it does not use a jig such as carbon jig, as in the conventional spacing of adjacent semiconductor chips without being restricted by the partition wall thickness may be 2mm or less. (2)上記のように隣接半導体チップ間隔を2mm以下にできるため、複合半導体装置の高密度実装化と小型化を図ることができる。 (2) Since the adjacent semiconductor chip interval as described above can be made 2mm or less, it is possible to achieve high density mounting and miniaturization of the composite semiconductor device. (3)半導体チップの外周に治具の枠が接触するということがないので、チップ自体にに損傷等を与えるおそれがなく、不良品の発生率が減少する。 (3) since there is no fact that the jig frame to the outer periphery of the semiconductor chip are in contact, there is no possibility of damage or the like on the chip itself, the incidence of defective products is reduced.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に使用する基板の平面図である。 1 is a plan view of a substrate used in the present invention.

【図2】図1のA−A線に沿う断面図である。 2 is a sectional view taken along line A-A of FIG.

【図3】上記基板の仕切り壁ないし半導体チップ用収納枠内にソルダペーストを印刷した状態を示す断面図である。 3 is a sectional view showing a state in which printing solder paste on the partition wall to the semiconductor chip accommodating frame of the substrate.

【図4】上記ソルダペーストが溶けて半導体チップが自己整列された状態を示す断面図である。 4 is a sectional view showing a state where the semiconductor chip the solder paste melts are self-aligned.

【図5】ソルダペーストが仕切り壁の間隙から外側へ流出している状態を示す平面図である。 5 is a plan view showing a state where solder paste is flowing from the gap of the partition wall to the outside.

【図6】基板の他の実施例を示す平面図である。 6 is a plan view showing another embodiment of a substrate.

【図7】従来の方法により製作された基板の平面図である。 7 is a plan view of a substrate which is manufactured by conventional methods.

【図8】基板上に半導体チップを載置・固定する従来の方法を説明するための断面図である。 8 is a sectional view for explaining a conventional method of a semiconductor chip is placed and fixed on the substrate.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 基板 2 半導体チップ 3 カーボン治 4 ソルダペースト 5 仕切り壁 6 間隙 7 マス目状の半導体チップ用収納枠 8 ソルダペースト 9 半導体チップ 1 substrate 2 the semiconductor chip 3 carbon jig 4 solder paste 5 partition wall 6 gap 7 squares shaped semiconductor chip for receiving frame 8 solder paste 9 semiconductor chip

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】基板上に、レジスト枠をレジストにより印刷する工程と、 次いで、前記レジスト枠内にソルダペーストを印刷する工程と、 次いで、前記ソルダペーストの上に半導体チップを載置する工程と、 次いで、前記基板を加熱し、前記ソルダペーストを溶かして前記半導体チップを基 板上にソルダ付けする工程とを含むことを特徴とする複合半導体装置の製造方法。 To 1. A substrate, a step of printing a resist frame by a resist, and then, the step of printing the solder paste in the resist frame, then a step of placing the semiconductor chip on the solder paste , then heating the substrate, a method of manufacturing a composite semiconductor device which comprises the step of attaching solder the semiconductor chip on a base plate by dissolving the solder paste.
  2. 【請求項2】前記レジスト枠は、少なくともその一部に、溶融した余分なソルダペーストが流出するための切欠部が形成されている仕切り壁であることを特徴とする請求項1に記載の複合半導体装置の製造方法。 Wherein said resist frame are at least in part, composite of claim 1, excess solder paste melting, characterized in that a partition wall notch portion is formed to flow out the method of manufacturing a semiconductor device.
  3. 【請求項3】前記レジスト枠は、マス目状の半導体チップ収納枠であることを特徴とする請求項1に記載の複合半導体装置の製造方法。 Wherein the resist frame method of producing a composite semiconductor device according to claim 1, characterized in that the grid-shaped semiconductor chip housing frame.
  4. 【請求項4】前記マス目状の半導体チップ用収納枠の線幅は、2mm以下であることを特徴とする請求項1に記載の複合半導体装置の製造方法。 4. A line width of the grid-shaped semiconductor chip for receiving frame method of producing a composite semiconductor device according to claim 1, characterized in that at 2mm or less.
  5. 【請求項5】前記基板は、熱伝導度の良好な導体板であることを特徴とする請求項1に記載の複合半導体装置の製造方法。 Wherein said substrate is a manufacturing method of a composite semiconductor device according to claim 1, characterized in that a good conductor plate of the heat conductivity.
JP12092599A 1999-04-28 1999-04-28 Manufacturing composite semiconductor device Pending JP2000311905A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006216729A (en) * 2005-02-03 2006-08-17 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method thereof
JP2008207207A (en) * 2007-02-26 2008-09-11 Fuji Electric Device Technology Co Ltd Method for solder joining, and method for manufacturing semiconductor device using the same
JP2010212723A (en) * 2010-05-17 2010-09-24 Fuji Electric Systems Co Ltd Method of manufacturing semiconductor device
JP2010533381A (en) * 2007-07-12 2010-10-21 ヴィシャイ ジェネラル セミコンダクター エルエルシーVishay General Semiconductor LLC Subassemblies and forming method comprising the power semiconductor die and the heat sink
WO2012034064A1 (en) * 2010-09-09 2012-03-15 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US20140131877A1 (en) * 2012-11-09 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4600065B2 (en) * 2005-02-03 2010-12-15 富士電機システムズ株式会社 Semiconductor device and manufacturing method thereof
US7781258B2 (en) 2005-02-03 2010-08-24 Fuji Electric Systems Co., Ltd. Manufacturing method of semiconductor device
JP2006216729A (en) * 2005-02-03 2006-08-17 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method thereof
JP2008207207A (en) * 2007-02-26 2008-09-11 Fuji Electric Device Technology Co Ltd Method for solder joining, and method for manufacturing semiconductor device using the same
US8273644B2 (en) 2007-02-26 2012-09-25 Fuji Electric Co., Ltd. Soldering method and method of manufacturing semiconductor device including soldering method
JP2010533381A (en) * 2007-07-12 2010-10-21 ヴィシャイ ジェネラル セミコンダクター エルエルシーVishay General Semiconductor LLC Subassemblies and forming method comprising the power semiconductor die and the heat sink
KR101621105B1 (en) 2007-07-12 2016-05-13 비샤이 제너럴 세미컨덕터 엘엘씨 Subassembly that includes a power semiconductor die and a heat sink and method of forming same
US8796840B2 (en) 2007-07-12 2014-08-05 Vishay General Semiconductor Llc Semiconductor assembly that includes a power semiconductor die located on a cell defined by first and second patterned polymer layers
JP2010212723A (en) * 2010-05-17 2010-09-24 Fuji Electric Systems Co Ltd Method of manufacturing semiconductor device
US8691626B2 (en) 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
WO2012034064A1 (en) * 2010-09-09 2012-03-15 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US20140131877A1 (en) * 2012-11-09 2014-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies
US9312193B2 (en) * 2012-11-09 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies
US9818700B2 (en) 2012-11-09 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies

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