JP2000261305A - Input buffer circuit - Google Patents

Input buffer circuit

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Publication number
JP2000261305A
JP2000261305A JP11065630A JP6563099A JP2000261305A JP 2000261305 A JP2000261305 A JP 2000261305A JP 11065630 A JP11065630 A JP 11065630A JP 6563099 A JP6563099 A JP 6563099A JP 2000261305 A JP2000261305 A JP 2000261305A
Authority
JP
Japan
Prior art keywords
stage buffer
level
signal
input
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11065630A
Other languages
Japanese (ja)
Inventor
Izumi Suzuki
泉 鈴木
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
東芝マイクロエレクトロニクス株式会社
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp, 東芝マイクロエレクトロニクス株式会社, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP11065630A priority Critical patent/JP2000261305A/en
Publication of JP2000261305A publication Critical patent/JP2000261305A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce the path delay of a signal and to improve the transmission speed of the signal by changing the level of operation voltage to be supplied to an initial stage buffer in accordance with the change of the output level of a final stage buffer. SOLUTION: When an input signal A changes from a high level H (2.5 V) to a low level L (0 V), the potential of Vc becomes 2.5 V and Va becomes 2.5 V, When the output signal Z of a final stage buffer 12 becomes 0 V, the PMOS transistor 108 of a leak current preventing circuit 13 is turned off. Thus, supply voltage Vc to an initial stage buffer 11 is supplied through a PMOS transistor 105 and it becomes 3.3 V, Va also becomes 3.3 V, a PMOS transistor 103 is completely turned off and leak current in the final stage buffer 12 does not flow. When the input signal A changes from 0 V to 2.5 V, a PMOS transistor 101 is completely turned off so that leak current in the initial stage buffer 11 does not flow.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an input buffer circuit having a function of shifting the level of an input amplitude voltage and inputting it to an LSI or the like.

[0002]

2. Description of the Related Art Conventionally, this type of input buffer circuit has
When receiving an input signal having an amplitude voltage lower than that of an SI internal (core) power supply, the input signal is level-shifted to prevent a leak current.

FIG. 3 shows a conventional input buffer circuit. First-stage 2.5 that sets thresholds in the same way as a normal input buffer
When an input signal (input amplitude voltage 0 or 1) A is input via a push-pull type buffer 1 of a V power supply, a non-inverted input signal is input to a level shift circuit 2 of a 3.3 V power supply, The input signal whose polarity is inverted by the 2.5 V power supply inverter 3 is also input to the same level shift circuit 2. The level shift circuit 2 shifts the amplitude voltage of 2.5 V to the amplitude voltage of 3.3 V, and outputs the obtained shift signal to the inside through the last-stage buffer 4 having a strong driving force for transmitting the shift signal to the inside of the 3.3 V power supply. .

FIG. 4 is a timing chart for explaining the operation of the conventional input buffer circuit described above. FIG. 4 (a)
When the input signal A as shown in FIG. 4 is input to the first-stage buffer 1, the signal at the point (B) becomes the input signal A as shown in FIG.
, And is input to the level shift circuit 2. On the other hand, the signal at the point B is further inverted in polarity by the inverter 3 and input to the same level shift circuit 2.

As a result, the point (D) of the level shift circuit changes in voltage as shown in FIG.
The point changes in voltage as shown in FIG. Since the signal at the point (C) is input to the final-stage buffer 4,
The final-stage buffer 4 outputs an output signal Z as shown in FIG.
Is output to the inside of an LSI or the like.

Now, the operation of the level shift circuit 2 will be described in more detail. When a high-level “1” of 2.5 V system is input as an input signal, the NMOS transistor 22 is turned on, thereby turning on the PMOS transistor 23.
Turns on. At the same time, since the NMOS transistor 24 is turned off, a high level “1” of the 3.3 V system is output to the final stage buffer 4. At this time, the PMOS transistor 21 is turned off.

When a low level "0" of the 2.5 V system is input as an input signal, the NMOS transistor 22 turns off and the NMOS transistor 24 turns on. As a result, the PMOS transistor 21 turns on and the PMOS transistor 23 turns off. As a result, the low level “0” of the 3.3 V system is output to the final stage buffer 4.

[0008]

Since the conventional input buffer circuit is composed of the first-stage buffer 1, the level shift circuit 2, the inverter 3, and the last-stage buffer 4 as described above, when the number of inverters is one, In a level shift circuit, there are two stages, and in total four stages from receiving an external signal to transmitting it to the inside, the signal path delay is large, and the signal transmission speed is reduced by that amount, so that it is applied to a high-speed interface. There was a problem that was difficult. Further, the conventional level shift circuit 2 is constituted by a push-pull circuit of P-channel and N-channel transistors, and operates so that both the P-channel and N-channel transistors are turned on so that a through current does not flow. There is a problem that the operation is slow and the above-mentioned problems are promoted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and can be applied to a high-speed interface by reducing a signal path delay and improving a signal transmission speed. An input buffer circuit is provided.

[0010]

In order to achieve the above object, the present invention is characterized in that a first stage buffer for inputting and outputting an input signal, and a signal inputted from the first stage buffer are inputted. A final-stage buffer that outputs an output signal having a different level from the input signal, and after the level of the input signal changes, the output level of the final-stage buffer changes in accordance with the level of the input signal. A leakage current prevention circuit for changing an operation voltage level supplied to the first-stage buffer according to the change.

According to the first aspect of the present invention, the first-stage buffer inputs an input signal to the last-stage buffer. The final-stage buffer changes the level of the input signal from, for example, 2.5 V to 3.3.
The output is shifted to the V system. At this time, a leak current occurs due to the level shift of the signal in the first-stage buffer or the last-stage buffer, and the leak current preventing circuit changes the output level of the last-stage buffer in accordance with the level of the input signal. Then, the operation voltage level supplied to the first-stage buffer is changed in accordance with this change to prevent this. Therefore, an input signal can be level-shifted in two stages without introducing a leak current and introduced into an LSI or the like.

The first-stage buffer and the last-stage buffer according to the second aspect of the invention are push-pull buffers that invert the polarity of an input signal and output the inverted signal.

According to a third aspect of the present invention, in the leakage current preventing circuit, when an input signal changes from a high level to a low level,
After the output signal of the last-stage buffer changes from high level to low level, the operating voltage supplied to the first-stage buffer is increased, the input signal changes from low level to high level, and the output signal of the last-stage buffer changes. Is changed from a low level to a high level, control is performed to lower the operating voltage supplied to the first-stage buffer.

According to a fourth aspect of the present invention, in the leakage current prevention circuit, an output signal of the last-stage buffer is input to a gate,
A first P-channel transistor whose source is connected to a first voltage source, a second P-channel transistor and an N-channel transistor are push-pull connected, and the output signal of the last stage buffer is inverted and output. An inverter; and a third P-channel transistor having a gate that receives a signal output from the inverter and having a source connected to a second voltage source.
Is supplied as the operating voltage of the first-stage buffer.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the input buffer circuit of the present invention. The input buffer circuit of this example includes a push-pull type first-stage buffer 11 for receiving an input signal A from the outside, a push-pull type last-stage buffer 12 having a strong driving force for transmitting a signal to the inside of an LSI or the like, and a first-stage buffer. 11 is comprised of a leakage current prevention circuit 13 for changing the operating voltage.

Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. First, as shown in FIG. 2A, the input signal A is at a high level H.
(2.5V) to low level L (0V),
As shown in FIG. 2D, the potential of Vc is 2.5 V, and the PMOS transistor 101 of the first-stage buffer 11
Changes from off to on, the NMOS transistor 102 changes from on to off, and as shown in FIG.
It becomes 5V.

Thus, the PMO of the last-stage buffer 12 is
The S transistor 103 changes from on to off and the NMOS transistor 104 changes from off to on, and the output signal Z goes to a low level L (0 V) as shown in FIG.

When the output signal Z becomes low level L (0 V), the PMOS transistor 10 of the leakage current prevention circuit 3
5 is turned on, the PMOS and NMOS transistors 106 and 107 are turned on and off, and as shown in FIG. 2C, Vb goes to a high level H (3.3 V) and PM
The OS transistor 108 turns off. As a result, the supply voltage Vc to the first-stage buffer 11 is supplied through the PMOS transistor 105 as shown in FIG.
(3.3 V).

As a result, the PMOS of the first stage buffer 11
The voltage applied to the source of the transistor 101 becomes 3.3 V, and as shown in FIG. 2B, Va also becomes 3.3 V, the PMOS transistor 103 is completely turned off, and a leak current flows in the final-stage buffer 12. Disappears.

Next, as shown in FIG. 2A, when the input signal (A) changes from the low level L (0 V) to H (2.5 V), the PMOS and NMOS transistors 101 and 102 of the first-stage buffer 11 are used. Changes from on to off and from off to on, and as shown in FIG.
(0 V).

As a result, the PMO of the last stage buffer 12 is
Since the S and NMOS transistors 103 and 104 are turned on from off and turned off from on, as shown in FIG.
The output signal Z becomes high level H (3.3 V).

When the output signal Z goes high (3.3 V), the PMOS transistor 105 of the leakage current prevention circuit 13 is turned off, and the PMOS and NMOS transistors 106 and 107 are turned on from off and on from off. , As shown in FIG.
(0 V), so that the PMOS transistor 108 is turned on. As a result, as shown in FIG. 2D, Vc becomes 2.5 V, and a voltage of 2.5 V is supplied from the PMOS transistor 108 to the source of the PMOS transistor 101 of the first-stage buffer 11.

As a result, 2.5 V is applied to the drain of the PMOS transistor 101 in the first stage, and the drain is completely turned off, so that no leak current flows in the first stage.

According to the present embodiment, a path for receiving an input signal and transmitting the signal to the inside can be constituted by only two stages of a first stage buffer 11 and a last stage buffer 13 similar to a normal input buffer. The leakage current prevention circuit 13 prevents the leakage current generated when the amplitude voltage of the input signal is shifted from 3.3 V to 3.3 V, so that the signal path delay can be reduced and the signal transmission speed of the input buffer circuit can be improved.

Furthermore, the conventional level shift circuit, which operates slowly, is omitted, and the level shift is performed in two stages, the first stage buffer 11 and the last stage buffer 13, which operate fast.
Since the signal transmission speed of the circuit can be further improved, the input buffer circuit of this example can be applied to a high-speed interface.

[0026]

As described above in detail, according to the input buffer circuit of the present invention, the signal transmission path for receiving an input signal and then transmitting the signal to the inside has two stages similar to a normal input buffer. , The signal transmission speed can be improved, and the present invention can be applied to a high-speed interface.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an input buffer circuit of the present invention.

FIG. 2 is a timing chart showing an operation of the input buffer circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration example of a conventional input buffer circuit.

FIG. 4 is a timing chart showing an operation of the input buffer circuit shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 First stage buffer 12 Last stage buffer 13 Leakage current prevention circuit 101, 103, 105, 106, 108 PMOS transistor 102, 104, 107 NMOS transistor

Claims (4)

    [Claims]
  1. A first-stage buffer for inputting and outputting an input signal; a last-stage buffer for receiving a signal input from the first-stage buffer and outputting an output signal having a different level from the input signal; After the output level of the last-stage buffer changes in accordance with the level of the input signal, and then changes the operating voltage level supplied to the first-stage buffer according to the change. An input buffer circuit, comprising:
  2. 2. The input buffer circuit according to claim 1, wherein the first-stage buffer and the last-stage buffer are push-pull buffers that invert the polarity of an input signal and output the inverted signal.
  3. 3. The leak current prevention circuit supplies the first-stage buffer after the input signal changes from a high level to a low level and the output signal of the last-stage buffer changes from a high level to a low level. After the input signal changes from a low level to a high level and the output signal of the last-stage buffer changes from a low level to a high level, control is performed to lower the operating voltage supplied to the first-stage buffer. 3. The input buffer circuit according to claim 1, wherein:
  4. 4. A leak current prevention circuit comprising: a first P-channel transistor having a gate receiving an output signal of the last-stage buffer and a source connected to a first voltage source; and a second P-channel transistor. And an N-channel transistor, which is push-pull connected, an inverter that inverts the polarity of the output signal of the last-stage buffer and outputs the inverted signal, and a signal output from the inverter is input to a gate.
    A third P-channel transistor whose source is connected to a second voltage source, wherein a voltage output from the drains of the first and third P-channel transistors is supplied as an operating voltage of the first-stage buffer. 4. The input buffer circuit according to claim 1, wherein
JP11065630A 1999-03-11 1999-03-11 Input buffer circuit Withdrawn JP2000261305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11065630A JP2000261305A (en) 1999-03-11 1999-03-11 Input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11065630A JP2000261305A (en) 1999-03-11 1999-03-11 Input buffer circuit

Publications (1)

Publication Number Publication Date
JP2000261305A true JP2000261305A (en) 2000-09-22

Family

ID=13292541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11065630A Withdrawn JP2000261305A (en) 1999-03-11 1999-03-11 Input buffer circuit

Country Status (1)

Country Link
JP (1) JP2000261305A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009510847A (en) * 2005-09-30 2009-03-12 モサイド・テクノロジーズ・インコーポレーテッド Semiconductor integrated circuit having a leakage current reduction mechanism
JP2010252330A (en) * 2009-04-13 2010-11-04 Taiwan Semiconductor Manufacturing Co Ltd Level shifter, integrated circuit, system, and method for operating level shifter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009510847A (en) * 2005-09-30 2009-03-12 モサイド・テクノロジーズ・インコーポレーテッド Semiconductor integrated circuit having a leakage current reduction mechanism
JP2010252330A (en) * 2009-04-13 2010-11-04 Taiwan Semiconductor Manufacturing Co Ltd Level shifter, integrated circuit, system, and method for operating level shifter
US8629704B2 (en) 2009-04-13 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifters, integrated circuits, systems, and methods for operating the level shifters
US9071242B2 (en) 2009-04-13 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifters, methods for making the level shifters and methods of using integrated circuits

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Effective date: 20060606