JP2000241798A - Active matrix type liquid crystal display device and its drive method (reset drive) - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device having high contrast and rapid response/wide view angle that 'step response' is not made, and without lowering luminance an increase in power consumption the increase in a display defect due to a short circuit between wiring and to provide its drive method. SOLUTION: This device is provided with plural first scanning lines 2 arranged parallel onto a first substrate, plural second scanning lines 3 arranged between adjacent wiring of plural first scanning lines 2, plural signal lines 1 arranged so as to intersect with the scanning lines 2 and 3, a second substrate arranged parallel to the first substrate, a liquid crystal layer held between the first substrate and the second substrate, a signal writing TFT element 4 and a resetting TFT element 5. Then, the TFT 4 is connected between the first scanning line 2 and the signal line 1 and between the first scanning line 2 and a pixel electrode, and is controlled by the elected first scanning line 2, and the TFT 5 is connected between the second scanning line 2 and the pixel electrode and between the second scanning line 3 and the first scanning line 2 of the preceding stage of the first scanning line 2, and is controlled by the elected second scanning line 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device using a ferroelectric liquid crystal and an antiferroelectric liquid crystal, and a driving method thereof.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display (TFT-LCD) using a TFT (thin film transistor) as a switching element, a liquid crystal material is required to realize a faster response speed and a wider viewing angle than a TN (twisted nematic) liquid crystal. Some methods using a ferroelectric liquid crystal or an antiferroelectric liquid crystal have been studied.

When a liquid crystal having spontaneous polarization such as a ferroelectric liquid crystal or an antiferroelectric liquid crystal (more generally, a liquid crystal of a chiral smectic C phase or its sub phase) is driven by a TFT, the response time of the liquid crystal is reduced. Is longer than the writing time, it is known that a phenomenon in which the holding voltage decreases due to the anti-electric field occurs (Hartmann: J. Appl.
Phys. 66, 1132 (1989)). This decrease in the holding voltage is a so-called insufficient writing, causes a decrease in the effective applied voltage, and lowers the contrast ratio, which is a serious problem in practical use.

[0004] As another problem, when the absolute value of the signal voltage changes at a certain frame, a "step response", that is, a phenomenon in which the transmitted light amount settles to a steady light amount while repeating light and dark over several frames ( Verhulst et al .: IDRC '94.
Digest, 377 (1994)).

The above problem can be solved by using a liquid crystal material which is sufficiently fast in driving at a low voltage or at a temperature slightly lower than room temperature, and has a response time shorter than the writing time. do not do. The realization of high speed especially in the low temperature region is questioned in the future. Further, the liquid crystal display device is required to have a larger screen and higher definition, but this necessarily involves shortening one horizontal period. Therefore, it is difficult to solve this problem only by improving the liquid crystal material.

As a solution to the "step response", a method of performing a reset operation of writing 0 V immediately before writing is known. As this method, a method using a TFT or a TFD (thin film diode) has been disclosed, but these methods allocate a part of the writing time to the reset operation. Therefore, although the "step response" is solved, the actual write time is reduced unless the number of lines is reduced.
For this reason, the contrast is not sufficiently improved.

Further, when the writing time is shortened due to the high definition, the writing time is further shortened due to the reset operation, and the insufficient writing becomes serious. TFD
Although it is possible to perform a reset operation during writing of another line by using, the TFD has a problem that it is difficult to suppress variations in element characteristics of the entire display element, and is not suitable for practical use. As described above, the conventional liquid crystal material and the reset method cannot solve the contrast reduction and the “step response” due to the anti-electric field.

In order to solve the above problem, a reset TFT is connected to the pixel electrode separately from the signal writing TFT, and the reset TFT is selected before the timing of selecting the signal writing TFT. By resetting the potential of the pixel electrode, the reset can be performed without substantially shortening the writing time.

The pixel structure for resetting using a TFT different from the signal writing TFT includes a scanning line for controlling the reset TFT and a scanning line for controlling the signal writing TFT. And a structure in which a scanning line for controlling a reset TFT is provided separately from a scanning line for controlling a signal writing TFT (Okumura et al., Published Japanese Patent Laid-Open No. 9-265112). These will be described with reference to the drawings.

FIG. 8 is a circuit diagram showing a structure of a first conventional example formed on a first substrate. In this structure, the reset scanning line is also used as the scanning line 7 preceding the signal writing scanning line 2. The pixel electrode 6 is connected to the signal writing TFT 4 and the reset TFT 5, and the Cs line 1
A storage capacitor (Cs) 9 is formed between the storage capacitor and the storage capacitor.

The driving waveform of the scanning line in this structure is shown in FIG.
It becomes as shown in. Here, reference numeral 11 denotes a driving waveform of the scanning line 7 selected before the scanning line 2 for signal writing, and reference numeral 12 denotes a driving waveform of the scanning line 2 for signal writing. Here Tfram
e represents one frame time, and the rewriting rate is 60 Hz.
Is 16.7 ms. Tgon represents one horizontal time, which is a time obtained by dividing one frame time by the number of signal writing scanning lines 2. Vgon is a signal writing TF for writing the voltage applied to the signal line 1 to the pixel electrode 6.
Vgoff represents the voltage applied to the signal writing scanning line 2 during the period of selecting T4, and Vgoff represents the voltage applied to the signal writing scanning line 2 during the other period. The difference between the voltage VCs applied to the Cs line 10 and the potential Vcom applied to the common electrode formed on the second substrate is 1 V or less.

In this structure, the reset scanning line is also used as the scanning line 7 preceding the scanning line 2 for writing the signal, and the reset TFT 5 is used during the period in which the scanning line 7 preceding the scanning line 2 is selected. The potential VCs of the Cs line 10 is
And a reset operation is performed. In this case, the resetting period is equal to one horizontal time Tgon.
For this reason, if one horizontal time is shortened due to high definition, the reset time cannot be sufficiently secured, and only an incomplete reset can be performed. Therefore, it is difficult to completely eliminate the step response.

FIG. 10 is a circuit diagram showing the structure of the second conventional example. In this structure, the reset scanning line 3 is formed substantially parallel to the signal writing scanning line 2. The pixel electrode 6 is composed of a signal writing TFT 4 and a reset TFT 5
To form a storage capacitor (Cs) 9 with the Cs line 10. Further, a potential VCs that is substantially the same as the potential Vcom applied to the common electrode formed on the second substrate or is higher by about 0.5 to 1 V is applied to the Cs line 10.

The driving waveform of the scanning line in this structure is shown in FIG.
As shown in FIG. Here, 11 denotes a driving waveform of the scanning line 7 selected before the signal writing scanning line 2, 12 denotes a driving waveform of the signal writing scanning line 2, and 13 denotes a driving waveform of the reset scanning line 3. . Vron is the reset TFT
5, a voltage applied to the reset scanning line 3 during the period Tron, and Vroff represents a voltage applied to the reset scanning line 3 during the other periods. Reset TFT5
During the period in which is selected, the reset TFT 5
, The potential VCs of the Cs line 10 is written to the pixel electrode 6 and the reset operation is performed. However, since the period Tron during which the reset TFT 5 is selected can be longer than one horizontal time, the signal writing TFT 4 Thus, before writing a signal, the pixel potential 6 can be made equal to the potential VCs of the Cs line 10, and reset can be performed so as to eliminate the step response. On the other hand, as compared with the first conventional example, the scanning line for signal writing 2, the scanning line for resetting 3, and the Cs line 10 are all independent, and the ratio of the area through which light can be transmitted because the number of wirings is increased. Since the aperture ratio is reduced, the brightness is reduced, the power consumption of the backlight is increased, or a display failure due to a short circuit between wirings is likely to occur.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an active matrix type liquid crystal display device using a ferroelectric liquid crystal or an antiferroelectric liquid crystal, in which the luminance is reduced, the power consumption is increased, and a display due to a short circuit between wirings. An object of the present invention is to provide a liquid crystal display device having a high response speed and a wide viewing angle in which a high contrast can be obtained without increasing a defect and a "step response" is not observed.

[0016]

According to the present invention, there is provided a first substrate, a plurality of first scanning lines arranged in parallel on the first substrate, and a plurality of first scanning lines adjacent to the plurality of first scanning lines. A plurality of second scanning lines arranged between the wirings, and a plurality of signal lines arranged to intersect the plurality of first scanning lines and the plurality of second scanning lines; and A second substrate disposed in parallel with the substrate, a common electrode formed on the second substrate, a liquid crystal layer sandwiched between the first substrate and the second substrate, and signal writing. TFT element for reset and TF for reset
A T element, wherein the signal writing TFT is connected between the first scanning line and the signal line and the pixel electrode, and is controlled by the selected first scanning line, and the reset TFT Is connected between the second scanning line, the pixel electrode and a first scanning line preceding the first scanning line, and is controlled by a selected second scanning line. An active matrix type liquid crystal display device is provided.

Further, the invention is characterized in that before the period in which the first scanning line is selected, the second TFT for controlling the reset TFT connected to the signal writing TFT via the pixel electrode is provided. A scanning line is selected, and during a period in which a scanning line next to the second scanning line is selected, a potential applied to the first scanning line and a common electrode formed on the second substrate are applied. 2. The method according to claim 1, wherein the difference between the applied potentials is 1 V or less.

In the present invention, a particularly great effect is exhibited when the liquid crystal layer contains a liquid crystal of a chiral smectic C phase or a subphase thereof.

[0019]

Embodiments of the present invention will be specifically described below with reference to the drawings.

In the present invention, the signal writing time is sufficiently secured without devoting to the reset time by performing the reset operation of the subsequently selected scanning line during the selection of the specific scanning line (during the signal writing time). And the number of lines can be maintained without loss. Thereby, by ensuring a sufficient writing time, the contrast can be improved, and high definition can be achieved. In addition, the reset time can be made longer independently of the signal writing time, and the problem of "step response" can be solved.

FIG. 1 is a circuit diagram showing the structure of the first embodiment. In this structure, the reset scanning line 3 is formed substantially parallel to the signal writing scanning line 2. The signal writing TFT 4 is connected between the signal writing scanning line 2, the signal line 1 and the pixel electrode 6 and controlled by the signal writing scanning line 2, and the reset TFT 5 is connected to the reset scanning line 3 and the pixel electrode 6. 6 is connected between the scanning line 7 before the signal writing scanning line 2 and is controlled by the reset scanning line 3. A storage capacitor (Cs) 9 is formed between the pixel electrode 6 and the scanning line 7 in the preceding stage of the signal writing scanning line 2.

The driving waveform of the scanning line in this structure is shown in FIG.
It becomes as shown in. Here, 11 is a driving waveform of the scanning line 7 selected before the scanning line 2 for signal writing, 12 is a driving waveform of the scanning line 2 for signal writing, 13 is a driving waveform of the scanning line 3 for resetting, Reference numeral 14 denotes a driving waveform of the scanning line 8 selected after the reset scanning line 3. Here Tfram
e represents one frame time, and the rewriting rate is 60 Hz.
Is 16.7 ms. Tgon represents one horizontal time, which is a time obtained by dividing one frame time by the number of signal writing scanning lines 2. Vron is the reset TFT5
Represents the voltage applied to the reset scanning line 3 during the period Tron, and Vroff represents the voltage applied to the scanning line 3 during other periods. Vgon denotes a voltage applied to the signal writing scanning line 2 during a period when the signal writing TFT 4 is selected in order to write the voltage applied to the signal line 1 to the pixel electrode 6, and Vr denotes a reset scanning line. The voltage applied to the signal writing scanning line 2 during the period in which the scanning line 8 at the stage following the third is selected, and Vgoff represents the voltage applied to the signal writing scanning line 2 during the other periods. Reset scan line 3
The difference between the voltage Vr applied to the signal writing scanning line 2 and the potential Vcom applied to the common electrode formed on the second substrate during the period when the next scanning line is selected is 1 V or less. .

During a period Tron during which the reset TFT 5 is selected, the potential Vr of the scanning line 7 preceding the signal writing scanning line 2 is written to the pixel electrode 6 by the reset TFT 5, and the reset operation is performed. Reset TFT5
Can be taken longer than one horizontal time, the pixel potential 6 is changed to the potential Vr of the scanning line 7 before the signal writing scanning line 2 before the signal is written by the signal writing TFT 4. Can be equal to Immediately after the period in which the reset TFT 5 is selected ends,
The pixel potential 6 drops due to the parasitic capacitance of the reset TFT 5, but the magnitude is usually 1 V or less. If Vr is selected such that the pixel potential 6 after dropping becomes equal to the potential Vcom applied to the common electrode formed on the second substrate,
It is possible to reset so as to eliminate the step response.

As an array configuration corresponding to the present invention, there is a configuration as shown in FIGS. FIG. 3 is a schematic diagram showing the entire array configuration, and FIG. 4 is an enlarged view of a pixel portion of the array configuration shown in FIG. It is desirable that the direction in which the scanning line for signal writing and the scanning line for resetting are drawn out face each other because the number of intersections of the wirings is reduced when connecting the scanning line to the driving element. No problem.

In the present invention, a great effect can be obtained when a liquid crystal of a chiral smectic C phase or a sub-phase thereof (for example, a ferroelectric liquid crystal or an antiferroelectric liquid crystal) is used as a liquid crystal material. This is because the reversal current accompanying the reversal of the spontaneous polarization of the liquid crystal is suppressed. However, the present invention can be applied to a liquid crystal display element of another display method. Here, the secondary phases of the chiral smectic C phase include a ferroelectric phase (Sc *), an antiferroelectric phase (Sc _A *), a ferrielectric phase (Scγ *), and other phases (Scα *, Sc).
_{β *, FI H, FI L} , AF, meaning the Sc _I, etc.).

In the present invention, a glass substrate, a plastic substrate, a resin film, or the like can be used as the substrate, and the materials such as an alignment film, an electrode, a spacer, and a sealant are those commonly used in liquid crystal display devices. Can be used.

Next, an embodiment performed to clarify the effect of the present invention will be described. (Example 1) A liquid crystal display device represented by the circuit diagram shown in FIG. 1 and having the array configuration shown in FIGS. 3 and 4 was manufactured. The number of signal lines in the array is 1024 × 3, and the number of scanning lines for signal writing is 768.
XGA of the book. At this time, a thresholdless antiferroelectric liquid crystal A (Fukuda: As) having a spontaneous polarization of 150 nC / cm ² , a response time of 100 μs, and a saturation voltage of 5 V was used as a liquid crystal material.
ia Display, 95 digest: 61 (1
995)), using a TFT as the active element,
As an FT drive system, an XGA with a maximum applied voltage of ± 6 V and a selection time Tgon of a signal writing scanning line of 21 μs was used. In this array, the aperture ratio, which represents the proportion of the light transmitting portion of the pixel portion, was 60%, and the light transmittance of the cell was 8%.

This liquid crystal display device was driven by the driving waveforms shown in FIG. 2, and was driven including a reset operation. The reset voltage is 0.5 V from the common voltage.
A time Tr for selecting a reset scanning line with a high voltage is five times the selection time Tgon for the signal writing scanning line.
105 μs. As a result, the contrast ratio is 50: 1.
Was obtained, and no afterimage due to the step response was observed. Comparative Example 1 A liquid crystal display device having an array configuration shown in the circuit diagram of FIG. 11 was manufactured. The liquid crystal material, active element, and drive system were the same as in Example 1.
The liquid crystal display device was driven including a reset operation simultaneously with the selection of the previous line as shown in FIG. As a result, the contrast ratio was as low as 15: 1, and an afterimage due to the step response was observed. Comparative Example 2 A liquid crystal display device having an array configuration shown in the circuit diagram of FIG. 13 was manufactured. The liquid crystal material, active element, and drive system were the same as in Example 1. About this liquid crystal display device,
Driving including a reset operation was performed simultaneously with the selection of the previous line as shown in FIG.

This liquid crystal display device was driven by the driving waveforms shown in FIG. 14, and was driven including a reset operation. The time Tr for selecting the reset scan line is Tr
Is 105 μs, which is five times the selection time Tgon of the scanning line for signal writing. As a result, the contrast ratio 5
0: 1 was obtained, and no afterimage due to the step response was observed. On the other hand, in this array, the aperture ratio indicating the ratio of the light transmitting portion in the pixel portion was 45%, and the light transmittance of the cell was 6%. As a result, the power consumption of the backlight increased by 30% or more. (Embodiment 2) FIG.
A liquid crystal display device having an array configuration represented by a circuit diagram shown in FIG. The liquid crystal material, active element, and drive system were the same as in Example 1. In this array, the aperture ratio, which represents the ratio of the light transmitting portion of the pixel portion, was 68%, and the light transmittance of the cell was 9%.

This liquid crystal display device was driven by the drive waveforms shown in FIG. 2 and was driven including a reset operation. The reset voltage is 0.5 V from the common voltage.
A time Tr for selecting a reset scanning line with a high voltage is five times the selection time Tgon for the signal writing scanning line.
105 μs. As a result, the contrast ratio is 40: 1.
Was obtained, and no afterimage due to the step response was observed.

[0031]

As described above, according to the present invention,
In an active matrix type liquid crystal display device using a ferroelectric liquid crystal or an antiferroelectric liquid crystal, high contrast can be obtained without a decrease in luminance, an increase in power consumption, and an increase in display failure due to a short circuit between wirings. A liquid crystal display device having a high-speed response and a wide viewing angle in which no "step response" is observed can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a pixel portion of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a driving method of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing the entire array configuration according to the first embodiment of the present invention.

FIG. 4 is a diagram of a pixel unit of the array according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a pixel portion of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a diagram of a pixel portion of an array according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a method for driving a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a first conventional example.

FIG. 9 is a diagram for explaining a driving method of a first conventional example.

FIG. 10 is a circuit diagram illustrating a second conventional example.

FIG. 11 is a diagram illustrating a driving method according to a second conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 signal line 2 signal writing scanning line 3 reset scanning line 4 signal writing TFT 5 reset TFT 6 pixel electrode 7 scanning line selected before signal writing scanning line 8 8 A scanning line selected after the reset scanning line 9 9... Auxiliary capacitance (Cs) 10... A Cs line 11... A scanning line 7 selected before the signal writing scanning line 2.
12 ... Drive waveform of signal writing scanning line 2 13 ... Driving waveform of reset scanning line 3 14 ... Driving waveform of scanning line 8 selected next to reset scanning line 3

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/36 3/36 G02F 1/136 500 (72) Inventor Tsuyoshi Ito Yokohama, Kanagawa 33, Shinisogo-cho, Isogo-ku, Toshiba, Japan Toshiba Production Technology Research Institute (72) Inventor Haruhiko Okumura 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in Toshiba Production Technology Research Lab. JA24 JB23 JB43 NA05 QA13 QA14 2H093 NA15 NA16 NA43 NB13 NC34 NC35 ND04 ND13 ND32 NE03 NF19 NF20 NH15 5C006 AA11 AC02 AC11 AC22 AF42 BA11 BB15 BC03 BC06 FA00 FA24 FA47 5C080 AA10 BB05 DD03 JJ01 EE03 EE25

Claims (3)

[Claims] 1. A first substrate, a plurality of first scanning lines disposed in parallel on the first substrate, and a plurality of first scanning lines disposed between adjacent wirings of the plurality of first scanning lines. A plurality of second scanning lines, a plurality of signal lines arranged so as to intersect the plurality of first scanning lines and the plurality of second scanning lines, and a plurality of signal lines arranged in parallel with the first substrate. A second substrate, a common electrode formed on the second substrate, a liquid crystal layer sandwiched between the first substrate and the second substrate, and a signal writing TF.
A T element and a reset TFT element, wherein the signal writing TFT is connected between the first scanning line and the signal line and the pixel electrode, and is controlled by the selected first scanning line. The reset TFT is connected between the second scanning line, the pixel electrode and a first scanning line preceding the first scanning line, and is controlled by a selected second scanning line. An active matrix type liquid crystal display device characterized in that: 2. Prior to a period in which the first scanning line is selected, the second scanning line that controls the reset TFT connected via the pixel electrode and the signal writing TFT is selected. And a potential applied to the first scanning line and a potential applied to a common electrode formed on the second substrate during a period in which a scanning line next to the second scanning line is selected. 2. The driving method of an active matrix type liquid crystal display device according to claim 1, wherein the difference is 1 V or less. 3. The driving method of an active matrix type liquid crystal display device according to claim 1, wherein the liquid crystal layer contains liquid crystal of a chiral smectic C phase or a sub phase thereof.