JP2000236081A - Photoelectric conversion element and photoelectric conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric converting element and a photoelectric converting device which can be operated at high speed. SOLUTION: This photoelectric conversion device is provided with a light- receiving part and a transfer part, which transfers the charge stored in the light-receiving part to a read-out part, and the light-receiving part has the impurity concentration gradient so that potential becomes lower as it approaches the transfer part. It is desirable that the light-receiving part be an embedded photodiode 101. As a result, the signal charge can be completely transferred from a light-receiving part to a read-out part in a short time, and the photoelectric conversion device using the element can be operated at a high speed, and a residual image is not generated even if the size of the light-receiving part is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device.

[0002]

2. Description of the Related Art In recent years, photoelectric conversion devices, such as a solid-state imaging device and a line sensor, for photoelectrically converting incident light into an image or sensing have been put to practical use. As these photoelectric conversion devices, devices that use a photoelectric conversion element having a buried photodiode (hereinafter, referred to as a BPD) as a light receiving unit as a configuration are actively used.

[0003] A BPD has a diffusion layer (hereinafter referred to as a charge storage layer) for storing photoelectrically converted charges under a depletion preventing layer disposed on a semiconductor surface. For this reason, even if the charge storage layer is completely depleted, the semiconductor surface is not depleted, and the dark current due to the interface order is small. Further, since the PN junction surrounds the charge storage layer, there is an advantage that the junction capacitance is large and more charges can be stored.

[0004] A conventional BPD will be described using a solid-state image sensor as an example.
Will be described. FIGS. 8A and 8B are diagrams showing a unit pixel of a conventional solid-state imaging device, where FIG. 8A is a plan view, and FIG.
FIG. 1C is a cross-sectional view along D ′, FIG. 2C is a cross-sectional view along D3-D3 ′, and FIG. 2D is a potential diagram along D2-D2 ′ in FIG. Note that the solid-state imaging device is a photoelectric conversion device in which a plurality of unit pixels that are photoelectric conversion elements are arranged.

The solid-state image pickup device includes a BPD 101 that generates and accumulates electric charge according to incident light, a junction field effect transistor (hereinafter, referred to as JFET) 102 that outputs a signal corresponding to the electric charge received from the BPD, It has a reset drain (hereinafter referred to as RSD) for discharging unnecessary charges from the control region (gate regions 203 and 204) of JFET 102 after signal output. In this figure, the aluminum wiring connected to the source of the JFET 102 and the RSD is omitted.

The BPD 101 includes a depletion preventing layer (an N-type layer on the front surface) 205 in order from the front surface to the rear surface of the semiconductor substrate.
A P-type charge storage layer 206 and an N-type Si substrate 201 are provided. The JFET 102 includes an N + type source region 207, an N type drain region 208, a surface P type gate region 203, a deep P type gate region 204, and an N type channel region 209, and the P type gate regions 203 and 204 are N type. The channel 209 is sandwiched from above and below.

The transfer electrode (hereinafter referred to as TG) 103
From the PD 101 to the gate regions 203 and 2 of the JFET 102
04 to transfer the charge to the BPD 101
P-type region 206 and gate P-type region 2 of JFET 102
03 is a source / drain P channel MOSFE
T. The reset gate (hereinafter referred to as RSG) 105 is connected to the gate region 203 of the JFET 102,
04 to the RSD 104.
P channel M in which P region 202 of SD 104 and P type gate region 203 of JFET 102 are the source / drain
It constitutes an OSFET. When a pulse voltage is applied to RSG 105, RSD 104 is electrically connected to gate regions 203 and 204 of JFET 102, and gate regions 203 and 204 are initialized to the voltage of RSD 104.

[0008] Such a solid-state image sensor has a BP for each pixel.
Since it has D and an amplifying element, it has low noise and high sensitivity. Here, the light receiving section of the photoelectric conversion device has been described as a BPD. However, an arrangement in which a photodiode including a semiconductor substrate and a light-receiving part diffusion layer is arranged in a light-receiving part is also known.

[0009]

In recent years, high-sensitivity elements have been demanded in various fields, and it has been proposed to increase the area of a light-receiving portion in order to increase the sensitivity. However, as the area of the light receiving section increases, the speed of charge transfer from the light receiving section to the reading section decreases. When the size is further increased, transfer cannot be completed completely within a prescribed readout period, and the remaining charge is observed as an afterimage.

Here, the phenomenon of the afterimage will be described. FIG.
(D) is a potential diagram along D2-D2 'in (b) of FIG. Here, the gate regions 203 and 204 of the JFET 102 are reset to the reference voltage, and the TG 103
Shows the potential when is turned on (when set to a low level). As can be seen from this figure, BPD101
On the transfer gate side and the opposite side, the BPD has a potential gradient. The signal charge moves to a lower potential by drift. Therefore, if there is a potential gradient, the signal charges can easily (ie, rapidly) move to the lower potential.

However, there is no potential gradient near the center of the BPD 101 and the BPD 101 is flat. Therefore, it takes a relatively long time for the signal charge accumulated in this portion to reach the control region of the JFET 102 through the transfer gate 103 without drift component due to the electric field. Therefore, complete transfer cannot be performed within the specified readout period,
Signal charges remain on the BPD 101. If the light receiving area is further increased, complete transfer cannot be performed even if the readout period is lengthened indefinitely.

As described above, in the conventional photoelectric conversion device, there is a limit to an increase in the pixel area, and it has been desired to increase the speed of charge transfer. The present invention has been made in view of such a problem, and provides a photoelectric conversion element and a photoelectric conversion device that enable complete transfer even with a large-area light receiving unit.

[0013]

According to a first aspect of the present invention, there is provided a light receiving unit disposed on a semiconductor substrate for generating and accumulating electric charges according to incident light, and reading out the electric charges stored in the light receiving units. Wherein the light receiving unit has an impurity concentration gradient, wherein the transfer unit transfers the transfer signal to the transfer unit, and the read unit generates a signal corresponding to the charge transmitted from the transfer unit. It is characterized in that the potential decreases as approaching the part.

In general, when there is a potential gradient, the electric charge placed there moves at a high speed to a lower potential due to electric field drift. According to the configuration of the first aspect, the potential gradient that monotonously decreases from the end of the light receiving portion toward the transfer electrode is formed at the time of reading the charge, so that the charge can be completely and rapidly transferred. According to a second aspect of the present invention, a light receiving unit is provided on a semiconductor substrate of a first conductivity type and generates and accumulates charges according to incident light, and transfers the charges accumulated in the light receiving unit to a readout unit. A photoelectric conversion element comprising: a transfer unit that performs a transfer operation; and a readout unit that generates a signal corresponding to the charge transmitted from the transfer unit, wherein the light receiving unit includes a first conductivity type depletion prevention layer, and
A second conductivity type charge storage layer provided in contact with the depletion prevention layer and below the depletion prevention layer, wherein the depletion prevention layer has an impurity concentration It has a gradient, and the impurity concentration of the first conductivity type becomes higher as the distance from the transfer section increases.

[0015] The invention described in claim 3 is the first invention.
A light-receiving unit that is arranged on a conductive semiconductor substrate and generates and accumulates charges according to incident light; a transfer unit that transfers the charge accumulated in the light-receiving unit to a readout unit; The readout unit that generates a signal in accordance with the charged charge, wherein the light receiving unit is a first conductivity type depletion preventing layer, and the depletion preventing layer is in contact with the depletion preventing layer. A buried photodiode comprising a second conductivity type charge storage layer provided below the prevention layer, wherein the charge storage layer has an impurity concentration gradient, and the second conductivity type impurity concentration is It is characterized in that the density decreases as the distance from the transfer unit increases.

The invention described in claim 4 is the first invention.
A light-receiving unit that is arranged on a conductive semiconductor substrate and generates and accumulates charges according to incident light; a transfer unit that transfers the charge accumulated in the light-receiving unit to a readout unit; The readout unit that generates a signal in accordance with the charged charge, wherein the light receiving unit is a first conductivity type depletion preventing layer, and the depletion preventing layer is in contact with the depletion preventing layer. A buried photodiode comprising a second conductivity type charge storage layer provided below the prevention layer, wherein the impurity concentration of the semiconductor substrate below the buried photodiode has a concentration gradient, and The density is low at a portion adjacent to the transfer portion, and becomes high as the distance from the transfer portion increases.

According to the second to fourth aspects of the present invention, a buried photodiode is arranged in the light receiving portion, and the buried photodiode has the same potential gradient as in the first aspect. The buried photodiode includes a depletion prevention layer, a charge storage layer, and semiconductor regions of a semiconductor substrate. In order to lower the potential on the transfer portion side, any one of these semiconductor regions may have an impurity concentration gradient. Of course, the impurity concentration of the plurality of semiconductor regions of the buried photodiode may have a concentration gradient.

According to this configuration, a potential gradient that monotonically decreases from the end of the light receiving section toward the transfer electrode is formed at the time of charge reading, so that the charges in the light receiving section are completely and rapidly transferred by the electric field drift. Further, since the light receiving section uses an embedded photodiode, the dark current is small and the accumulated dose is large. According to a fifth aspect of the present invention, in the photoelectric conversion element according to any one of the first to fourth aspects, the concentration gradient changes stepwise. In this case, the concentration gradient of the light receiving section can be easily obtained.

According to a sixth aspect of the present invention, in the photoelectric conversion element according to any one of the first to fifth aspects, the read section has a transistor for amplifying the charge. With this configuration, not only high-speed operation can be performed, but also an amplifying transistor is provided in the reading unit, so that a low-noise and high-sensitivity photoelectric conversion element can be provided.

According to a seventh aspect of the present invention, in the photoelectric conversion element according to the sixth aspect, the transistor is a junction field effect transistor.
The junction field effect transistor has good matching with the buried photodiode because the gate is provided by a semiconductor. For this reason, according to the structure of claim 7, the manufacture is easy, and the yield is accordingly improved.

According to another aspect of the present invention, there is provided a photoelectric conversion device in which the photoelectric conversion elements according to any one of the first to seventh aspects are arranged in a matrix as unit pixels, and are arranged in an XY manner.
A signal is output from each pixel by an address scanning circuit. When the photoelectric conversion elements are arranged in a matrix, an image sensor or the like that generates an image signal can be obtained.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a drawing showing a unit pixel (photoelectric conversion element) of a photoelectric conversion device according to a first embodiment of the present invention. Figure,
(B) is a sectional view along A1-A1 ', (c) is A2-
A sectional view along A2 ', (d) is A3-A3' of (b)
FIG.

The unit pixel includes a buried photodiode (BPD) 10 that generates and accumulates electric charge according to incident light.
1 and a junction field-effect transistor (hereinafter referred to as JFET) that outputs a signal corresponding to the charge received from the BPD 101.
102), and the unnecessary charge after signal output is J
Control region of FET 102 (gate regions 203 and 204)
And a reset drain (hereinafter referred to as RSD) for discharging from the memory. In this figure, the source contact portion 106 of the JFET 102 and the contact portion 1 of the RSD 104
The aluminum wiring connected to 07 is omitted.

The transfer electrode (hereinafter referred to as TG) 103
This is for transferring the charge accumulated in the PD 101 to the gate regions 203 and 204 of the JFET 102,
P-type region 206 of D101 and gate P of JFET 102
P-channel M in which the mold region 203 becomes the source / drain
It constitutes an OSFET. The JFET 102 is a reading unit that outputs a signal according to the transmitted charge.
N + type source region 20 having an impurity concentration of 5 × 10 ²⁰ cm ⁻³
7. N-type drain region 2 having an impurity concentration of 5 × 10 ¹⁸ cm ⁻³
08, an impurity concentration of 5 × 10 ¹⁷ cm surface P-type gate region 203 of ^-3, an impurity concentration of 5 × 10 ¹⁷ cm ^-3 deep P-type gate region 204, N-type channel region having an impurity concentration 1 × 10 ¹⁷ cm-3 209, the surface P-type gate region 203 and the deep P-type gate region 2 which are electrically connected.
04 has a structure sandwiching the N-type channel 209 from above and below. Then, a signal amplified according to the charge in the gate region is output from the N + type source region 207.

Reset gate (hereinafter referred to as RSG) 10
5 transfers charges from the gate regions 203 and 204 of the JFET 102 to the RSD 104;
4 P region 202 (impurity concentration 5 × 10 ¹⁷ cm ⁻³ ) and J
The P-type gate region 203 of the FET 102 constitutes a P-channel MOSFET serving as a source / drain. R
When a pulse voltage is applied to the SG 105, the RSD 104
And the gate regions 203 and 204 of the JFET 102 are electrically connected.
4 is initialized.

The BPD 101 includes a depletion preventing layer (an N-type layer on the front surface) 205 in order from the front surface to the rear surface of the semiconductor substrate.
A P-type charge storage layer 206 having an impurity concentration of 3 × 10 ¹⁶ cm ⁻³ ,
The N-type substrate 201 has an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ . The depletion prevention layer is electrically connected to the substrate 201. Further, the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ , 2 × 1
0 ¹⁷ cm ⁻³ , 3 × 10 ¹⁷ cm ⁻³ three regions 205a,
205b and 205c. As described above, the N-type impurity concentration gradually increases in the order of 205a <205b <205c. Therefore, as described later, the TG10
A potential gradient of the P-type charge storage layer 206 is formed such that the third is lower. Such a structure is formed by changing the implantation amount at the same acceleration energy according to the ion implantation method. At this time, the higher the impurity concentration, the deeper the diffusion.

FIG. 1D is a view showing A3-A3 'of FIG. 1B.
FIG. Here, JFET1
02 shows the potential when the gate regions 203 and 204 are reset to the reference voltage and the TG 103 is turned on (set to a low level). Area c of BPD101
In FIG. 1A, since the concentration of the depletion preventing layer 205c is high, the P-type charge storage layer 206 is more likely to be depleted than in the region b. That is, the depletion voltage is small. Region b and region a
Is the same. Then, the depletion prevention layers 205a,
Since 205b and 205c are fixed at the substrate potential,
When the BPD 101 is completely depleted, the potential (potential) of the region c of the P-type charge storage layer 206 becomes higher than that of the region b. Similarly, the region b has a higher potential (potential) than the region a. In other words, a potential gradient is created in the light receiving unit by the impurity concentration gradient in the light receiving unit.

The light receiving portion of the conventional photoelectric conversion element has a uniform potential in a range where the fringe electric field at the end of the light receiving portion does not reach. However, the photoelectric conversion element of this embodiment is
The potential is different in each of the three regions. This potential decreases as approaching the transfer electrode. Therefore, even when the BPD 101 is completely depleted, a potential gradient is generated in each region, so that the BPD 101
01 is the surface P-type gate region 2 of the JFET 102
03, transferred to the deep P-type gate region 204 at high speed.

In this embodiment, the BPD 101 is divided into three regions. However, it goes without saying that the BPD 101 can be divided into an arbitrary number so that a potential gradient is formed in the P-type charge storage layer 206. Although the BPD is used for the light receiving portion here, this may be used as a photodiode, and the concentration of the diffusion region on the surface may be provided with a concentration gradient similarly to the P-type charge storage layer in the present embodiment.

In the photoelectric conversion device, the unit pixels are arranged in a matrix, and a signal is output from each pixel by an XY address scanning circuit. Driving scanning of a photoelectric conversion device in which photoelectric conversion elements are arranged in a matrix is disclosed in
293591. Next, a method for manufacturing a photoelectric conversion element according to the present invention will be described with reference to the drawings.
FIG. 2 is a cross-sectional view of a light receiving unit in each manufacturing process of the photoelectric conversion element according to the first embodiment. First, according to the well-known photolithography method and the ion implantation method, the impurity concentration is 1 × 1.
An N-type diffusion region 302 used as a drain of a JFET is formed on an N-type Si substrate 301 of 0 ¹⁵ cm ^-3 .

Next, an SiO ₂ substrate 301 is formed on the surface of the N-type Si substrate 301.
Film 303 and polysilicon electrode 304 used as TG
To form Then, a mask made of a resist 305 is formed by photolithography so as to open at least a region where a BPD is to be formed, and ¹¹ B ⁺ ions are implanted to form a P-type charge storage layer 306. At this time, the polysilicon electrode 304 functions as a part of a mask for ion implantation. ³¹ P ⁺ ions are implanted with the same mask and BP
An anti-depletion layer 307 having an impurity concentration corresponding to the region a of D101 (see FIG. 1A) is formed. ¹¹ B ⁺ and ³¹ P ⁺ acceleration energy of, depletion prevention layer 307 is formed on the substrate 301 surface, so P-type charge accumulation layer 306 is formed thereunder, ¹¹ B ⁺ and ³¹ P ⁺ acceleration Regulate energy. FIG. 2A shows this state.

Next, the resist 305 is peeled off, and the BPD 10
A resist 308 is formed so as to open portions (see FIG. 1A) corresponding to the regions b and c, and ³¹ P ⁺ is ion-implanted using the resist 308 as a mask to form a depletion preventing layer 307b. At this time, no ions are implanted into the region a, and the region a remains as the depletion prevention layer 307a. FIG. 2B shows this state.

Next, the resist 308 is peeled off and the BPD 10
Resist 3 so as to open a portion corresponding to region c of FIG.
09 is formed, and using this as a mask, ³¹ P ⁺ is ion-implanted to form a depletion preventing layer 307 c having an impurity concentration corresponding to the region c of the BPD 101. At this time, no ions are implanted into the regions a and b, and the respective regions remain as the depletion preventing layers 307a and 307b. FIG. 2C shows this state.

Next, the resist 309 is peeled off, annealing for electrically activating the implanted impurities is performed, and a portion other than the BPD is formed according to a conventional method, whereby a photoelectric conversion element is obtained. FIG. 7 is a graph showing the afterimage characteristics of the photoelectric conversion element of the first embodiment and the conventional photoelectric conversion element.

The horizontal axis represents the length of one side of the square light receiving portion (BPD), and the vertical axis represents the degree of afterimage normalized by setting the output when light is applied to 1. Note that the afterimage is caused by a signal charge remaining from the light receiving unit without being completely transferred. In the case of a photoelectric conversion element employing a conventional BPD, an afterimage is observed from 15 μm square, whereas the BP
In the photoelectric conversion device of the present invention in which D was provided with a three-step potential difference, the afterimage was below the measurement limit even at 30 μm square.

When a potential gradient is formed in the light receiving section as described above, the charges in the BPD 101 are quickly transferred to the JFET 102. Therefore, high-speed operation is also possible. (Second Embodiment) FIGS. 3A and 3B are drawings showing a unit pixel (photoelectric conversion element) of a photoelectric conversion device according to a second embodiment of the present invention, wherein FIG. 3A is a plan view and FIG. (C) is a cross-sectional view along B2-B2 ',
(D) is a potential diagram along B3-B3 'of (b).

The difference from the first embodiment is that the BPD 10
1 is that the portion where the concentration gradient is formed is different. The other parts are the same as those of the first embodiment, and the description is omitted. The BPD 101 has a depletion preventing layer (N-type layer on the surface) 205 with an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ and a impurity concentration of 3 × 10 ¹⁶ cm 3 in order from the front surface to the back surface of the semiconductor substrate.
^-3 P-type charge storage layer 206 and N-type substrate 201. The depletion prevention layer is electrically connected to the substrate 201.

The impurity concentration of the N-type substrate under the P-type charge storage layer 206 is 1 × 10 ¹⁵ cm ⁻³ and 2 × 10 ¹⁵
cm ^-3 , 6 × 10 ¹⁵ cm ^-3
201b and 201c. As described above, the N-type impurity concentration gradually increases in the order of 201a <201b <201c. For this reason, a potential gradient is formed such that the TG 103 becomes lower.

FIG. 3D is a sectional view taken along line B3-B3 'of FIG.
FIG. Here, JFET1
02 shows the potential when the gate regions 203 and 204 are reset to the reference voltage and the TG 103 is turned on (set to a low level). In the region c (see FIG. 3A) below the P-type charge storage layer 206, the P-type charge storage layer 206 is more likely to be depleted than in the region b because the impurity concentration is high.
That is, the depletion voltage is small. The same applies to the relationship between the region b and the region a. Since the depletion preventing layer 205 is fixed at the substrate potential, the potential (potential) of the region c of the P-type charge storage layer 206 becomes higher than that of the region b when the BPD 101 is completely depleted. Similarly, the region b has a higher potential (potential) than the region a. In other words, a potential gradient is created in the light receiving unit due to the impurity concentration gradient in the light receiving unit. Therefore, BPD1
When 01 is completely depleted, a potential gradient occurs in each region, so that the charge in the BPD 101 is reduced to JFET 10
2 surface P-type gate region 203, deep P-type gate region 2
04 is transferred at high speed.

Next, referring to the drawings, manufacture of the photoelectric conversion element will be described.
The method will be described. FIG. 4 shows a photoelectric conversion device according to the second embodiment.
It is sectional drawing of the light-receiving part in each manufacturing process of a replacement element. First, Zhou
According to the well-known photolithography method and ion implantation method, N
Used as a drain of a JFET on a silicon substrate 301
A mold diffusion region 302 is formed. Next, the N-type Si substrate 30
Si0 on one surface_TwoThe film 303 and the policy used as the TG
A recon electrode 304 is formed. And at least BP
Photolithography so as to open the area where D is to be formed
Forming a mask with the resist 305 according to the method¹¹
B⁺To form a P-type charge storage layer 306
You. At this time, the polysilicon electrode 304 is
Acts as part of a mask. Then, with the same mask
³¹P⁺To form a depletion preventing layer 307
You.¹¹B⁺as well as ³¹P + acceleration energy prevents depletion
A layer 307 is formed on the surface of the substrate 301, and a P-type
As the load accumulation layer 306 is formed,¹¹B⁺When³¹P⁺Addition
Adjust the speed energy. FIG. 4 shows this state.
(A).

Next, the resist 305 is peeled off, and the BPD 10
A resist 308 is formed so as to open portions (see FIG. 3A) corresponding to the first regions b and c, and ³¹ P ⁺ is ion-implanted using the resist 308 as a mask. Then, adjustment is performed so that the N-type impurity concentration of the substrate 301b corresponding to the region b of the BPD 101 is higher than that of the region a. At this time, no ions are implanted into the region a, and the region 301a is
The density remains at 01. FIG. 4 shows this state.
(B).

Next, the resist 308 is peeled off and the BPD 10
Resist 3 so as to open a portion corresponding to region c of FIG.
09 is formed, and using this as a mask, ³¹ P ⁺ is ion-implanted. Then, the substrate 3 corresponding to the region c of the BPD 101
The N-type impurity concentration of 01c is adjusted to be higher than the region of b. At this time, no ions are implanted into the regions a and b, and the concentrations of the regions 301a and 301b do not change. FIG. 4C shows this state.

Next, the resist 309 is peeled off, annealing for electrically activating the implanted impurities is performed, and a portion other than the BPD is formed according to a conventional method, whereby the photoelectric conversion element of this embodiment is obtained. Can be (Third Embodiment) FIGS. 5A and 5B are diagrams showing a unit pixel (photoelectric conversion element) of a photoelectric conversion device according to a third embodiment of the present invention, wherein FIG. 5A is a plan view and FIG. -C1 '
(C) is a cross-sectional view along C2-C2 ', and (d) is a potential diagram along C3-C3' in (b). The difference from the first and second embodiments is that the BP
The point where the concentration gradient is formed in D101 is different.

The BPD 101 has a depletion preventing layer (N-type layer on the surface) 205 having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ and a P-type charge storage layer 20 in order from the front surface to the back surface of the semiconductor substrate.
6. The N-type substrate 201 has an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ . The depletion prevention layer is electrically connected to the substrate 201. The P-type charge storage layer 206 has an impurity concentration of 3 × 10 ¹⁶ cm ⁻³ , 2 × 10 ¹⁶ cm ⁻³ , 1 × 10 ¹⁶ cm ⁻³ .
It is divided into three regions 206a, 206b, and 206c of cm ^-3 . Thus, the P-type impurity concentration is 206a> 2.
06b> 206c. For this reason, a potential gradient is formed such that the TG 103 becomes lower.

FIG. 5D is a view showing a line C3-C3 'in FIG. 5B.
FIG. Again, JFET1
02 shows the potential when the gate regions 203 and 204 are reset to the reference voltage and the TG 103 is turned on.
In the region c of the BPD 101 (see FIG. 5A), the P-type charge storage layer 206 is more likely to be depleted than in the region b because the impurity concentration is high. That is, the depletion voltage is small. The same applies to the relationship between the region b and the region a. Then, the depletion prevention layer 205
Is fixed to the substrate potential, so that the potential (potential) of the region c of the P-type charge storage layer 206 becomes higher than that of the region b when the BPD 101 is completely depleted. Similarly, the region b has a higher potential (potential) than the region a. In other words, a potential gradient is created in the light receiving unit due to the impurity concentration gradient in the light receiving unit. Therefore, when the BPD 101 is completely depleted, potential gradients are generated in the respective regions, so that charges in the BPD 101 are transferred to the surface P-type gate region 203 and the deep P-type gate region 204 of the JFET 102 at high speed.

Next, referring to the drawings, manufacture of the photoelectric conversion element will be described.
The method will be described. FIG. 6 shows a photoelectric conversion device according to the third embodiment.
It is sectional drawing of the light-receiving part in each manufacturing process of a replacement element. First, Zhou
According to the well-known photolithography method and ion implantation method, N
Used as a drain of a JFET on a silicon substrate 301
A mold diffusion region 302 is formed. Next, the N-type Si substrate 30
Si0 on one surface_TwoThe film 303 and the policy used as the TG
A recon electrode 304 is formed. And at least BP
Photolithography so as to open the area where D is to be formed
Forming a mask with the resist 305 according to the method¹¹
B⁺To form a P-type charge storage layer 306
You. At this time, the polysilicon electrode 304 is
Acts as part of a mask. Then, with the same mask
³¹P⁺To form a depletion preventing layer 307
You.¹¹B⁺as well as ³¹P⁺The acceleration energy of the depletion prevention layer
307 is formed on the surface of the substrate 301, and a P-type
As the accumulation layer 306 is formed,¹¹B⁺When³¹P⁺Acceleration
Regulate energy. FIG. 6 shows this state.
(A).

Next, the resist 305 is peeled off, and the BPD 10
A resist 310 is formed so as to open portions (see FIG. 5A) corresponding to the first regions a and b, and 11B + is ion-implanted using the resist 310 as a mask to form a P-type charge storage layer 306b. At this time, no ions are implanted into the region c,
Region c remains P-type charge storage layer 306c. FIG. 6B shows this state.

Next, the resist 310 is peeled off and the BPD 10
Resist 3 so as to open a portion corresponding to region c of FIG.
11 is formed, and using this as a mask, ¹¹ B ⁺ ions are implanted to form a P-type charge storage layer 306 a having an impurity concentration corresponding to the region a of the BPD 101. At this time, the areas b and c
Are not implanted into the first region, and the respective regions remain as P-type charge storage layers 306b and 306c. FIG. 6C shows this state.

Next, the resist 311 is peeled off, annealing for electrically activating the implanted impurities is performed, and a portion other than the BPD is formed according to a conventional method, thereby obtaining the photoelectric conversion element of the present embodiment. Can be

[0050]

As described above in detail, in the photoelectric conversion element of the present invention, since the potential gradient is arranged in the light receiving portion so that the transfer portion is lower, the signal from the light receiving portion to the readout portion is provided. The charge is completely transferred in a short time. Therefore, the photoelectric conversion element of the present invention and a photoelectric conversion device using the same,
High-speed operation is possible, and there is an effect that an afterimage does not occur even if the size of the light receiving unit is increased.

[Brief description of the drawings]

FIG. 1 is a drawing showing a unit pixel (photoelectric conversion element) of a photoelectric conversion device according to a first embodiment of the present invention, where (a) is a plan view and (b) is a cross section along A1-A1 ′. Figure, (c)
Is a sectional view along A2-A2 ', and (d) is A3 in (b).
It is a potential diagram along -A3 '.

FIG. 2 is a cross-sectional view of a light receiving unit in each manufacturing process of the photoelectric conversion element according to the first embodiment.

3A and 3B are diagrams illustrating a unit pixel (photoelectric conversion element) of a photoelectric conversion device according to a second embodiment of the present invention, where FIG. 3A is a plan view and FIG. 3B is a cross-section along B1-B1 ′. Figure, (c)
Is a sectional view along B2-B2 ', and (d) is B3 in (b).
It is a potential diagram along -B3 '.

FIG. 4 is a cross-sectional view of a light receiving unit in each manufacturing process of the photoelectric conversion element according to the second embodiment.

FIG. 5 is a drawing showing a unit pixel (photoelectric conversion element) of a photoelectric conversion device according to a third embodiment of the present invention,
(A) is a plan view, (b) is a cross-sectional view along C1-C1 ', (c) is a cross-sectional view along C2-C2', and (d) is a cross-sectional view along C3-C3 'in (b). It is a potential diagram.

FIG. 6 is a cross-sectional view of a light receiving unit in each manufacturing process of the photoelectric conversion element according to the third embodiment.

FIG. 7 is a graph showing the afterimage characteristics of the photoelectric conversion element of the first embodiment and a conventional photoelectric conversion element.

8A and 8B are diagrams showing a unit pixel of a conventional solid-state imaging device, where FIG. 8A is a plan view, FIG. 8B is a cross-sectional view along D1-D1 ′, and FIG. 8C is a view along D3-D3 ′. (D) is a potential diagram along D2-D2 'of (b).

[Explanation of symbols]

101: embedded photodiode 102: JFET 103: transfer electrode 104: reset drain 105: reset gate 106, 107: contact portion 201, 301: N-type Si substrate 203; 204 gate region 205, 307 depletion prevention layer 206, 306 P-type charge storage layer 207 N + type source region 208, 302 N-type drain region 209 N Mold channel 303: silicon oxide film 304: polysilicon electrode 305, 308, 309, 310, 311: photoresist

Claims (8)

[Claims] 1. A light receiving unit which is arranged on a semiconductor substrate and generates and accumulates an electric charge according to incident light, a transfer unit which transfers the electric charge accumulated in the light receiving unit to a reading unit, and a transfer unit which receives the electric charge from the transfer unit. A photoelectric conversion element having the readout unit that generates a signal corresponding to the received electric charge, wherein the light receiving unit has a concentration gradient of an impurity, and the potential decreases as approaching the transfer unit. element. 2. A semiconductor device comprising: a first conductive type semiconductor substrate;
A light receiving unit that generates and accumulates a charge corresponding to the incident light, and a transfer unit that transfers the charge accumulated in the light receiving unit to a reading unit;
A photoelectric conversion element having a read section that generates a signal corresponding to the charge transmitted from the transfer section, wherein the light receiving section includes a first conductivity type depletion prevention layer, and a depletion prevention layer. A buried photodiode that is in contact with and has a second conductivity type charge storage layer provided below the depletion prevention layer, wherein the depletion prevention layer has an impurity concentration gradient; A photoelectric conversion element, wherein an impurity concentration of one conductivity type becomes higher as the distance from the transfer section increases. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate is disposed on a semiconductor substrate of a first conductivity type.
A light receiving unit that generates and accumulates a charge corresponding to the incident light, and a transfer unit that transfers the charge accumulated in the light receiving unit to a reading unit;
A photoelectric conversion element having a read section that generates a signal corresponding to the charge transmitted from the transfer section, wherein the light receiving section includes a first conductivity type depletion prevention layer, and a depletion prevention layer. A buried photodiode that is in contact with and has a second conductivity type charge storage layer provided below the depletion prevention layer, wherein the charge storage layer has an impurity concentration gradient; A photoelectric conversion element, wherein the conductivity type impurity concentration decreases as the distance from the transfer section increases. 4. A semiconductor device comprising: a first conductive type semiconductor substrate;
A light receiving unit that generates and accumulates a charge corresponding to the incident light, and a transfer unit that transfers the charge accumulated in the light receiving unit to a reading unit;
A photoelectric conversion element having a read section that generates a signal corresponding to the charge transmitted from the transfer section, wherein the light receiving section includes a first conductivity type depletion prevention layer, and a depletion prevention layer. And a second conductivity type charge storage layer provided in contact with and below the depletion preventing layer. The semiconductor substrate under the buried photodiode has an impurity concentration of: A photoelectric conversion element having a gradient, wherein the density is low at a portion adjacent to the transfer section, and becomes higher as the distance from the transfer section increases. 5. The photoelectric conversion device according to claim 1, wherein the concentration gradient changes stepwise. 6. The photoelectric conversion element according to claim 1, wherein said read section has a transistor for amplifying said electric charge. 7. The photoelectric conversion device according to claim 6, wherein said transistor is a junction type field effect transistor. 8. The pixel according to claim 1, wherein the photoelectric conversion elements are arranged in a matrix as unit pixels, and a signal is output from each pixel by an XY address scanning circuit. Photoelectric conversion device.