JP2000228663A - Method for transferring q bit to line in echo canceller system and its network terminating equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely confirm the test state at the time of performing a test on the host station side of network terminating equipment by transferring Q bit data to a line when a line standard (ANSI/T.601) and a terminal standard (ITU-T/I.430) are different. SOLUTION: This network terminating equipment 1A is provided with a line terminating part 2, a data processing part 3A and a terminal terminating part 4 and the data processing part 3A is provided with each part from a line reception multi-frame synchronization circuit 9 to a line transmission multi-frame insertion circuit 30 and generates the multi-frames of the common multiple cycle of the multi-frames on a line side and a terminal side. A compression processing for holding Q bits from a terminal by a fixed cycle is performed. Further, the processing of allocating multi-frame bits and the information of compressed Q bits from the terminal to free bits on the line is performed and the information of the compressed Q bits is transferred to the line as the Q bits from the terminal to a host station.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller system for transferring Q-bit data, which is a test request signal from a terminal to a network terminating device, to a line even when the line standard differs from the terminal standard. Regarding the bit transfer method and the network terminating device, particularly, the line standard is ANSI (Ame
ricn National Standards Institute) T. 601 and the terminal standard is ITU-T / I. The present invention relates to a method for transferring a Q bit to a line in an echo canceller system based on the 430 standard (user network interface), and a network terminating device thereof.

[0002]

2. Description of the Related Art Conventionally, a part of a simple telephone network (PHS) in North America and Japan is connected to a line such as a microcell base station (outdoor device) and ISDN, and ANSI / T. 601 is applied, and ITU-T / I. There is an example in which a network terminating device (NT / Digital Service Unit (DSU)) to which the 430 standard (user network interface) is applied and to which an echo canceller method is applied is used. This echo canceller method extracts only a received signal when a transmitted signal leaks to a receiving circuit side in a so-called up / down (bidirectional) transmission of a digital signal through one subscriber line.

[0003] This line standard is ANSI / T. 601 and the terminal standard is ITU-T / I. In a network termination device to which the echo canceller system of the 430 standard is applied, a test control bit (Q bit in the I.430 standard) from a digital subscriber terminal (appropriately abbreviated as a terminal) is defined as an overhead bit on a line. Is not transferred to the line. This Q bit is defined in ITU-T / I. 430
According to the standard, the terminal is open to the user for free use, and can be set on the terminal side at a position corresponding to FA (auxiliary frame) bits for every five received frames in multi-frame (abbreviated as MF) transmission. Data.

FIG. 8 is a block diagram showing a configuration example of such a conventional network termination device. In FIG. 8, the network terminating device 1 performs analog-to-digital conversion of a downstream signal S5, performs termination processing, and establishes synchronization of a multi-frame on a line with a line terminating unit 2 that transmits an upstream signal S6. Terminates overhead bits, processes format conversion and multi-frame bit addition, performs a data processing unit 3 that performs various tests based on the detected Q bits, and processes conversion and termination for uplink signal S8. And a terminal terminator 4 for transmitting the converted signal as a downlink signal S7 to a terminal (not shown).

Next, the operation of the conventional example will be described. The line termination unit 2 performs analog / digital conversion of the down signal S5 from the line and performs termination processing.
A process of transmitting the digital / analog converted signal to the line as an uplink signal S6 is performed.

In the data processing unit 3, a down signal S5 from the line, which is an output signal of the line terminating unit 2, is input to the line receiving multi-frame synchronization circuit 9, where the multi-frame synchronization on the line is established and the overhead bit is controlled. Perform termination processing. Further, the downlink format conversion circuit 10 performs format conversion from the data array on the line to the data array on the terminal side. Furthermore, for this converted signal,
The signal created by the terminal transmission multi-frame counter circuit 11 is added as multi-frame bits by the terminal transmission multi-frame insertion circuit 12 and output to the terminal termination unit 4.

In the data processing unit 3, an uplink signal S8 from a terminal (not shown) is input to the Q bit detection circuit 13 through the terminal termination unit 4, where the Q bit on the terminal interface is detected. Various tests are performed in the device from the bits. The main signal in the upstream signal S8 is format-converted from the data array on the terminal side to the data array on the line by the upstream format conversion circuit 14, and the line transmission multi-frame insertion circuit 16 is generated by the line transmission multi-frame counter circuit 15. The multi-frame bit period is added to the uplink signal S8 as 8 multi-frame bits and transmitted to the line termination unit 2.

The terminal termination unit 4 processes the conversion and termination of the AMI (ternary code) / NRZ (binary code) for the uplink signal S8 from a terminal (not shown), and also performs the NRZ (binary code) / AMI ( The converted signal (ternary code) is transmitted to a terminal (not shown) as a downlink signal S7.

In the network terminating device 1, the Q bit from the terminal is terminated in the device, and is not transferred on the line. Therefore, even when the network termination device 1 is in the test state due to a request from the terminal, the test state cannot be confirmed on the upper station side (not shown) of the network termination device 1.

As examples relating to such a network terminating device, “Specific terminal communication system” in JP-A-4-246962 and “ISD” in JP-A-7-107202.
An "N basic inter-interface connection device" is known. In the former conventional example, a logical value having a low priority is stored at a predetermined bit position in a frame transmitted by a terminal that establishes multiframe synchronization, and a terminal that has already established multiframe synchronization transmits the logical value. The predetermined bits of the transmission frame to be transmitted are not destroyed. In the latter conventional example, the D bit and the S / Q bit or start / stop information are multiplexed in the ISDN, transmitted using the same bus as the information (B) channel, the S / Q bit is transmitted transparently, and The start / stop procedure is performed synchronously at both ends of the transmission path.

Japanese Patent Application Laid-Open No. 10-285160 discloses "Receiving Circuit in ISDN Line Termination Device" and Japanese Patent No. 2800710 "Remote Maintenance Test Method and System". Of these, the former example is
ITU-T / I. It automatically responds to all wiring configurations supported by the network termination device according to the 430 rule, prevents continuation of bit errors, and enables normal reception. Further, in the latter conventional example, the maintenance is performed without using a specific channel by putting a maintenance signal on an unused bit in the F-bit multiframe of the multiplex transmission line.

[0012]

In these conventional examples,
Line standard ANSI / T. 601 and the terminal standard ITU-T / I. When the 430 standard is applied and the echo canceller method is further applied, the Q bit from the terminal is not transferred on the line, and the higher-order station side of the network terminating apparatus puts the network terminating apparatus 1 in the test state by a request from the terminal. In this case, there is a disadvantage that the test state cannot be confirmed.

The present invention solves the above-mentioned problems in the conventional technology, and adopts a line standard (ANSI / T.
601) and the terminal standard (ITU-T / I.430) are different, a new multi-frame bit is added to the vacant bit of the line, and the Q bit data, which is a test request signal from the terminal to the network terminating device, is transmitted. When the network terminating equipment is in a test state by a request from the terminal at the higher station side of the network terminating equipment, the Q-link to the line in the echo canceller system can be surely confirmed. It is an object of the present invention to provide a bit transfer method and a network terminating device thereof.

[0014]

In order to achieve the above-mentioned object, the present invention relates to a method for transmitting a signal to a line in an echo canceller system according to the present invention.
The bit transfer method is to perform Q bit transfer to the line in the echo canceller system at the network termination where the line standard and the terminal standard are different, a process of generating a multi-frame on the line side and the terminal side in a common multiple cycle. Next, a process of holding the Q bits from the terminal at a fixed period and performing a compression process, a process of allocating the multi-frame bits and the information of the compressed Q bits from the terminal to the vacant bits on the line, and the allocation information To the upper station as Q bits from the terminal.

The network terminating device of the present invention performs Q bit transfer to a line in an echo canceller system at a network terminal having a different line standard and terminal standard, and adds a new multi-frame bit to a vacant bit of the line. Then, it is configured to include processing means for transferring Q-bit data, which is a test request signal from the terminal to the network terminating device, to the line.

The processing means includes: a generation means for generating a common multiple period of a multi-frame on the line side and the terminal side; a holding compression processing means for holding a Q bit from the terminal at a fixed period and performing a compression process; Allocation processing means for allocating multi-frame bits and information on compressed Q bits from the terminal to vacant bits on the line, and compression Q allocated by the allocation processing means
Transfer processing means for transferring the bit information to the upper station as Q bits from the terminal. Further, the common multiple cycle in the generation means is set to the minimum common multiple cycle, and the line standard is set to ANSI / T. 601 standard and the terminal standard is described in ITU-T / I. 430
The configuration is based on the user network interface standard.

Further, the processing means includes a line terminating section for transmitting an upstream signal obtained by converting and terminating a downstream signal, establishing at least synchronization of a multiframe and terminating overhead bits, and converting the signal into a format-converted signal. A test is performed by adding a multi-frame bit and detecting the Q bit on the terminal interface,
In addition, the configuration includes a data processing unit that adds a multi-frame bit to the format-converted signal, and a terminal termination unit that processes the conversion and termination of the uplink signal and transmits the converted signal to the terminal as a downlink signal.

Further, as the data processing unit, a signal on the line for a down signal from the line which is an output of the line terminating unit.
Line reception multi-frame synchronization circuit for establishing multi-frame synchronization and terminating overhead bits, downlink format conversion circuit for format conversion from data array on the line to data array on the terminal side, and generation and transmission of multi-frame bit period A terminal transmission multi-frame counter circuit, and a terminal transmission multi-frame insertion circuit that adds the multi-frame bits generated by the terminal transmission multi-frame counter circuit to the converted signal from the downlink format conversion circuit and outputs the result to the terminal termination unit. It is a structure provided with.

Also, the data processing unit receives a Q signal on a terminal interface with respect to an uplink signal passing through a terminal termination unit.
A Q-bit detection circuit for detecting a bit and performing a test, a compression processing circuit for processing the number of Q-bit protection stages from the Q-bit detection circuit and performing compression at a fixed period, and an upstream signal An upstream format conversion circuit that performs format conversion on the main signal from a data array on the terminal side to a data array on the line, and a Q bit insertion circuit that adds Q bits to the data array that has been format converted by the upstream format conversion circuit A line transmission multi-frame counter circuit for generating an 8 multi-frame bit period on the line, a new multi-frame counter circuit for generating a line-side and terminal-side least common multiple period from an output of the line transmission multi-frame counter circuit, The output of the new multi-frame counter circuit is added to the upstream signal S8 as a new multi-frame bit. And the new multi-frame insertion circuit is configured to include a line transmission multiframe insertion circuit for outputting 8 multiframe bits on the line to the line termination unit in addition to the up signal.

Further, in place of the compression processing circuit, an n-stage compression processing circuit for performing Q-bit data compression by processing n-stage consecutive matches and sampling every n cycles of a multiframe is used. .

The method of transferring a Q bit to a line in the echo canceller system of the present invention and the network terminator thereof add a new multi-frame bit to a vacant bit of the line and transmit a test request signal from the terminal to the network terminator. Some Q
Bit data is being transferred to the line.

As a result, the Q executed by the network terminating device
The test information based on the bits can be recognized by the upper station on the line. Furthermore, a new multi-frame configuration is employed, and Q bit transfer is performed using unused bits that are not currently defined. Therefore, Q bit transfer can be performed without affecting processing in the existing network terminating device. .

Also, a method for transferring a Q bit to a line in the echo canceller system of the present invention and a network terminating device thereof are provided.
In the compression process, an n-stage compression process for compressing Q-bit data is performed by performing n-stage consecutive matching and sampling every n periods of the multiframe.

As a result, it is possible to reduce bit allocation processing of Q bits to be transferred on a line as a new multiframe.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for transferring a Q bit to a line in an echo canceller system and a network terminating device thereof according to the present invention will be described in detail with reference to the drawings. In the following text and figures, the same components as those in FIG. 8 described above are denoted by the same reference numerals. FIG. 1 is a block diagram showing an embodiment of a method for transferring a Q bit to a line in an echo canceller system and a network terminating device thereof according to the present invention.

In FIG. 1, the network terminating apparatus 1A converts the downstream signal S5 into an upstream signal S which has been processed and terminated.
6, mainly for establishing synchronization of multiframes and terminating overhead bits, and
A data processing unit 3A that adds a multi-frame bit to the format-converted signal, detects the Q bit on the terminal interface, performs various tests, and further adds a multi-frame bit to the format-converted signal; Process conversion and termination for signal S8,
Also, a terminal termination unit 4 for transmitting the converted signal as a downlink signal S7 to a terminal (not shown) is provided.

The data processing unit 3A includes a line receiving multi-frame synchronizing circuit 9 for establishing synchronization of eight multi-frames on the line with respect to the down signal S5 from the line, which is an output of the line terminating unit 2, and terminating overhead bits. A downlink format conversion circuit for format-converting the data array on the line into a data array on the terminal side; a terminal transmission multi-frame counter circuit for generating and transmitting a multi-frame bit period; And a terminal transmission multi-frame insertion circuit 12 that adds the multi-frame bits generated by the terminal transmission multi-frame counter circuit 11 to the converted signal and outputs the result to the terminal termination unit 4.

The data processing unit 3A detects a Q bit on the terminal interface with respect to the uplink signal S8 passing through the terminal terminating unit 4, and performs various tests in the apparatus from the detected Q bit. A Q bit detection circuit 13,
A compression processing circuit 24 that processes the number of Q-bit protection stages from the Q-bit detection circuit 13 and performs compression at a fixed period, and recovers the main signal of the uplink signal S8 through the terminal termination unit 4 from the data array on the terminal side. An upstream format conversion circuit 25 performs format conversion to a data array on a line, and a Q bit insertion circuit 26 adds Q bits to the data array converted here.

Further, the data processing section 3A includes a new multi-frame insertion circuit 27 for adding the output of the new multi-frame counter circuit 29 as a new multi-frame bit to the upstream signal S8, and an ANSI / T. A line transmission multi-frame counter circuit 28 that processes the phase of 8 multi-frames from the 601 standard network terminator 1A to the line and generates an 8-multi-frame bit period on the line, and the output of the line transmission multi-frame counter circuit 28 A new multi-frame counter circuit 29 for generating a cycle of a common multiple between the line side and the terminal side, and a line transmission multi-frame insertion circuit 30 for adding 8 multi-frame bits on the line to the upstream signal S8 and outputting it to the line terminating section 2. And The cycle of the common multiple of the new multi-frame counter circuit 29 is the cycle of the least common multiple to reduce the processing scale.

Next, the operation of this embodiment will be described. The line termination unit 2 performs analog / digital conversion of the down signal S5 from the line and performs termination processing.
A process of transmitting the digital / analog converted signal to the line as an uplink signal S6 is performed.

The data processing unit 3A receives the down signal S5 from the line, which is the output of the line termination unit 2, and inputs the down signal S5 to the line reception multi-frame synchronization circuit 9, where the synchronization of 8 multi-frames on the line and the overhead bit Is terminated. Further, the downlink format conversion circuit 10 performs format conversion from the data array on the line to the data array on the terminal side. Further, a signal generated by the terminal transmission multi-frame counter circuit 11 is added to the converted signal as a multi-frame bit by the terminal transmission multi-frame insertion circuit 12 and output to the terminal termination unit 4.

In the data processing unit 3A, an upstream signal S8 from a terminal (not shown) is input to the Q bit detection circuit 13 through the terminal termination unit 4, where the Q bit on the terminal interface is detected and detected. Various tests are performed in the apparatus from the Q bit. Further, the compression processing circuit 24
Performs processing on the number of Q-bit protection stages from the Q-bit detection circuit 13 and performs compression at a constant cycle. The main signal of the upstream signal S8 through the terminal termination unit 4 is input to the upstream format conversion circuit 25, where the format conversion is performed from the data array on the terminal side to the data array on the line. The Q bit insertion circuit 26 adds Q bits to the format-converted data array.

Further, the line transmission multi-frame counter circuit 28 generates an 8 multi-frame bit period on the line, and outputs a new multi-frame counter circuit 29 from this output.
Generates the cycle of the least common multiple between the line side and the terminal side. The new multi-frame insertion circuit 27 adds this output to the upstream signal S8 as a new multi-frame bit. Also, the line transmission multi-frame insertion circuit 30 adds 8 multi-frame bits on the line to the uplink signal S8 and outputs the result to the line termination unit 2.

The terminal terminating unit 4 performs the AM for the uplink signal S8.
It processes the conversion and termination from I (ternary code) to NRZ (binary code), and converts NRZ (binary code) to AMI (3
The converted signal (downlink signal S7) is transmitted to a terminal (not shown).

Next, the operation of the main part of this embodiment will be described with a specific example. FIG. 2 is a diagram for explaining a line-side I / F frame format configuration common to uplink and downlink, and FIG. 3 is a diagram for explaining a line-side multiframe (8MF) configuration. FIG. 4A is a diagram for explaining the terminal-side I / F frame format configuration in the uplink (from the terminal to the network termination device 1A).
(B) is a diagram for explaining the terminal-side I / F frame format configuration in the downstream (from the network termination device 1A to the terminal). FIG. 5 is a diagram for explaining a terminal-side multi-frame (20 MF) configuration related to Q bits, and FIG. 6 is a diagram for explaining a line-side new multi-frame (40 MF) configuration for a line from the network termination device 1A. FIG.

In FIG. 1, the down signal S5 is an analog signal of the echo canceller system,
/ D conversion. This downlink signal S5 is composed of the frame shown in FIG. 2, and 240 bits are transmitted in 1.5 ms. The line-side I / F frame format common to uplink and downlink shown in FIG. 2 is frame / multiframe synchronization bit / 18 bits (bit positions 1-8), 12 × (information channel (2B) + control channel (D) / It consists of 216 bits (bit positions 19 to 234) and M / 6 bits (bit positions 235 to 240).

The overhead bits are transmitted in the eight multi-frames (basic frames 1 to 3) shown in FIG.
8) Transferred by configuration. That is, the line side multi-frame (8MF) shown in FIG.
In the framing (ISW (Inverted
syne word) / 9-bit inverted frame signal and SW (syne word) / 9-bit frame signal), and information channels (2B) + control channels (D) are allocated to bit positions 19-234. Can be Also, in bit positions 235-240,
_{1, M 2, M 3,} M 4, M 5, eoc for each basic frame 1-8 M ₆ (remote control bits), act
(Start bit), ps1 (main power status bit), ntm
(NT test mode bit), febe (far end block error bit), crc (cyclic redundancy check bit), and the like. Here, there are five empty bits.

The output of the line terminating unit 2 receives the establishment of synchronization of 8 multiframes on the line and termination processing of overhead bits in a line receiving multiframe synchronizing circuit 9, and the information channel (2B) + control channel in a downlink format converting circuit 10. The downlink signal S5 of (D) is converted from the format of the line-side interface (abbreviated as I / F) frame shown in FIG. 2 to the format of the downstream terminal-side I / F frame shown in FIG. 4B. .

The downstream (network terminating device 1) shown in FIG.
The terminal-side I / F frame format in A to terminal) includes F, L (frame bits of the I430 standard side),
E (echo bit of rising control (D) channel signal from terminal on I430 standard side), A (start identification bit), N
(Inverse bit of Fa), M (multi-frame bit), D1, D2 (control (D) channel bit), S
(Response to the Q bit from the terminal and transfer bits such as an error to the terminal) and B1ch and B2ch (information channel bits) are stored.

The terminal-side multiframe counter circuit 11 generates a 20-frame period (5 ms) in order to transfer overhead bits by the terminal-side multiframe configuration of FIG. The terminal transmission multi-frame insertion circuit 12 inserts the output of the terminal transmission multi-frame counter circuit 11 into the downlink signal S7 as multi-frame bits. The downlink data signal (NRZ) of the multi-frame configuration shown in FIG.
Here, it is converted into a terminal I / F signal or AMI signal and output to the terminal side.

Next, an uplink signal S8 from a terminal (not shown)
Is an AMI signal, and this AMI signal is
NRZ that can be processed by a digital circuit (not shown)
Convert to a signal. The NRZ signal converted by the terminal terminating unit 4 is input to the Q bit detection circuit 13, and the Q bit detection circuit 13 uses the terminal multiframe (20M) shown in FIG.
F) The overhead bits Q1, Q2, Q in the configuration
4 bits of 3, Q4 are detected.

In order to transfer the Q bit to the line side, five vacant bits (fixed to 1) provided on the uplink multi-frame (8MF) configuration shown in FIG.
As defined in the line-side new multi-frame (40MF) configuration shown in FIG. 1, one bit is allocated and transferred as a new multi-frame bit, and four bits are allocated and transferred as a Q bit.

The current multiframe periods shown in FIGS. 3 and 4 are, for example, 5 ms on the terminal side and 12 ms on the line side, and the period of the least common multiple is 60 ms. During this time, 8 multi-frames are transferred 5 times on the line side and 20 multi-frames are transferred 12 times on the terminal side. When this is applied to Q bits, the terminal side is 4 × 12 = 48 bits, and the line side is 4 × 5.
= 20 bits, and the Q-bit data from the terminal cannot be transferred as it is. Therefore, the compression processing circuit 24 applies the triple coincidence protection of the Q bits detected by the Q bit detection circuit 13, performs sampling every three periods of 20 multiframes, and performs data compression processing of Q bits.

The compressed Q bit data is input to the Q bit insertion circuit 26. The Q bit insertion circuit 26 adds Q bit data to the signal of the upstream information channel (2B) + control data (D) which has been subjected to the frame format conversion shown in FIGS. 4 (a), 3 and 2 from the upstream format conversion circuit 25. Is added.

In the terminal-side I / F frame format in the upstream (from the terminal to the network termination device 1A) shown in FIG. 4A, F, L (frame bits of the I430 standard side), D
1, D2 (control (D) channel bits), S (transfer bits for a response from the terminal to the Q bit and an error to the terminal, etc.), and B1ch and B2ch (information channel bits).

Next, the 8-multiframe period signal (12 m
s) to the new multi-frame counter circuit 29,
Here, the frequency is divided to the least common multiple period (60 ms), and this output is input to the new multi-frame insertion circuit 27 and added to the upstream data, thereby generating the line-side new multi-frame (40 MF) shown in FIG. .

In the line-side new multiframe (40MF) for the line from the network terminating device 1A shown in FIG.
L (frame bit on I430 standard side), D1, D2
(Control (D) channel bits), Fa (auxiliary frame bits), S (transfer bits for response from terminal to Q bit and error to terminal), and B1ch and B2ch (information channel bits).

Thereafter, the currently used 8 multiframes on the line side are inserted into the line transmission multiframe insertion circuit 30.
2 and 3 (a) to generate the digital signal format shown in FIGS. 2 and 3A.
/ A conversion and output on the line.

As described above, in this embodiment, a new multi-frame bit is added to a vacant bit of a line, and Q-bit data, which is a test request signal to the network terminator 1A, is transferred from a terminal (not shown) to the line. Therefore, the test information based on the Q bit executed in the network terminating device 1A can be recognized by the higher station on the line. Furthermore,
Adopting a new multi-frame configuration and performing Q bit transfer using unused bits that are not currently defined, it does not affect the processing in the existing network termination device (1A).
Q bit transfer is performed.

Next, another embodiment will be described. FIG. 7 is a block diagram illustrating a configuration of another embodiment. In this embodiment, instead of the compression processing circuit 24 in the data processing unit 3A of the network termination device 1A shown in FIG. 1, an n-stage compression processing circuit 3B is added to the data processing unit 3B of the network termination device 1B.
4 are provided. Other configurations are the same as those in FIG. In this n-stage compression processing circuit 34, n of 4 to 12 stages
(N = 4,6,12) By applying successive matches and sampling every n periods of 20 multiframes,
Q-bit data compression is performed.

Next, the operation of another embodiment will be described. The downstream signal S5 from the line is the network termination device 1A of FIG.
And is output to the terminal (not shown) as a downlink signal S7. Further, the uplink signal S8 from the terminal is subjected to AMI / NRZ conversion in the terminal termination unit 4, and the Q bit detection circuit 13 detects Q bits. This detected Q
The bit is subjected to n-stage continuous coincidence protection by an n-stage compression processing circuit 34, and the terminal transmission multi-frame counter circuit 11
The compression process is performed at a sampling cycle of every 20 cycles of 20 multi-frames output from.

Then, the Q bit insertion circuit 26 adds the compressed Q bit data to the upstream data,
The new multi-frame insertion circuit 27 adds the 60 ms period generated by the new multi-frame counter circuit 29 as a new multi-frame bit. Next, the line transmission multi-frame insertion circuit 30 inserts the 8 multi-frame periods generated by the line transmission multi-frame counter circuit 28 into the uplink data as multi-frame bits, and performs D / A conversion in the line termination unit 2. Output to the line as an up signal S6.

In this configuration, the Q transferred to the line as a new multi-frame by the processing of the n-stage compression processing circuit 34
It becomes possible to reduce bit allocation processing of bits.

[0054]

As is apparent from the above description, according to the method for transferring Q bits to a line in the echo canceller system of the present invention and the network terminating device thereof, a new multi-frame bit is added to a free bit of the line. The terminal transfers Q-bit data, which is a test request signal to the network terminating device, to the line.

As a result, the Q executed by the network terminating device
Since the test information using bits can be recognized by the upper station on the line, and a new multi-frame configuration is adopted, and Q bits are transferred using unused bits that are not currently defined, processing in the existing network terminating equipment is performed. There is an effect that Q-bit transfer can be performed without affecting.

Further, according to the method of transferring a Q bit to a line in the echo canceller system of the present invention and the network terminating device thereof, in the compression processing, n stages of consecutive matches are performed and sampling is performed every n periods of a multiframe. , Q-bit data compression is performed.

As a result, there is an effect that the bit allocation processing of Q bits to be transferred on the line as a new multiframe can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a method for transferring a Q bit to a line in an echo canceller system and a network terminating device thereof according to the present invention.

FIG. 2 is a diagram illustrating a line-side I / F frame format configuration in the embodiment.

FIG. 3 is a diagram illustrating a configuration of a line-side multiframe in the embodiment.

FIG. 4 is a diagram for describing a terminal-side I / F frame format configuration in the embodiment.

FIG. 5 is a diagram for describing a terminal-side multiframe configuration related to Q bits in the embodiment.

FIG. 6 is a diagram illustrating a new line-side multi-frame configuration in the embodiment.

FIG. 7 is a block diagram showing a configuration of another embodiment.

FIG. 8 is a block diagram illustrating a configuration example of a conventional network termination device.

[Explanation of symbols]

 1A, 1B Network termination device 2 Line termination unit 3A, 3B Data processing unit 4 Terminal termination unit 9 Line reception multiframe synchronization circuit 10 Downlink format conversion circuit 11 Terminal transmission multiframe counter circuit 12 Terminal transmission multiframe insertion circuit 13 Q bit detection Circuit 24 compression processing circuit 25 upstream format conversion circuit 26 Q bit insertion circuit 27 new multiframe insertion circuit 28 line transmission multiframe counter circuit 29 new multiframe counter circuit 30 line transmission multiframe insertion circuit 34 n-stage compression processing circuit

Claims (10)

[Claims] 1. A method of transferring a Q bit to a line in an echo canceller system at a network termination where a line standard and a terminal standard are different, wherein a process of generating a multi-frame on a line side and a terminal side in a common multiple cycle; Next, a process of holding the Q bits from the terminal at a constant period and performing a compression process, a process of allocating the multi-frame bits and the information of the compressed Q bits from the terminal to vacant bits on the line, Transferring a Q bit from the terminal to an upper station as a Q bit, the method comprising: 2. A network terminator for performing Q bit transfer to a line in an echo canceller system at a network end where a line standard and a terminal standard are different, wherein a new multi-frame bit is added to a vacant bit of the line.
Q which is a test request signal from the terminal to the network termination device
A network terminating device comprising processing means for transferring bit data to a line. 3. A processing means for generating a common multiple period of a multi-frame between a line side and a terminal side, and a holding compression processing means for holding Q bits from the terminal at a constant period and performing compression processing. Allocation processing means for allocating multi-frame bits and compressed Q bit information from the terminal to empty bits on the line; and transmitting the compressed Q bit information allocated by the allocation processing means 3. The network terminating device according to claim 2, further comprising: transfer processing means for transferring as bits. 4. The network terminating apparatus according to claim 3, wherein a common multiple cycle in said generating means is a minimum common multiple cycle. 5. The system according to claim 1, wherein said line standard is ANSI / T. 3. The network terminating device according to claim 2, wherein the network terminating device is 601 standard. 6. The terminal standard according to ITU-T / I. 3. The network termination device according to claim 2, wherein the network termination device is 430 user network interface standard. 7. A line termination unit for transmitting an upstream signal obtained by converting and terminating a downstream signal, as a processing unit, and at least synchronizing a multiframe and terminating an overhead bit, and converting the signal into a format-converted signal. A data processing unit that adds a multi-frame bit, performs a test by detecting the Q bit on the terminal interface, and adds a multi-frame bit to the format-converted signal, and processes conversion and termination for the uplink signal. 3. The network terminating device according to claim 2, further comprising: a terminal terminating unit that transmits a converted signal to the terminal as a downlink signal. 8. A line receiving multi-frame synchronization circuit for establishing synchronization of 8 multi-frames on a line with respect to a downlink signal from a line, which is an output of a line terminating unit, and terminating an overhead bit, A downlink format conversion circuit for format-converting the data array to a data array on the terminal side, a terminal transmission multi-frame counter circuit for generating and transmitting a multi-frame bit period, and a conversion signal from the downlink format conversion circuit.
The network termination device according to claim 7, further comprising: a terminal transmission multi-frame insertion circuit that adds a multi-frame bit generated by the terminal transmission multi-frame counter circuit and outputs the result to a terminal termination unit. 9. A Q bit detection circuit for detecting a Q bit on a terminal interface and performing a test on an uplink signal passing through a terminal termination unit, as the data processing unit; A compression processing circuit that processes the number of Q-bit protection stages and performs compression at a fixed period; and an upstream that performs format conversion from a data array on the terminal side to a data array on the line for a main signal of the upstream signal through the terminal termination unit. A format conversion circuit, a Q bit insertion circuit for adding Q bits to the data array format-converted by the upstream format conversion circuit, a line transmission multi-frame counter circuit for generating an 8 multi-frame bit period on the line, A new multiplexer for generating a cycle of the least common multiple of the line side and the terminal side from the output of the line transmission multi-frame counter circuit. A new multi-frame counter circuit, a new multi-frame insertion circuit for adding the output of the new multi-frame counter circuit as a new multi-frame bit to the upstream signal S8, and a line termination by adding 8 multi-frame bits on the line to the upstream signal. The network terminating device according to claim 7, further comprising: a circuit transmission multi-frame insertion circuit that outputs the signal to a unit. 10. An n-stage compression processing circuit for performing Q-bit data compression by processing n-stage consecutive matches and sampling every n periods of a multi-frame, instead of the compression processing circuit. The network termination device according to claim 9, wherein