JP2000216812A - Error compensation method and error compensation device using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To partially substitute a re-transmitted packet at a bit level by detecting an error from a newly generated bit string and dealing with the bit string as regular received data when a code error cannot be detected. SOLUTION: When a reception station receives a packet, it detects the code error of the received packet. When the code error exists, the packet is once preserved in an intermediate buffer (S1-S3). When the reception of the packet is not the first time, the corresponding packet and the packet which is received this time are synthesized and a new bit string is generated (S4 and S5). The number of the patterns of the new bit string which is newly generated becomes plural in general and the plural new bit strings are independently code error- checked (S6-S8). When the packet without the code error is detected in the bit strings, one pattern is selected from the packet and the pattern with the error code is canceled (S9-S10).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system for connecting a transmitting station and a receiving station via a cable or wirelessly and transferring data in packet units. The present invention relates to a technique for compensating for a code error by retransmission when is detected. The present invention
In particular, it is used in wireless communication systems such as wireless ATM.

[0002]

2. Description of the Related Art In a conventional error compensation method, a transmitting station adds a code error detection code in packet units, performs error detection at a receiving station, and retransmits when a code error is detected. I was

FIG. 10 shows an algorithm of retransmission control on the receiving station side at the time of packet reception in the conventional system. When the receiving station first receives the packet (S100), it performs an error detection process using the code error detection code assigned by the transmitting station,
If a code error is detected (S101), the entire received packet is discarded (S102), and a retransmission request for this packet is made (S103). On the other hand, if no code error is detected (S101), the receiving process for the packet is performed (S104), and the process ends (S105). As a method of requesting retransmission of a packet in S103, Stop and Wai
t (SW) method, Go Back N (GBN) method, Selective Repea
There are t (SR) method, etc., but the simplest method is SW method.

FIG. 11 shows an outline of the operation of the SW system. In the figure, the left side indicates a transmitting station, the right side indicates a receiving station, right arrows D1 to D4 indicate a flow of packets, and left arrows C1 to C4 indicate a flow of retransmission request information. An x mark in D2 means that a code error has occurred during packet transmission. # 1 to # 3 given to the transmitted packet are serial numbers given for easy understanding of the description, and in the case of the SW system, it is not necessary to actually give the packet. In D1, packet # 1 was received without any code error by the receiving station, so that the receiving station received Acknowle indicating normal reception as control information C1.
Send a dgement (ACK) signal. Upon receiving the ACK, the transmitting station transmits the next packet # 2 (D2).
However, since a code error has occurred here, a negative acknowledgment message indicating reception failure is used as control information C2.
Send an nt (NAK) signal. The transmitting station retransmits packet # 2 because ACK was not received at C2 (D
3) After receiving the ACK (C3), transmit the next packet # 3 (D4). At this time, when a code error is detected in D2, even if there is only one bit error in the packet, the state cannot be recognized, so the entire packet is discarded.

Although an example of the SW method has been given here, GB
In the N system and the SR system, a method of giving a sequence number, which is a serial number, to a packet itself and returning the sequence number of the packet as an ACK or NAK is also generally used.

FIG. 12 shows a functional block diagram of a transmitting station in an error compensating apparatus according to the conventional system. In the figure, 10
0 is a code error detection code adding circuit, 101 is a transmission buffer, 10
2 is a control information circuit, 103 is a transmission state management table, and 104 is a control information receiving circuit. When a packet to be transmitted is input to the transmitting station, first, an error detection code is provided by an error detection code providing circuit 100. The packet to which the error detection code is added is temporarily stored in the transmission buffer 101 and transmitted according to the instruction of the transmission control circuit 102. The receiving station returns control information indicating the reception state as to whether the packet was successfully received without a code error.The control information receiving circuit 104 receives the information, and the content is stored in the reception state management table 103. Manage. Transmission control circuit 102
When deciding the packet to be transmitted, the transmission state management table 103 is referred to and the transmission packet is selected.

In the case of the SW system, ACK / NAK of the last transmitted packet is notified in the control information, and the transmission state of the last transmitted packet is simply recorded as ACK / NAK in the transmission state management table 102. However, in the case of the SR method or the like, a packet transmission state is recorded for each sequence number assigned to a packet to be transmitted.

FIG. 13 shows a functional block diagram of a receiving station in the error compensating apparatus according to the conventional system. In the figure, 10
5 is an error detection circuit, 106 is a reception buffer, 107 is a reception state management table, and 108 is a control information generation circuit. At the receiving station, first, when a packet is received, an error detection circuit
A packet is input to 105, and a code error is detected. At this time, if an error is detected in the packet, the packet is discarded, and only the packet having no code error is received.
Is input to In the case of the GBN system or the SR system, a sequence number is assigned to a packet, and the reception buffer 10
The sequence number of the received packet is managed in the reception state management table 107 by referring to the sequence number at the time of storing the packet in 6. In the control information generation circuit 108, (1) the sequence number of the normally received packet is notified as ACK, or (2) the sequence number of the normally received packet is confirmed by the continuity of the packet. Either the sequence number of the packet is reported as a NAK, or the transmitting station is notified of the receiving state by either method. The transmitting station determines a packet to be transmitted according to the control information indicating the reception state, and transmits a new packet or retransmits the packet as necessary.

In the case of the SW method, the control information generation circuit 108 may simply notify ACK or NAK as described with reference to FIG. 10 without using a sequence number.

[0010]

In particular, in a communication system using a wireless channel, since frequency resources are limited, efficient packet transmission is required. In addition, regardless of wired or wireless, in the retransmission control at the time of a code error, delay due to signal propagation is unavoidable, so that the transmission of the packet can be completed with a small number of retransmissions especially in a service that requires real-time performance. Is required.

Particularly, in wireless communication, bit errors on a transmission path cannot be ignored, and sometimes a packet error rate (PER) is 0.1.
It may be operated in a poor environment. An effective method for improving such poor PER characteristics is error compensation by retransmission. For example, if retransmission is performed N times, the final PER becomes PER ^{N + 1} , and in principle, it is possible to improve the PER characteristic to an arbitrary level. However, it cannot be ignored that the delay time increases in proportion to the number of retransmissions and that the transmission efficiency decreases due to the band wasted due to the retransmission.

In the conventional error compensation by retransmission, since error detection is performed on a packet basis, even if a bit in which a code error actually occurs is a part, it is not possible to specify the location. For example, if the bit of another part is wrong at the time of retransmission, if the place where the code error occurs can be limited, the correct bit parts of two packets are combined and the bits are selectively replaced to efficiently compensate for the error. Can be performed. In this case, due to the effect of the bit combination, the packet error rate at the time of retransmission is improved over the PER at the time of the first transmission, and as a result, the delay time and the transmission efficiency are improved. However, since the place where the code error occurs cannot be limited, such partial bit replacement cannot be performed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for efficiently estimating a place where a code error has occurred and for partially replacing a retransmitted packet at a bit level, and an error compensation method using the method. It is to provide a device.

[0014]

Means for Solving the Problems To solve the above problems,
For this reason, the present invention provides a method for detecting errors in transmitted data,
Error compensation method for compensating code errors by retransmitting data
, If a code error is detected in the retransmitted data
In this case, on the receiving station side, for integers N and M of 2 or more,
Bit string of retransmission data of the data length of the data ｛DATA # 1 (1) to D
ATA # 1 (N)｝ and data transmitted prior to this data
Each of {DATA # 2 (1) to DATA # 2 (N)} is an integer k₁, K_Two,
... k_M-11 ≦ k₁, K₁+ 1 ≦ k_Two, K_Two+ 1 ≦ k_Three, ... k
_M-2+ 1 ≦ k _M-1, K_M-1M partial bit strings ｛DA where + 1 ≦ N
TA # 1 (1) ~ DATA # 1 (k₁)｝ ｛DATA # 1 (k₁+1) to DATA # 1 (k_Two)｝
・ ・ ・ ｛DATA # 1 (k_M-1+1) ~ DATA # 1 (N)｝ and ｛DATA # 2 (1)
~ DATA # 2 (k₁)｝ ｛DATA # 2 (k₁+1) to DATA # 2 (k_Two)｝ ・ ・ ・
｛DATA # 2 (k_M-1+1) ~ DATA # 2 (N)｝, ｛DATA # 1 (1) ~
DATA # 1 (k₁)｝ Or ｛DATA # 2 (1) ~ DATA # 2 (k₁)｝, ｛DATA #
1 (k₁+1) to DATA # 1 (k_Two)｝ Or ｛DATA # 2 (k₁+1) ~ DATA # 2
(k_Two)｝, ｛DATA # 1 (k_Two+1) to DATA # 1 (k_Three)｝ Or ｛DATA # 2 (k
_Two+1) to DATA # 2 (k_Three)｝, ・ ・ ・ ｛DATA # 1 (k_M-2+1) to DATA # 1
(k_M-1)｝ Or ｛DATA # 2 (k_M-2+1) to DATA # 2 (k_M-1)｝, ｛DA
TA # 1 (k_M-1+1) ~ DATA # 1 (N)｝ or ｛DATA # 2 (k_M-1+1) to DAT
A # 2 (N)｝, the original bit string ｛DATA # 1 (1) ~ DATA #
1 (N)｝ and new data different from {DATA # 2 (1) ~ DATA # 2 (N)}
Create bit strings {DATA # 3 (1) to DATA # 3 (N)}
Error detection for the data sequence {DATA # 3 (1) to DATA # 3 (N)}.
This bit string if no code error is detected.
Handle {DATA # 3 (1) ~ DATA # 3 (N)} as regular received data
It is what we did.

In the conventional method, received data in which a code error is detected is not completely discarded, new data is generated by combining two error data, and if no error is detected in this data, normal reception is performed. They differ in that they are considered data.

Also, two types of bit strings {DATA # 1 (1) to DATA # 1 (N)} and {DATA # 2, retransmission data and previous transmission data
(1) to DATA # 2 (N)｝ are compared in bit units, and DATA # 1 (i) = D
ATA # 2 (i) and DATA # 1 (i + 1) ≠ DATA # 2 (i + 1) or DATA # 1
(i) ≠ DATA # 2 ( i) and DATA # 1 (i + 1) = DATA # 2 (i + 1) and comprising dividing position of an integer i the partial bit string _{k 1, k 2, ··· k} M _-1
It is also preferred to use This is done by separating a partial bit string that is expected to have a code error from a partial bit string that is expected to have no code error, and replacing only the partial bit string that is expected to have a code error with the other data. The present invention proposes a simple implementation method for reducing the number and selectively generating only a bit string that is likely to include normal reception data.

On the other hand, in order to realize the above error compensation method on a device, the present invention provides a receiving station in which a first error detection circuit for detecting an error of received data and a data for which a code error is detected are temporarily transmitted. An intermediate buffer for storing, a new bit string generation circuit for generating new data by combining the data stored in the intermediate buffer with newly received retransmission data, and an individual bit stream for one or a plurality of the generated bit strings. And a selector for selecting and outputting data having no code error based on the detection result of the second error detection circuit and the result of the first error detection circuit. . It differs from the conventional device in that it has an intermediate buffer, a new bit string generation circuit, a second error detection circuit, and a selector.

Further, it is preferable that the new bit string generation circuit comprises a bit comparison circuit, a bit string switching circuit, and a new bit string output control circuit.

Further, it is preferable that the new bit string output control circuit is constituted by an L-bit shift register, an OR circuit, and a 2-bit shift register.

In the present invention, means for comparing the retransmitted data with the previously received data on a bit-by-bit basis, estimating a partial bit string expected to contain a code error, and retransmitting the data or the previously received data on a per bit basis And a means for creating one or more new bit strings by this means. Therefore, even if there is a code error in the retransmission data, an error is generated by combining the retransmission data and the previous reception data. Correction can be performed, and as a result, the error correction efficiency can be improved, and the effect of performing efficient error retransmission control in a short time and with a small bandwidth can be obtained.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a processing flow on the receiving station side in one embodiment of the present invention. Upon receiving the packet (S1), the receiving station detects a code error in the received packet (S2). If there is a code error, the packet is temporarily stored in an intermediate buffer (S3). If this packet is not received for the first time (S4), that is, if the packet corresponding to the intermediate buffer has already been received once, the corresponding packet and the currently received packet are combined to newly create a new bit string. (S5). At this time, the number of patterns of the newly created new bit string is generally plural, and therefore, a code error check is independently performed on the plurality of new bit strings (S6 to S8). When a packet having no code error is detected in these, one pattern is selected from among them (S9). On the other hand, a packet having a code error is discarded (S10). Thereafter, if any of the received data or the new bit string does not include any one with no code error (S11), a retransmission request is made (S12), and a series of processing is completed (S13).

The invention described in claim 1 of the present application is:
This processing flow is defined.

Here, there are various methods for creating a new bit string, and N-bit bit strings D1 (1) to D1 (N) of previously received data and N-bit bit string D2 of retransmitted data are used.
For example, (1) to D2 (N) are divided into a plurality of blocks at fixed delimiter positions, and a new bit string is created by combining each block. For example, a method of trying to replace only two bits between the two data with respect to the bits not to be used can be considered. In general, it is expected that the probability of obtaining normal reception data will increase as the number of variations of the new bit string to be created increases, but it is difficult to create an enormous number of new bit strings and perform error detection for each. It is. For this reason, in practice, it is necessary to consciously consider the bit error occurrence pattern (characteristic) of the received data and to devise so that a correct bit string is included in a smaller variation.

In particular, it is known that when Viterbi decoding is used as error correction, a code error occurs in a burst. FIG. 2 shows an example of creating a new bit string at the time of a burst error. The figure shows the previously received data, the newly received (retransmitted) data, the result of comparison of each data in bit units, and three new bit strings created. In the previous received data and the new received data, ○ indicates a bit without a code error, and × indicates a bit with a code error. In the comparison result of each data in bit units, ○ indicates bit coincidence, and × indicates bit non-coincidence. The receiving station does not know whether or not each bit has a code error. However, comparing the previously received data with the newly received data, k ₁ +1 to k ₂ are determined as an area where the bits do not match the entire N-bit bit string. , And k ₃ +1 to k ₄ . Thus, by performing such a replacement operation by blocking such an area, it is possible to suppress the overall processing amount. The invention described in claim 2 of the present application defines processing as shown in FIG.

Here, in FIG. 2, a case where bits are continuously erroneous when a burst error occurs is selected as an example. However, in reality, a state in which the presence or absence of a code error is mixed is continuous in a burst. FIG. 3 shows an outline of an actual error pattern and blocking. For example, if an error occurs in the bit of which the bit number of the previously received data or the newly received data is 9, 11 to 13, 15, or 17, if the bit comparison result is as shown in FIG. , 11-13, 15, and 17 do not match. As shown in FIG. 2, when the block is formed for each unmatched bit, the bit numbers are 8, 9, 10, 13, 14, 15, 16,
You must set a block break at position 17. However, this leads to an enormous variation of bit replacement, and it is required to reduce the processing amount by further blocking. In such a case, the area where the bit comparison results match does not continue, that is, when the bit number is 9
Regions Nos. To 17 may be regarded as error blocks, and bits may be replaced in this unit. The invention described in claim 3 of the present application defines processing as shown in FIG.

In order to realize the processing shown in FIG. 3, it is necessary to determine whether or not to block from bit comparison result information in which several bits are continuous. This can be easily realized using a shift register. is there. FIG. 4 is a diagram showing a processing flow for creating a new bit string using a shift register in one embodiment of the present invention. The new bit string to be created is assumed to be m types for convenience of description, and each bit is represented as d (1) to D (m).

When the bits of the previously received data and the newly received data stored in the intermediate buffer are input (S14),
The previous received data is D1 and the new received data is D2 (S1
5) The contents of R (2) to R (L) in the L-bit shift register are shifted (S16). Then, D1 and D2 are compared (S17). If they match, R (1) = 0 is input to the shift register (S18), and if they do not match, R (1) = 1 is input (S19).
Next, the 2-bit shift register is shifted to r (2) = r (1) and R
(1) = 0 is set in (S20), and r (1) is ORed with each register value of the previous L-bit shift register, and the value is input (S2)
1). Here, when r (1) = 0 (S22), since the two bits D1 and D2 match, the replacement process of each bit is unnecessary, and D1 is adopted for convenience (S23). ). On the other hand, if r (1) = 1, there is a possibility that D1 and D2 of the corresponding bits do not match, and therefore, determination processing of m types of new bit strings (S24 to S31) is performed. When r (1) = 1 and r (2) = 1 (S24), it indicates that the error block continues, and when r (1) = 1 and r (2) = 0 (S24) indicates that a new error block has started. Here, the serial number n is set to the error block, and when r (1) = 1 and r (2) = 0 (S24), the count is incremented (S25). The function P (k, n) used in the condition determination of S27 is a function indicating whether or not bit replacement of the n-th error block in the k-th new bit string is performed. Here, P (k, n) = 1 When P (k, n) = 0, no replacement. Referring to this function, if P (k, n) = 1 (S27), set d (k) = D1 to (S2
8) If P (k, n) = 0 (S27), d (k) = D2 (S29) is selected. The above processing is performed on m types of new data strings (S31), the obtained bits are output (S32), and a series of processing ends (S33).

The invention described in claim 4 of the present application
This processing flow is defined. Claim 2
Is equivalent to the case where L = 1 in the above processing, and in this case, the L-bit shift register is unnecessary. The reason for using the L-bit shift register is
Even if the bit comparison results match in the error block, L-
This is because if it is 1 bit or less, it is regarded as one error block.

The function P (k, n) is defined in advance.
For example, in FIG. 2, if the initial value of n is 0,
Function P (k, n) for generating new bit strings (1) to (3)
Is P (1,1) = 1, P (1,2) = 0, P (2,1) = 1, P (2,2) = 1, P (3,1) = 0, P (3, 2) = 1 (Equation 1) is defined. In general, the larger the maximum value of the number of error blocks that can be handled is, the higher the probability of obtaining normal received data is, but the hardware scale increases accordingly. Therefore, the maximum value of the number of error blocks that can be dealt with is limited, and P (k, n) = 0 for the n larger than that is treated as (Equation 2). As an example, an example of a function when the maximum value of n is 3 is shown in (Equation 3). P (1,1) = 1, P (1,2) = 0, P (1,3) = 0, P (2,1) = 0, P (2,2) = 1, P (2,3 ) = 0, P (3,1) = 0, P (3,2) = 0, P (3,3) = 1, P (4,1) = 1, P (4,2) = 1, P (4,3) = 0, P (5,1) = 1, P (5,2) = 0, P (5,3) = 1, P (6,1) = 0, P (6,2) = 1, P (6,3) = 1 (Equation 3) In this case, the number of new bit strings generated is 6 (that is, P
(k of (k, n) takes 1 to 6).

FIG. 5 is a functional block diagram of a receiving station in the error compensating apparatus according to one embodiment of the present invention. In the figure, 1 is a first error detection circuit, 2 is a new bit string generation circuit, 3 is an intermediate buffer, 4 to 7 are second error detection circuits,
8 is a selector, 9 is a control information generation circuit, 10 is a reception state management table, and 11 is a reception buffer.

In the receiving station device, the first packet error detection device 1 determines the presence or absence of a code error in the received packet, and outputs the packet to the selector 8 if there is no code error. On the other hand, if a code error is detected, it is output to the new bit string generation circuit 2, and if there is data previously received in this packet (that is, if the packet is retransmitted), a new bit string is generated. The data input to the new bit string generation circuit 2 is stored in the intermediate buffer 3 together with the generation of the new bit string,
At the time of the next retransmission, a new bit string is generated by the data in the intermediate buffer 3 and the retransmission packet received next time. A plurality of (or one) new bit strings generated by the new bit string generation circuit 2 are input to the second error detection circuits 4 to 7, respectively, and independently detect code errors. here,
The normally received packet for which no code error has been detected is then output to the selector 8. Second error detection circuits 4 to 7
In such a case, a code error may not be detected in a plurality of circuits, and the number of normally received packets input to the selector 8 is not limited to one. The selector 8 selects any one of the input packets and outputs the selected packet to the reception buffer 11. Subsequent processing is the same as the processing of the receiving station in the conventional method described with reference to FIG. 13, and the reception state is managed by the reception state management table 10. The control information generation circuit 9 generates control information for notifying the reception state of the packet,
Return it to the transmitting station.

The difference between the conventional system and the present invention is that a new bit string generation circuit 2 and an intermediate buffer 3 are provided between the error detection circuit 105 (corresponding to the first code error detection circuit 1 of the present invention) and the reception buffer 106 in the conventional system. , The second error detection circuits 4 to 7 and the selector 8 are added, and there is no change in other parts related to control.

The invention described in claim 8 of the present application is:
This defines the configuration of the receiving station in this error compensator.

FIG. 6 is a functional block diagram of a new bit string generation circuit according to one embodiment of the present invention. In the figure,
12 is a bit comparison circuit, 13 is a new bit string output control circuit, 14
Indicates a bit string switching circuit. Further, in order to show the connection relationship of this circuit, the first error detection circuit 1 and the intermediate buffer 3 described with reference to FIG. 5 are also shown.

The input signal from the first error detection circuit 1 is branched into two systems inside the new bit string generation circuit 2, and one of them is returned to the intermediate buffer 3 for storage for the next retransmission. The other is input to the bit comparison circuit 12.
In the intermediate buffer, bits are output in response to the input of the received data, and the bit comparison circuit compares the newly received data with the data from the intermediate buffer 3 on a bit-by-bit basis. The comparison result is input to the new bit string output control circuit 13, and the new bit string output control circuit 13 controls the output of the bit string of the bit string switching circuit 14 based on the comparison result and its history. New reception data (retransmission data) and previous reception data are input in parallel to the bit switching circuit 14, and one of the output bit strings is output. When there are a plurality of outputs of the new bit string, the rules for selecting these outputs are different for each. This selection rule is given by, for example, the above-described function P (k, n).

FIG. 7 is a functional block diagram of a new bit string output control circuit according to one embodiment of the present invention. In the figure, 15 is an L-bit shift register, 16 is an OR circuit, and 17 is 2
2 shows a bit shift register. Further, in order to show the connection relation of this circuit, the bit comparison circuit 12 and the bit string switching circuit 14 described with reference to FIG. 6 are also shown.

When the comparison result from the bit comparison circuit 12 is input to the L-bit shift register 15 as 0 (coincidence) or 1 (non-coincidence), each data of R (1) to R (L-1) is bit by bit. The result is shifted and the comparison result input to R (1) is recorded.
Next, each value from R (1) to R (L) is input to the OR circuit 16,
If at least one of the comparison results does not match, “1” is determined to be in an erroneous block. If all comparison results match, “0” is determined to be in a normal block, and the 2-bit shift register is used. Output to 17. The 2-bit shift register 17 shifts the value of the register of r (1) to r (2), and
Record the new entry in (1). Here, r (1) and r (2) and the current state are normal block continuation when r (1) = 0 and r (2) = 0, and r (1) = 0 and r (2 If) = 1, transition from abnormal block to normal block, if r (1) = 1 and r (2) = 0, transition from normal block to abnormal block, r (1) = 1 a
When nd r (2) = 1, it indicates that an abnormal block is being continued. In response to this state, the bit string switching circuit 14 switches the output bit string. Switching of the output bit string at this time has been described with reference to FIG.

FIG. 8 is a diagram showing the insertion position of the sequence number estimating circuit in the error compensator according to one embodiment of the present invention. In the figure, 2 is a new bit string generation circuit,
Reference numeral 3 denotes an intermediate buffer, 9 denotes a control information generation circuit, and 18 denotes a sequence number estimation circuit. This figure is a diagram in which a part around the intermediate buffer 3 in the functional block of the receiving station in the error compensator in FIG. 5 is extracted.

In practicing the present invention, it is one problem to associate a retransmitted packet with a packet transmitted prior to the retransmitted packet. In the case of the SW method described in the conventional method, since the corresponding packet is always transmitted after the error packet, the correspondence can be easily achieved.
The N method and the SR method require some contrivance. In the simplest method, the sequence number of the packet passed through the new bit string generation circuit 2 is referred to by the sequence number generation circuit 18 as described in claim 6 of the present invention. This is a method of associating a write address with a packet. In this case, if there is an error in the sequence number part, there is a possibility that the association of packets will be incorrect,
Since the error check is performed again by the second error detection circuits 4 to 7, a slight error is allowed in the association of the packets.

Another method for associating packets is the method defined in claim 7 of the present invention. In the case of the conventional GBN method or SR method, the receiving station detects an error packet by referring to the continuity of the sequence number given to the received packet, and notifies the transmitting station side of this sequence number. Request retransmission. For example, in the case of the GBN system, the notified sequence number S
The packet of N is retransmitted first, and thereafter, packets of consecutive sequence numbers such as SN + 1, SN + 2, SN + 3,... Even in the case of the SR method, if the provision is made such that the sequence number for which a retransmission request has been made is transmitted first, and then continuous transmission of new packets is defined, packets transmitted by the transmitting station can be transmitted even at the receiving station side. Can be estimated. In FIG. 8, the sequence number of the retransmission request output from the control information generating circuit 9 is referred to by the sequence number estimating circuit 18, and based on this information, the sequence number of the packet that the transmitting station will transmit later. Is estimated. If no code error occurs in the sequence number notified to the transmitting station, the transmitting station outputs packets in the order estimated by the receiving station. If a code error occurs in the notified sequence number, the danger of an error occurring in the handling of the packet cannot be completely avoided, but finally the second error detection circuits 4 to 7 check the error. Therefore, in this case as well, some errors are allowed in the association of the packets.

The embodiments described above all illustrate the present invention by way of example and not by way of limitation, and the present invention can be embodied in various other modified and modified forms. Therefore, the scope of the present invention is defined only by the appended claims and their equivalents.

[0043]

First, assuming that the present invention is applied to a wireless ATM, a fading environment in which orthogonal frequency division multiplexing (OFDM) and convolutional code / Viterbi decoding are used will be considered. When using Viterbi decoding, bit errors in decoded data tend to be bursty. Furthermore, in the case of OFDM using multiple carriers, the BER
Since the characteristics are different, a burst-like error occurs only at the point where the subcarriers having deteriorated quality are continuous. Therefore,
When both methods are used together, the burstiness of the code error is extremely high, and the normal block and the error block tend to be separated clearly as shown in FIG. If this feature is utilized, it is possible to improve the code error characteristics at the time of retransmission by using the present invention.

FIG. 9 shows a characteristic improvement effect of the present invention in a fading environment when orthogonal frequency division multiplexing (OFDM) and convolutional code / Viterbi decoding are used. D8PSK is used as a modulation method, and a coding rate R = ２ and a constraint length K = 7 in Viterbi decoding. Other parameters include 48 OFDM carriers and 25
0nsec, 1 packet length is 6-OFDM symbol (576 bits),
The number of error blocks that can be handled (maximum value of n) was 4, the number of generated new bit strings (maximum value of k) was 14, and the number L of stages of the shift register was 6. In the figure, the horizontal axis represents the reception Eb / No, the right vertical axis represents the packet error rate (PER: Packet Error Rate), and the left vertical axis represents the probability (PRR: Packet Revival) of the packet rescued by the present invention when a retransmission packet error occurs. Rate).

In the evaluation, the zone edge of the service area in the wireless ATM is assumed, and the evaluation is performed in the vicinity of the condition of about 0.1 as the PER limit quality. For example, when the normal PER is 0.1 (Reception Eb / No is about 16.6d
B) The remedy probability that a packet in which a code error has occurred can be treated as a normal packet by applying the present invention is about 74.7% (that is, the PER at the time of retransmission is 2.53 × 10 ⁻² ). this is,
This is equivalent to achieving the PER improvement effect (10 ^-6 ) of performing the retransmission five times in the conventional method with about three retransmissions. For example, PER after retransmission is required quality of service
If 1.0 × 10 ⁻⁶ is required, the conventional method requires five retransmissions, but according to the present invention, the required quality can be almost brought close to three retransmissions.

As described above in detail, according to the present invention, even when a received retransmission packet has a code error, a normal packet is reproduced by combining the previous reception packet and the retransmission packet, and Can be improved, and as a result, it is possible to reduce the time required for packet transmission completion and to suppress the waste of bandwidth due to retransmission. As a result, especially in a high-speed wireless system such as a wireless ATM or the like, even if the code error characteristics of the transmission path are poor, it is possible to efficiently perform error compensation by retransmission.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow on a receiving station side according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of creating a new bit string at the time of a burst error.

FIG. 3 is a diagram showing an outline of an actual error pattern and blocking.

FIG. 4 is a diagram showing a processing flow for creating a new bit string using a shift register in one embodiment of the present invention.

FIG. 5 is a diagram showing functional blocks of a receiving station in the error compensation device according to one embodiment of the present invention.

FIG. 6 is a diagram illustrating functional blocks of a new bit string generation circuit according to an embodiment of the present invention.

FIG. 7 is a diagram showing functional blocks of a new bit string output control circuit according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating an insertion position of a sequence number estimating circuit in the error compensation device according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating a characteristic improvement effect according to the present invention in a fading environment when orthogonal frequency division multiplexing (OFDM) and convolutional code / Viterbi decoding are used.

FIG. 10 is a diagram showing an algorithm of retransmission control on the receiving station side at the time of packet reception in the conventional method.

FIG. 11 is a diagram illustrating an operation outline of a SW (Stop and Wait) method.

FIG. 12 is a diagram showing functional blocks of a transmitting station in an error compensating apparatus according to a conventional method.

FIG. 13 is a diagram showing functional blocks of a receiving station in the error compensating apparatus according to the conventional method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first error detection circuit 2 new bit string generation circuit 3 intermediate buffer 4 to 7 second error detection circuit 8 selector 9 control information generation circuit 10 reception state management table 11 reception buffer 12 bit comparison circuit 13 new bit string output control circuit 14 bit string switching Circuit 15 L-bit shift register 16 OR circuit 17 2-bit shift register 18 Sequence number estimation circuit 100 Code error detection code adding circuit 101 Transmission buffer 102 Control information circuit 103 Transmission state management table 104 Control information reception circuit 105 Error detection circuit 106 Reception buffer 107 Reception state management table 108 Control information generation circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuaki Mochizuki 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Inside Japan Telegraph and Telephone Corporation (72) Inventor Masahiro Umehira 3-19, Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Nippon Telegraph and Telephone Corporation F term (reference) 5K014 AA03 BA00 DA02 FA00 FA05 5K030 GA12 HA08 JL01 JL07 LA02 MB13 MB20 MC06 9A001 CC02 CC05 EZ04 FZ01 JJ18 LL18

Claims (12)

[Claims] An error detection code is added together with data on a wired or wireless transmission path to transfer data. When a code error is detected on the receiving station side by the error detection code, the code is re-transmitted to retransmit the code. An error compensation method for performing error compensation, wherein, when a code error is detected in retransmitted data, a bit string of retransmitted data having a data length of N bits for the integers N and M of 2 or more at the receiving station side. DATA # 1 (1) ~ DATA # 1
(N)} and data transmitted prior to the data {DATA #
2 (1) to DATA # 2 (N)｝ are each represented by an integer k ₁ , k ₂ ,... K
1 ≦ k ₁ to _{M-1, k 1 + 1} ≦ k 2, k 2 + 1 ≦ k 3, ··· k M-2 + 1 ≦
_M partial bit strings kDATA # 1 (1) satisfying k _M-1 and k _M-1 + 1 ≦ N
~ DATA # 1 (k ₁ )｝ ｛DATA # 1 (k ₁ +1) ~ DATA # 1 (k ₂ )｝ ・ ・ ・
｛DATA # 1 (k _M-1 +1) ~ DATA # 1 (N)｝ and ｛DATA # 2 (1) ~ DATA
# 2 (k ₁ )｝ ｛DATA # 2 (k ₁ +1)-DATA # 2 (k ₂ )｝ ・ ・ ・ ｛DATA # 2
(k _M-1 +1) to DATA # 2 (N)｝, and are divided into {DATA # 1 (1) to DATA # 1 (k
₁ )｝ or ｛DATA # 2 (1) to DATA # 2 (k ₁ )｝, ｛DATA # 1 (k ₁ +1)
~ DATA # 1 (k ₂ )｝ or {DATA # 2 (k ₁ +1) ~ DATA # 2 (k ₂ )｝,
_{{DATA # 1 (k 2 +1} ) ~DATA # 1 (k 3)} or _{{DATA # 2 (k 2 +1} ) ~DA
TA # 2 (k ₃ )｝, ・ ・ ・ ｛DATA # 1 (k _M-2 +1) ~ DATA # 1 (k _M-1 )｝
Or {DATA # 2 (k _M-2 +1) to DATA # 2 (k _M-1 )}, ｛DATA # 1 (k
_M-1 +1) ~ DATA # 1 (N)｝ or ｛DATA # 2 (k _M-1 +1) ~ DATA # 2
(N)｝ combined with DATA # 1 (1) to DATA # 1 (N)｝ and DATA #
2 (1) ~ DATA # 2 (N)｝ New bit string ｛DATA # 3
(1) -DATA # 3 (N)}, and the bit string {DATA # 3 (1) -D
ATA # 3 (N)} is subjected to error detection, and if no code error is detected, the bit string {DATA # 3 (1) to DATA # 3
(N) An error compensation method characterized in that｝ is treated as normal reception data. 2. The error compensating method according to claim 1, wherein the receiving station uses the two types of bit strings {DATA # 1 (1) to D ## 1 (D)}.
ATA # 1 (N)} and {DATA # 2 (1) to DATA # 2 (N)} are compared in bit units, and DATA # 1 (i) = DATA # 2 (i) and DATA # 1 (i + 1) DAT
A # 2 (i + 1) or DATA # 1 (i) ≠ DATA # 2 (i) and DATA # 1 (i + 1)
= DATA # 2 (i + 1 ) and comprising an integer i division position of the partial bit string according to the first aspect k _1, k _2, error compensation method, which comprises using as ··· k _M-1. 3. The error compensation method according to claim 2, wherein the receiving station is an adjacent division position of the partial bit string determined by the method of claim 2, and j ₁ <j ₂ < j ₃
To the integer j _1, j _2, j ₃ consisting, DATA # 1 (j1) ≠ DATA # 2 (j 1) and _{DATA # 1 (j 2) =} DATA # 2 (j 2) and DATA # 1 (j ₃ ) ≠ DATA # 2 (j ₃ )
In the case of, when j ₂ −j ₁ is smaller than a predetermined threshold value, _three partial bit strings having j ₁ , j ₂ , and j ₃ as division positions are replaced with one partial bit string having j ₃ as a division position. An error compensation method characterized by limiting the types of newly created bit strings. 4. The error compensation method according to claim 1, wherein the receiving station includes an L-bit shift register R (1) to R (L) for an integer L, and an N-bit bit string DATA # 1 (1)
~ DATA # 1 (N)｝ and {DATA # 2 (1) ~ DATA # 2 (N)｝
From the first bit to the N-th bit, the register value is shifted while the comparison result of whether the bits match or not matches is input to the shift register, and the result is shifted from R (1) to R (L). If at least one result indicates a mismatch, the bit is regarded as an erroneous bit, while if all of R (1) to R (L) indicate a match, the bit is normal. An error compensating method, wherein positions where normal bits and error bits are replaced are used as division positions k ₁ , k ₂ ,... K _M-1 of the partial bit sequence. 5. The method according to claim 1, wherein
The error compensation method described in the section, wherein the original bit string {DATA # 1 (1) to DATA # 1 (N)} or {DATA # 2
From (1) to DATA # 2 (N)｝, only a part of the partial bit strings are replaced with the other partial bit strings, and a new bit string ｛DATA # 3 (1)
~ DATA # 3 (N)}, and in the partial bit string replacement process, only partial bit strings other than the partial bit strings in which all bits of the partial bit strings completely match are limited to replacement targets. Error compensation method. 6. The method according to claim 1, wherein
Item, wherein the transmitting station adds a sequence number, which is a serial number of data, to the transmitted data and transmits the data, and the receiving station transmits data normally received without a code error. Confirm the continuity of the sequence number has been assigned to, select the data in which a code error has occurred by detecting a discontinuous sequence number, all or part of the discontinuous sequence number The transmitting station notifies the transmitting station, and the transmitting station retransmits only the data to which the notified sequence number has been assigned, or a series of data including the data to which the notified sequence number has been assigned, thereby causing a code error. An error compensation method for compensating, wherein when associating the retransmitted data with data transmitted prior to the retransmitted data, the method is added to each received data. An error compensating method, wherein the sequence number obtained is used. 7. The method according to claim 1, wherein
Item, wherein the transmitting station adds a sequence number, which is a serial number of data, to the transmitted data and transmits the data, and the receiving station transmits data normally received without a code error. Confirm the continuity of the sequence number has been assigned to, select the data in which a code error has occurred by detecting a discontinuous sequence number, all or part of the discontinuous sequence number The transmitting station notifies the transmitting station, and the transmitting station retransmits only the data to which the notified sequence number has been assigned, or a series of data including the data to which the notified sequence number has been assigned, thereby causing a code error. An error compensation method for performing compensation, wherein the receiving station, according to the content of the sequence number notified to the transmitting station, a series of transmission next transmitted by the transmitting station When predicting the correspondence between the data and the sequence number assigned to the data, when associating the retransmission data with the data transmitted prior to the retransmission data, the data will be assigned to each data. An error compensation method characterized by performing correspondence by using a predicted value of a sequence number. 8. A data transfer is performed by adding an error detection code together with data on a wired or wireless transmission path, and when a code error is detected on the receiving station side by the error detection code, the code is retransmitted to re-transmit the code. 2. An error compensating apparatus using the error compensating method according to claim 1 for performing error compensation, wherein the receiving station comprises: a first error detecting circuit for detecting an error in received data; An intermediate buffer that is once stored, a new bit string generation circuit that generates new data by combining the data stored in the intermediate buffer and newly received retransmission data, and one or more generated bit strings. A second error detection circuit for individually performing error detection, and selecting and outputting data having no code error based on the detection result of the second error detection circuit and the result of the first error detection circuit. Error compensating apparatus characterized by comprising a selector. 9. The error compensator according to claim 8, wherein the new bit string generation circuit compares a bit stored in the intermediate buffer with newly received retransmission data. A bit string switching circuit that receives two types of bit strings of data stored in the intermediate buffer and newly received retransmission data, selects one of the bits for each bit, and outputs one or more output bit strings. And a new bit string output control circuit for controlling the output from the bit string switching circuit based on the comparison result of the bit comparison circuit and / or its history. 10. The error compensating device according to claim 9, wherein in the new bit string output control circuit, an output signal from the bit comparison circuit is 0 when they match, and 1 when they do not match, For an integer L, an L-bit shift register that stores the history of the output result from the bit comparison circuit for L bits, and each register value R of the L-bit shift register
An OR circuit for calculating the logical sum of the values of (1) to R (L), and a 2-bit shift register for recording the history of the output result of the OR circuit, wherein each register value r (1 ) And r (2) are output as control information to the bit string switching circuit. 11. The error compensating apparatus according to claim 8, wherein the receiving station stores the data in the intermediate buffer. An error compensator comprising a sequence number estimating circuit for estimating a sequence number given to received data using the means described in Item 7. 12. A data transfer is performed by adding an error detection code together with data on a wired or wireless transmission path, and when a code error is detected on the receiving station side by the error detection code,
An error compensation method for compensating a code error by retransmitting data, wherein when a code error is detected in data retransmitted K times (K ≧ 2), the first reception data is retransmitted on the receiving side. All of the K data or two or more of these data are combined to create new bit string data, error detection is performed on the bit string data, and a code error is detected. If not, treat the data of the bit string as correctly received data, and request a K + 1-th retransmission data when a code error is detected in all data of the new bit string. .