JP2000216413A - Bga type transparent plastic semiconductor package - Google Patents

Bga type transparent plastic semiconductor package

Info

Publication number
JP2000216413A
JP2000216413A JP1707899A JP1707899A JP2000216413A JP 2000216413 A JP2000216413 A JP 2000216413A JP 1707899 A JP1707899 A JP 1707899A JP 1707899 A JP1707899 A JP 1707899A JP 2000216413 A JP2000216413 A JP 2000216413A
Authority
JP
Japan
Prior art keywords
transparent plastic
package
bga type
bga
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1707899A
Other languages
Japanese (ja)
Inventor
Hirohito Tanaka
浩仁 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apic Yamada Corp
Original Assignee
Apic Yamada Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apic Yamada Corp filed Critical Apic Yamada Corp
Priority to JP1707899A priority Critical patent/JP2000216413A/en
Publication of JP2000216413A publication Critical patent/JP2000216413A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To make a transparent plate unnecessary, eliminate exposure failure in an inner connection part of BGA type wiring, make conductor for connection hard to be oxidized, improve reliability, and enable miniaturization and reduction of weight and cost. SOLUTION: A photo detecting or light emitting semiconductor element 12 is mounted on one surface of a BGA type wiring board 11. Each of the electrodes of the semiconductor element 12 is connected with a corresponding inner connection part 16 of the BGA type wiring by using conductor 19. By molding, the semiconductor element 12, each conductor 19, and the vicinity of the connection part of the conductor 19 are resin-sealed with transparent plastic, and a transparent plastic package part 27 is formed on one surface of the BGA type wiring board 11.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は受光又は発光半導体
素子を搭載したＢＧＡ型透明プラスチック半導体パッケ
ージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA type transparent plastic semiconductor package on which a light receiving or light emitting semiconductor element is mounted.

【０００２】[0002]

【従来の技術】従来、受光又は発光半導体素子を搭載し
た半導体パッケージとして、外部から受光半導体素子に
光を照射するため或いは発光半導体素子から外部に光を
放出するため、そのパッケージ部を筒状にして中空に
し、そこにガラス、透明プラスチック等の透明板を取り
付けて窓を形成したものが使用されている。なお、受光
又は発光半導体素子はホトダイオード、発光ダイオー
ド、ＣＣＤ、ＥＰＲＯＭ、Ｃ−ＭＯＳ等を適宜組み合せ
て構成したものである。このような中空半導体パッケー
ジの製作時には通常リードフレーム、ＢＧＡ型配線基板
等を用い、そのダイパッドエリア、チップエリア等に受
光又は発光半導体素子を搭載し、更にダイパッドエリ
ア、チップエリア等付近の外周をリング状に被って突出
する筒状のプラスチック製パッケージ部を形成し、その
受光又は発光半導体素子の各電極とリードフレーム等の
内部接続部とをワイヤー等の導電体を用いてそれぞれ接
続し、そのパッケージ部の開口に透明板を取り付け閉鎖
するという工程を踏む。2. Description of the Related Art Conventionally, as a semiconductor package on which a light receiving or light emitting semiconductor element is mounted, a package portion is formed in a cylindrical shape in order to irradiate light to the light receiving semiconductor element from outside or to emit light from the light emitting semiconductor element to the outside. In this case, a window is formed by attaching a transparent plate made of glass, transparent plastic, or the like to a hollow. The light-receiving or light-emitting semiconductor element is formed by appropriately combining a photodiode, a light-emitting diode, a CCD, an EPROM, a C-MOS, and the like. When manufacturing such a hollow semiconductor package, a lead frame, a BGA type wiring board, or the like is usually used, and a light receiving or light emitting semiconductor element is mounted in a die pad area, a chip area, and the like. A cylindrical plastic package portion is formed to protrude in a shape, and each electrode of the light-receiving or light-emitting semiconductor element is connected to an internal connection portion such as a lead frame using a conductor such as a wire, and the package is formed. Attach a transparent plate to the opening of the part and close it.

【０００３】すると、図１５に示すような中空半導体パ
ッケージ１が得られる。この中空半導体パッケージ１は
リードフレーム２を使用し、受光半導体素子としてＣＣ
ＤＩＣチップ３を搭載したものである。図中、４はパッ
ケージ部、５は窓透明板、６(６ａ、６ｂ)はワイヤー、
７はリードフレーム２のダイパッドエリア、８(８ａ、
８ｂ)はその内部接続部、９(９ａ、９ｂ)はその外部端
子である。このような中空半導体パッケージ１ではリー
ドフレーム２を反らないようにするため、その両面にパ
ッケージ部４を設置し、その片面側を筒状にしている
が、ＢＧＡ型配線基板を用いたＢＧＡ型中空半導体パッ
ケージでは片面のみに筒状のパッケージ部を設置し、他
面に外部端子となるハンダボールを配設する。なお、中
空半導体パッケージにはセラミック筐体にメッキ配線を
施したものもあるが、そのセラミック筐体の筒状部にや
はり透明板を取り付けて窓を形成している。Then, a hollow semiconductor package 1 as shown in FIG. 15 is obtained. This hollow semiconductor package 1 uses a lead frame 2 and has a CC as a light receiving semiconductor element.
The DIC chip 3 is mounted. In the figure, 4 is a package part, 5 is a window transparent plate, 6 (6a, 6b) is a wire,
7 is a die pad area of the lead frame 2, and 8 (8a,
8b) is its internal connection, and 9 (9a, 9b) is its external terminal. In order to prevent the lead frame 2 from warping in such a hollow semiconductor package 1, package portions 4 are provided on both surfaces thereof, and one side thereof is cylindrical, but a BGA type using a BGA type wiring board is used. In a hollow semiconductor package, a cylindrical package portion is provided only on one side, and solder balls serving as external terminals are provided on the other side. In some hollow semiconductor packages, a ceramic casing is plated with wiring, and a window is also formed by attaching a transparent plate to the cylindrical portion of the ceramic casing.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな中空半導体パッケージではパッケージ部等の筒状開
口を透明板で閉じて窓を形成しているため問題がある。
何故なら、透明板を用いると、製品を小型化、軽量化
し、安価にし難い。しかも、透明板を別途に製作しなけ
ればならず、その透明板を高精度に取り付ける工程等も
必要である。使用中、透明板が脱落することがある。
又、透明板の取り付け時にパッケージ部の内部を真空に
しようとしてもどうしても空気が残る。しかも、使用中
に透明板の接着箇所或いは溶着箇所から内部に空気や水
蒸気が侵入し易い。それ故、受光又は発光半導体素子や
ワイヤー等の接続用導電体に酸化が生じ易く、特に接続
用導電体の酸化が問題になる。However, there is a problem in such a hollow semiconductor package because the window is formed by closing the cylindrical opening of the package and the like with a transparent plate.
This is because using a transparent plate makes it difficult to reduce the size, weight, and cost of the product. In addition, a transparent plate must be separately manufactured, and a step of attaching the transparent plate with high accuracy is required. During use, the transparent plate may fall off.
Further, even if an attempt is made to evacuate the inside of the package portion when the transparent plate is attached, air remains. In addition, air and water vapor easily enter the inside of the transparent plate from the bonding portion or the welding portion during use. Therefore, the connection conductor such as a light-receiving or light-emitting semiconductor element or a wire is easily oxidized, and particularly the oxidation of the connection conductor becomes a problem.

【０００５】又、中空半導体パッケージの製造工程では
プラスチック製の筒状パッケージ部を成形した後、受光
又は発光半導体素子の各電極とリードフレーム等の内部
接続部とをワイヤー等の導電体を用いてそれぞれ接続す
るが、成形時にリードフレーム等の内部接続部に樹脂バ
リが付着する樹脂フラッシュを起こし易い。それ故、接
続前にフラッシュ樹脂の除去工程を実施するが、露出不
良の問題がある。In the manufacturing process of the hollow semiconductor package, after forming a plastic cylindrical package portion, each electrode of the light receiving or light emitting semiconductor element and an internal connection portion such as a lead frame are connected using a conductor such as a wire. Each connection is made, but resin flash is likely to occur when resin burrs adhere to internal connection parts such as a lead frame during molding. Therefore, a flash resin removing step is performed before connection, but there is a problem of poor exposure.

【０００６】本発明はこのような従来の問題点に着目し
てなされたものであり、透明板を必要とせず、ＢＧＡ型
配線の内部接続部に露出不良がなく、接続用導電体が酸
化し難く信頼性に優れた、小型化、軽量化が可能で安価
なＢＧＡ型透明プラスチック半導体パッケージを提供す
ることを目的とする。The present invention has been made in view of such conventional problems, does not require a transparent plate, has no exposure failure in the internal connection portion of the BGA type wiring, and oxidizes the connection conductor. An object of the present invention is to provide an inexpensive BGA-type transparent plastic semiconductor package which is difficult, has excellent reliability, can be reduced in size and weight, and is inexpensive.

【０００７】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明によるＢＧＡ型プラスチック半導体パッケー
ジではＢＧＡ型配線基板の片面に受光又は発光半導体素
子を搭載し、その受光又は発光半導体素子の各電極とＢ
ＧＡ型配線の対応する内部接続部とを導電体を用いてそ
れぞれ接続する。そして、モールド成形によりその受光
又は発光半導体素子及び各接続用導電体とその各接続用
導電体の接続箇所付近を透明プラスチックで樹脂封止し
てＢＧＡ型配線基板の片面に透明プラスチック製パッケ
ージ部を設ける。又、透明プラスチック製パッケージ部
をレンズ一体型に成形すると好ましくなる。In order to achieve the above object, in a BGA type plastic semiconductor package according to the present invention, a light receiving or light emitting semiconductor element is mounted on one surface of a BGA type wiring board, and each of the light receiving or light emitting semiconductor elements is provided. Electrode and B
The corresponding internal connection portion of the GA type wiring is connected using a conductor. The light-receiving or light-emitting semiconductor element and the vicinity of the connection between the connection conductors and the connection conductors are resin-sealed with transparent plastic by molding, and a transparent plastic package portion is formed on one surface of the BGA type wiring board. Provide. It is also preferable that the transparent plastic package is molded into a lens-integrated type.

【０００８】又、本発明による他のＢＧＡ型透明プラス
チック半導体パッケージでは片面にチップエリア用凹所
を設けた透明プラスチック製パッケージ筐体を成形し、
そのチップエリア用凹所付近の表面所定箇所に立体的に
メッキ配線をそれぞれ施してＢＧＡ型配線を設ける。そ
して、そのチップエリアに受光又は発光半導体素子を搭
載し、その受光又は発光半導体素子の各電極とＢＧＡ型
配線の対応する内部接続部とを導電体を用いてそれぞれ
接続する。又、その各接続用導電体と各接続用導電体の
接続箇所付近を少なくとも樹脂封止する。又、透明プラ
スチック製パッケージ筐体をレンズ一体型に成形すると
好ましくなる。In another BGA type transparent plastic semiconductor package according to the present invention, a transparent plastic package housing having a recess for a chip area provided on one side is formed.
A BGA type wiring is provided by three-dimensionally applying plating wiring to a predetermined portion of the surface near the chip area recess. Then, a light-receiving or light-emitting semiconductor element is mounted on the chip area, and each electrode of the light-receiving or light-emitting semiconductor element is connected to a corresponding internal connection portion of the BGA type wiring using a conductor. Further, at least the vicinity of the connection portion between each connection conductor and each connection conductor is resin-sealed. Further, it is preferable that the transparent plastic package housing is molded into a lens integrated type.

【０００９】[0009]

【発明の実施の形態】以下、添付の図１〜１４を参照し
て、本発明の実施の形態を説明する。図１は本発明を適
用したＢＧＡ型配線基板使用によるＢＧＡ型透明プラス
チック半導体パッケージの縦断面図である。このＢＧＡ
型透明プラスチック半導体パッケージ１０は製造時に次
のような工程を踏む。先ず、ＢＧＡ型配線基板例えばＢ
ＧＡ型多層配線基板１１と受光又は発光半導体素子例え
ばＣＣＤＩＣチップ１２を用意する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the attached FIGS. FIG. 1 is a longitudinal sectional view of a BGA type transparent plastic semiconductor package using a BGA type wiring board to which the present invention is applied. This BGA
The following steps are performed at the time of manufacturing the transparent plastic semiconductor package 10. First, a BGA type wiring board such as B
A GA type multilayer wiring board 11 and a light receiving or light emitting semiconductor element, for example, a CCDIC chip 12 are prepared.

【００１０】このＢＧＡ型多層配線基板１１はプラスチ
ック、繊維強化プラスチック等の絶縁基材１３の表面、
内部等に配線パターン１４（１４ａ、１４ｂ）、内部配
線（図示なし）等の層を複数設けてＢＧＡ型配線を構成
し、その片面（上面）中央部をチップエリア１５とし、
そのチップエリア１５付近に配線パターン１４ａの一部
を内部接続部１６（１６ａ、１６ｂ）として配置し、他
面（下面）に配線パターン１４ｂの一部を外部接続部１
７（１７ａ、１７ｂ）として格子状に配置したものであ
る。図中、１８（１８ａ、１８ｂ）は両配線パターン１
４間に介在する内部に被覆導電層を有するスルーホール
である。なお、ＢＧＡ型配線基板としてＢＧＡ型単層配
線基板即ちＢＧＡ型配線を構成するため、同様の絶縁基
材の上面のみに配線パターンを施して内部接続部を形成
し、下面にその配線パターンと接続するスルーホール内
被覆導電層を介して外部接続部を形成したものを使用す
ることもできる。The BGA type multilayer wiring board 11 has a surface of an insulating base material 13 made of plastic, fiber reinforced plastic, or the like.
A plurality of layers such as a wiring pattern 14 (14a, 14b) and an internal wiring (not shown) are provided inside to form a BGA type wiring, and a central portion of one surface (upper surface) is a chip area 15,
A part of the wiring pattern 14a is arranged near the chip area 15 as the internal connection part 16 (16a, 16b), and a part of the wiring pattern 14b is formed on the other surface (lower surface) of the external connection part 1.
7 (17a, 17b) arranged in a lattice. In the figure, 18 (18a, 18b) indicates both wiring patterns 1
This is a through hole having a coating conductive layer in the interior interposed between the four. In order to form a BGA-type single-layer wiring board as a BGA-type wiring board, that is, a BGA-type wiring, a wiring pattern is formed only on the upper surface of the same insulating base material to form an internal connection portion, and the lower surface is connected to the wiring pattern. It is also possible to use one in which an external connection portion is formed via a through-hole covered conductive layer.

【００１１】そして、図２のに示すようにＢＧＡ型多
層配線基板１１の各セクションのチップエリア１５に接
着剤を塗布した後、ＣＣＤＩＣチップ１２をそれぞれ搭
載し、その各チップ１２の各電極とＢＧＡ型配線の対応
する内部接続部１６とをＡｕワイヤー１９（１９ａ、１
９ｂ）でそれぞれ接続する。なお、２０はＣＣＤＩＣチ
ップ１２のＣＣＤセンサー部である。このようにして、
樹脂封止前に各ＣＣＤＩＣチップ１２の各電極とＢＧＡ
型配線の対応する内部接続部１６とをＡｕワイヤー１９
でそれぞれ接続すると、当然その各内部接続部１６に露
出不良等の問題が発生しない。なお、ＣＣＤＩＣチップ
１２にＣ−ＭＯＳを使用すると、外部端子数を多くする
ことができる。Then, as shown in FIG. 2, an adhesive is applied to the chip area 15 of each section of the BGA type multilayer wiring board 11, and then the CCDIC chips 12 are mounted, and the electrodes of each chip 12 and the BGA The Au wire 19 (19a, 1a)
9b). Reference numeral 20 denotes a CCD sensor unit of the CCD IC chip 12. In this way,
Before resin sealing, each electrode of each CCDIC chip 12 and BGA
The corresponding internal connection part 16 of the pattern wiring is connected to the Au wire 19.
In this case, the problem such as poor exposure does not occur in each of the internal connection portions 16. If a C-MOS is used for the CCD IC chip 12, the number of external terminals can be increased.

【００１２】次に、パッケージ部成形用モールド金型装
置を用い、に示すようにそのモールド金型２１には上
側に対応するプラスチック成形用キャビテイ２２を有す
る上金型２３を備え、下側にプラスチック成形用キャビ
テイがなく、ＢＧＡ型配線基板１１が嵌まる配置用凹所
２４を有する下金型２５を備える。そして、そのモール
ド金型２１内の所定位置にＣＣＤＩＣチップ１２を搭載
し、Ａｕワイヤー１９で接続したＢＧＡ型配線基板１１
をそれぞれ収容し、金型２１のパーティングライン面２
６にその基板１１の上面を一致させる。すると、各キャ
ビテイ２２内にＣＣＤＩＣチップ１２、Ａｕワイヤー１
９等が入る。そこで、上金型２３の各ゲートから対応す
るキャビテイ２２内に、溶融した熱硬化性透明プラスチ
ック例えばユリア樹脂を注入する。Next, using a molding die apparatus for molding a package portion, the molding die 21 is provided with an upper die 23 having a plastic molding cavity 22 corresponding to the upper side as shown in FIG. A lower mold 25 having no molding cavity and having an arrangement recess 24 into which the BGA type wiring board 11 fits is provided. Then, the BGA type wiring board 11 mounted with the CCDIC chip 12 at a predetermined position in the molding die 21 and connected with the Au wire 19.
And the parting line surface 2 of the mold 21
6 is matched with the upper surface of the substrate 11. Then, the CCD IC chip 12 and the Au wire 1 are placed in each cavity 22.
9 mag. Then, molten thermosetting transparent plastic, for example, urea resin, is injected from each gate of the upper mold 23 into the corresponding cavity 22.

【００１３】すると、モールド成形により各セクション
毎にＣＣＤＩＣチップ１２及び各Ａｕワイヤー１９とそ
の各Ａｕワイヤー１９の接続箇所付近を透明プラスチッ
クで樹脂封止してＢＧＡ型配線基板１１の上面に平たい
四角錐台状の透明プラスチック製パッケージ部２７を設
けることができる。次に、必要な場合のみ図３のに示
すようにそのパッケージ部２７の上面に研磨材２８を当
て、矢印方向に移動しながら鏡面状に仕上げ光の透過を
良くする。次に、に示すように上下を反対にし、ＢＧ
Ａ型配線基板１１に設けた配線パターン１４ｂの外部接
続部１７に外部端子となるハンダボール２９（２９ａ、
２９ｂ）をそれぞれ溶融接合する。次に、図４のに示
すように再度上下を反対にして元に戻し、ウォータージ
ェット３０又はダイシングソー３１若しくは切断金型を
用いて個片にカットする。すると、ＢＧＡ型配線基板１
１を用いたＢＧＡ型透明プラスチック半導体パッケージ
１０が完成する。Then, by molding, the vicinity of the connection between the CCD IC chip 12 and each Au wire 19 and each Au wire 19 in each section is resin-sealed with transparent plastic, and a flat quadrangular pyramid is formed on the upper surface of the BGA type wiring board 11. A trapezoidal transparent plastic package 27 can be provided. Next, only when necessary, as shown in FIG. 3, an abrasive 28 is applied to the upper surface of the package portion 27, and the transmission of the finishing light is improved in a mirror surface while moving in the direction of the arrow. Next, turn the BG upside down as shown in
Solder balls 29 (29 a, 29 a) serving as external terminals are connected to the external connection portions 17 of the wiring pattern 14 b provided on the A-type wiring substrate 11.
29b) are respectively melt-bonded. Next, as shown in FIG. 4, the upper and lower parts are again turned upside down, and cut into individual pieces using a water jet 30, a dicing saw 31, or a cutting die. Then, the BGA type wiring board 1
1 is completed using the BGA type transparent plastic semiconductor package 10.

【００１４】このＢＧＡ型透明プラスチック半導体パッ
ケージ１０は、図５に示すように透明プラスチック製パ
ッケージ部２７の内部の２方にＡｕワイヤー１９をそれ
ぞれ複数本例えば５本ずつ収容した上側構造を有し、更
に図６に示すようにＢＧＡ型配線基板１１の下面の２方
にそれぞれ５個ずつハンダボール２９を配設した下側構
造等を有している。なお、ワイヤー１９等は透明プラス
チック製パッケージ２７の内部の４方にそれぞれ必要数
配置してもよく、ハンダボール２９もＢＧＡ型配線基板
１１の下面に必要数格子状に配置してもよい。このよう
にして、ＢＧＡ型配線基板１１の上面に透明プラスチッ
ク製パッケージ部２７を設け、ＣＣＤＩＣチップ１２及
び各Ａｕワイヤー１９とその各Ａｕワイヤー１９の接続
箇所付近を透明プラスチックで樹脂封止して一体成形す
ると、透明板を必要とせず、製品を小型化、軽量化し、
安価にできる。そして、各Ａｕワイヤー１９が酸化し難
くなり、信頼性が向上する。As shown in FIG. 5, the BGA type transparent plastic semiconductor package 10 has an upper structure in which a plurality of, for example, five Au wires 19 are respectively accommodated in two portions inside a transparent plastic package portion 27. Further, as shown in FIG. 6, the BGA type wiring board 11 has a lower structure in which five solder balls 29 are provided on two sides of the lower surface, respectively. The required number of wires 19 and the like may be arranged on four sides inside the transparent plastic package 27, respectively, and the solder balls 29 may be arranged on the lower surface of the BGA type wiring board 11 in the required number of grids. In this manner, the transparent plastic package portion 27 is provided on the upper surface of the BGA type wiring board 11, and the vicinity of the connection between the CCD IC chip 12, each Au wire 19 and each Au wire 19 is resin-sealed with transparent plastic and integrated. When molded, there is no need for a transparent plate, making the product smaller and lighter,
It can be cheap. And each Au wire 19 becomes hard to be oxidized, and reliability improves.

【００１５】上記実施の形態ではＢＧＡ型配線基板１１
の上面に平たい四角錐台状の透明プラスチック製パッケ
ージ部２７を設けたＢＧＡ型透明プラスチック半導体パ
ッケージ１０について説明したが、図７に示すようにそ
の透明プラスチック製パッケージ部３２をレンズ一体型
にして、ＢＧＡ型透明プラスチック半導体パッケージ３
３を製作することもできる。このＢＧＡ型透明プラスチ
ック半導体パッケージ３３の製造工程は上記パッケージ
１０の製造工程とほぼ同一である。しかし、透明プラス
チック製パッケージ部３２にレンズ３４を一体型にする
ため、そのパッケージ部３２の上面中央部にレンズ３４
となる例えば半球を平たくした突部を設け、その突部を
削って表面を非球面レンズ形状等に形成して焦点距離を
設定しなければならない。In the above embodiment, the BGA type wiring board 11
The BGA type transparent plastic semiconductor package 10 provided with a flat quadrangular truncated pyramid-shaped transparent plastic package portion 27 on the upper surface has been described, but as shown in FIG. BGA type transparent plastic semiconductor package 3
3 can also be manufactured. The manufacturing process of the BGA type transparent plastic semiconductor package 33 is almost the same as the manufacturing process of the package 10. However, since the lens 34 is integrated with the transparent plastic package portion 32, the lens 34 is provided at the center of the upper surface of the package portion 32.
For example, a projection having a flattened hemisphere is provided, and the projection is cut to form a surface having an aspheric lens shape or the like, and the focal length must be set.

【００１６】そこで、パッケージ部成形用モールド金型
装置に図８に示すようなモールド金型３５を用いる。そ
して、その上金型３６のキャビテイ３７の天井中央部に
凹所３８を設け、レンズ３４の突部成形用に使用する。
なお、下金型３９にはやはりキャビテイを設けず、ＢＧ
Ａ型配線基板４０が嵌まる配置用凹所４１を設ける。こ
のようにして、モールド成形により透明プラスチック製
パッケージ部３２にレンズ３４を一体化すると、そのパ
ッケージ部３２にレンズ３４を強固に結合して、ＢＧＡ
型透明プラスチック半導体パッケージ３３を簡単にレン
ズ３４付きにすることができる。そして、レンズ３４付
きパッケージ３３を小型化、軽量化し、安価にすること
ができる。Therefore, a molding die 35 as shown in FIG. 8 is used in a molding die apparatus for molding a package portion. Then, a recess 38 is provided at the center of the ceiling of the cavity 37 of the upper mold 36, and is used for forming the projection of the lens 34.
In addition, the lower mold 39 is not provided with a cavity,
An arrangement recess 41 into which the A-type wiring board 40 fits is provided. In this way, when the lens 34 is integrated with the transparent plastic package portion 32 by molding, the lens 34 is firmly connected to the package portion 32 and the BGA
The transparent plastic semiconductor package 33 can be easily provided with the lens 34. And the package 33 with the lens 34 can be reduced in size, weight, and cost.

【００１７】又、上記実施の形態ではＢＧＡ型配線基板
１１、４０を用い、その各上面に透明プラスチック製パ
ッケージ部２７、３２を設けたレンズのない或いはレン
ズ３４付きのＢＧＡ型透明プラスチック半導体パッケー
ジ１０、３３について説明したが、図９に示すような片
面（上面）の中央部にチップエリア用凹所４２を設けた
透明プラスチック製パッケージ筐体４３を用いて、ＢＧ
Ａ型プラスチック半導体パッケージ４４を製造すること
もできる。このＢＧＡ型プラスチック半導体パッケージ
４４は製造時に図１０〜１３に示すような工程を踏む。
先ず、透明プラスチック製パッケージ筐体４３の連続体
を成形するため、パッケージ筐体成形用モールド金型装
置を用いる。In the above embodiment, the BGA type wiring board 11 or 40 is used, and the BGA type transparent plastic semiconductor package 10 without the lens or the lens 34 provided with the transparent plastic package portions 27 and 32 on the respective upper surfaces thereof. , 33 have been described, but a BG using a transparent plastic package housing 43 in which a chip area recess 42 is provided in the center of one surface (upper surface) as shown in FIG.
An A-type plastic semiconductor package 44 can also be manufactured. This BGA type plastic semiconductor package 44 goes through steps as shown in FIGS.
First, in order to form a continuum of the package 43 made of transparent plastic, a mold device for molding a package housing is used.

【００１８】そして、図１０のに示すようにそのモー
ルド金型４５には上側に連続した各パッケージ筐体４３
の上面、周側面等成形用キャビテイ４６をそれぞれ有す
る上金型４７を備え、下側に成形用キャビテイがなく、
連続した各パッケージ筐体４３のチップエリア用凹所４
２を成形する成形用突部４８をそれぞれ有する下金型４
９を備える。すると、モールド金型４５の内部に溶融し
たユリア樹脂等の熱硬化性透明プラスチックを注入し、
透明プラスチック製パッケージ筐体４３の連続体を得る
ことができる。As shown in FIG. 10, each of the package casings 43 connected to the upper side
An upper mold 47 having a molding cavity 46 such as an upper surface, a peripheral side surface, etc. is provided, and there is no molding cavity on the lower side,
Chip area recesses 4 of each successive package housing 43
Lower mold 4 each having a molding projection 48 for molding 2
9 is provided. Then, a molten thermosetting transparent plastic such as urea resin is injected into the mold 45,
A continuum of the transparent plastic package housing 43 can be obtained.

【００１９】次に、に示すように連続した透明プラス
チック製パッケージ筐体４３の上下を反対にし、各パッ
ケージ筐体４３のチップエリア用凹所４２付近の表面所
定箇所に例えばＣｕ＋Ｎｉ−Ｐｄ−Ａｕメッキをそれぞ
れ施し、いずれも表面より若干突出させ立体的な配線５
０（５０ａ、５０ｂ）にする。しかも，これ等の立体メ
ッキ配線５０はパッケージ筐体４３の２方或いは４方に
それぞれ複数本例えば５本ずつ配置し、いずれもパッケ
ージ筐体４３の下面（図では上面）からチップエリア用
凹所４２のボンディングエリアに掛けて設け、ＢＧＡ型
配線に形成する。その際、立体メッキ配線５０の形成法
として、例えば３次元立体マスク法（３Ｄマスク法）を
採用する。なお、３Ｄマスク法の詳細については本出願
人が先に提出した特願平１０−３３８３２９号に記載さ
れている。Next, as shown in the figure, the continuous transparent plastic package housing 43 is turned upside down, and for example, Cu + Ni-Pd-Au plating is performed on a predetermined portion of the surface of the package housing 43 near the chip area recess 42. And three-dimensional wiring 5
0 (50a, 50b). In addition, a plurality of these three-dimensional plating wirings 50 are arranged on each of two or four sides of the package housing 43, for example, five each, and all of them are recessed from the lower surface (the upper surface in the figure) of the package housing 43 to the chip area recess. It is provided over the 42 bonding area to form a BGA type wiring. At this time, as a method for forming the three-dimensional plated wiring 50, for example, a three-dimensional three-dimensional mask method (3D mask method) is employed. The details of the 3D mask method are described in Japanese Patent Application No. 10-338329 previously submitted by the present applicant.

【００２０】次に、図１１のに示すように連続した透
明プラスチック製パッケージ筐体４３に施した各立体メ
ッキ配線５０の外部接続部５１（５１ａ、５１ｂ）にハ
ンダボール５２（５２ａ、５２ｂ）をそれぞれ溶融接合
する。そして、受光又は発光半導体素子として例えばＣ
ＣＤＩＣチップ５３を用意する。次に、に示すように
ＣＣＤＩＣチップ５３上にその電極と接続するスタッド
バンプ５４（５４ａ、５４ｂ）をそれぞれ形成する。Next, as shown in FIG. 11, the solder balls 52 (52a, 52b) are attached to the external connection portions 51 (51a, 51b) of the three-dimensional plated wiring 50 applied to the continuous transparent plastic package housing 43. Each is melt-bonded. And, as a light receiving or light emitting semiconductor element, for example, C
A CDIC chip 53 is prepared. Next, stud bumps 54 (54a, 54b) connected to the electrodes are formed on the CCDIC chip 53 as shown in FIG.

【００２１】次に、図１２のに示すように各立体メッ
キ配線５０の内部接続部５５（５５ａ、５５ｂ）にバン
プ例えばＡｇ−Ｐｂバンプ５６（５６ａ、５６ｂ）をそ
れぞれ形成し、その各バンプ５６上に封止用樹脂をそれ
ぞれ塗布する。すると、に示すように透明プラスチッ
ク製パッケージ筐体４３の各Ａｇ−Ｐｂバンプ５６にＣ
ＣＤＩＣチップ５３の対応するスタッドバンプ５４をそ
れぞれ接続するスタッドバンプボンディング（ＳＢＢ）
接続により、チップエリア用凹所４２のチップエリアに
ＣＣＤＩＣチップ５３を搭載し、それ等のスタッドバン
プ５４、バンプ５６とその各接続箇所付近をそれぞれ樹
脂封止できる。なお、チップエリア用凹所４２の内部に
全てプラスチックを充填し、ＣＣＤＩＣチップ５３等の
全体を樹脂封止してもよい。又、接続用導電体としてス
タッドバンプ５４等を用いたスタッドバンプボンディン
グ接続に代えてワイヤー接続をすることもできる。Next, as shown in FIG. 12, bumps, for example, Ag-Pb bumps 56 (56a, 56b) are formed on the internal connection portions 55 (55a, 55b) of the three-dimensional plated wirings 50, respectively. A sealing resin is applied on each of them. Then, as shown in FIG. 7, C is applied to each Ag-Pb bump 56 of the transparent plastic package housing 43.
Stud bump bonding (SBB) for connecting the corresponding stud bumps 54 of the CDIC chip 53 respectively
By the connection, the CCDIC chip 53 is mounted in the chip area of the chip area recess 42, and the stud bumps 54 and the bumps 56 and the vicinity of each connection portion can be resin-sealed. Note that the entirety of the chip area recess 42 may be filled with plastic, and the entire CCD IC chip 53 and the like may be sealed with resin. Also, wire connection can be used instead of stud bump bonding connection using the stud bump 54 or the like as the connection conductor.

【００２２】次に、図１３のに示すように再度上下を
反対にして元に戻し、やはりウォータージェット３０又
はダイシングソー３１若しくは切断金型を用いて個片に
カットする。すると、大略四角錐台状の透明プラスチッ
ク製パッケージ筐体４３を用いたＢＧＡ型透明プラスチ
ック半導体パッケージ４４が完成する。なお、チップエ
リア用凹所４２の空間形状も四角錐台状である。このよ
うにして、透明プラスチック製パッケージ筐体４３を用
いたＢＧＡ型透明プラスチック半導体パッケージ４４を
製作すると、ＢＧＡ型配線基板１１、４０を用いる場合
より一層信頼性が向上し、小型化、軽量化が可能で製品
も安価になる。Next, as shown in FIG. 13, the upper and lower parts are again turned upside down, and are again cut into individual pieces using a water jet 30, a dicing saw 31, or a cutting die. Then, a BGA-type transparent plastic semiconductor package 44 using the substantially rectangular truncated pyramid-shaped transparent plastic package case 43 is completed. The space shape of the chip area recess 42 is also a truncated quadrangular pyramid. In this manner, when the BGA type transparent plastic semiconductor package 44 using the transparent plastic package case 43 is manufactured, the reliability is further improved as compared with the case where the BGA type wiring boards 11 and 40 are used, and the size and weight are reduced. Possible and cheaper product.

【００２３】又、上記実施の形態では平らな上面を有す
る透明プラスチック製パッケージ筐体４３を用いたＢＧ
Ａ型透明プラスチック半導体パッケージ４４について説
明したが、その透明プラスチック製パッケージ筐体をレ
ンズ一体型にしてＢＧＡ型透明プラスチック半導体パッ
ケージを製作することもできる。その際には、透明プラ
スチック製パッケージ筐体の製造工程において、その上
面中央部にレンズとなる突部等を設け、その表面を非球
面レンズ形状等に形成する。すると、モールド成形によ
り透明プラスチック製パッケージ筐体にレンズを強固に
結合して、やはり半導体パッケージをレンズ付きにする
ことができる。In the above embodiment, the BG using the transparent plastic package housing 43 having a flat upper surface is used.
Although the A-type transparent plastic semiconductor package 44 has been described, a BGA-type transparent plastic semiconductor package may be manufactured by integrating the transparent plastic package housing with a lens. In that case, in the manufacturing process of the transparent plastic package case, a projection or the like serving as a lens is provided at the center of the upper surface, and the surface is formed into an aspheric lens shape or the like. Then, the lens is firmly connected to the transparent plastic package housing by molding, so that the semiconductor package can be provided with the lens.

【００２４】又、上記実施の形態では片面の中央部にチ
ップエリア用凹所４２を設けた透明プラスチック製パッ
ケージ筐体４３を用い、そのパッケージ筐体４３に施し
た各立体メッキ配線５０の外部接続部５１にハンダボー
ル５２をそれぞれ溶融接合したＢＧＡ型透明プラスチッ
ク半導体パッケージ４４について説明したが、図１４に
示すように透明プラスチック製パッケージ筐体５７に施
した各立体メッキ配線５８の外部接続部５９に外部端子
としてメッキ被覆を施した円錐台状突起６０をそれぞれ
設けると、ハンダボールを不要とすることができる。こ
れ等の外部端子用突起６０はパッケージ筐体５７の成形
時に同時に形成し、その各突起６０に対するメッキ被覆
は各立体メッキ配線５８の形成時に同時に施す。なお、
６１はチップエリア用凹所である。Further, in the above embodiment, a transparent plastic package housing 43 having a chip area recess 42 provided at the center of one surface is used, and external connection of each three-dimensional plating wiring 50 provided on the package housing 43 is performed. The BGA type transparent plastic semiconductor package 44 in which the solder ball 52 is melt-bonded to the portion 51 has been described. However, as shown in FIG. 14, the external connection portion 59 of each three-dimensional plating wiring 58 provided on the transparent plastic package case 57 is provided. If the truncated cone-shaped projections 60 coated with plating are provided as external terminals, solder balls can be eliminated. These external terminal projections 60 are formed at the same time when the package casing 57 is formed, and the plating for each of the projections 60 is applied simultaneously when the three-dimensional plated wirings 58 are formed. In addition,
61 is a recess for the chip area.

【００２５】[0025]

【発明の効果】以上説明した本発明によれば、請求項１
記載の発明ではＢＧＡ型配線基板の片面に設置した受光
又は発光半導体素子及び各接続用導電体とその各接続用
導電体の接続箇所付近をモールド成形により透明プラス
チックで樹脂封止して、そのＢＧＡ型配線基板の片面に
透明プラスチック製パッケージ部を設けることにより、
透明板を不要にできる。それ故、透明板の製作や取り付
け工程等が当然不要であり、取付後の脱落も発生しな
い。According to the present invention described above, claim 1
In the described invention, a light-receiving or light-emitting semiconductor element installed on one side of a BGA type wiring board and each connection conductor and the vicinity of the connection portion of each connection conductor are resin-sealed with a transparent plastic by molding, and the BGA By providing a transparent plastic package part on one side of the wiring board,
A transparent plate can be eliminated. Therefore, the process of manufacturing the transparent plate and the mounting process are naturally unnecessary, and no dropout occurs after the mounting.

【００２６】又、透明板を使用しないと、ＢＧＡ型配線
基板の片面に設置した受光又は発光半導体素子の各電極
とＢＧＡ型配線の対応する内部接続部とを導電体を用い
てそれぞれ接続した後に、受光又は発光半導体素子を樹
脂封止してパッケージ部を一体成形するという工程を踏
むことができるため、当然樹脂フラッシュは発生せず除
去工程も不要となり、ＢＧＡ型配線の内部接続部に露出
不良の問題が発生することもない。又、透明板を使用せ
ず、透明プラスチック製パッケージ部を一体成形すると
接続用導電体が酸化し難くなる等、信頼性が向上する。
又、透明板を使用せず、ＢＧＡ型配線基板の片面のみに
透明プラスチック製パッケージ部を設けると、製品の小
型化、軽量化が可能となり、製品も安価になる。If the transparent plate is not used, each electrode of the light-receiving or light-emitting semiconductor element provided on one side of the BGA-type wiring board is connected to the corresponding internal connection portion of the BGA-type wiring using a conductor. In addition, the process of integrally molding the package portion by resin-sealing the light-receiving or light-emitting semiconductor element can be performed, so that the resin flash does not occur and the removal process is not necessary, and the internal connection portion of the BGA type wiring has poor exposure. The problem does not occur. In addition, if a transparent plastic package is integrally formed without using a transparent plate, reliability is improved, for example, the connecting conductor is less likely to be oxidized.
If a transparent plastic package is provided only on one side of the BGA type wiring board without using a transparent plate, the product can be reduced in size and weight, and the product can be inexpensive.

【００２７】又、請求項２記載の発明では透明プラスチ
ック製パッケージ部をレンズ一体型に成形することによ
り、その透明プラスチック製パッケージ部にレンズを強
固に結合して、ＢＧＡ型透明プラスチック半導体パッケ
ージを簡単にレンズ付きにすることができる。そして、
レンズ付きの透明プラスチック半導体パッケージを小型
化、軽量化し、安価にすることができる。According to the second aspect of the present invention, the transparent plastic package is molded into a lens-integrated type, so that the lens is firmly connected to the transparent plastic package, thereby simplifying the BGA type transparent plastic semiconductor package. Can be fitted with a lens. And
A transparent plastic semiconductor package with a lens can be reduced in size, weight, and cost.

【００２８】又、請求項３記載の発明では片面にチップ
エリア用凹所を設けた透明プラスチック製パッケージ筐
体を成形し、そのチップエリア用凹所付近の表面所定箇
所に立体的にメッキ配線をそれぞれ施してＢＧＡ型配線
を設けることにより、透明板をやはり不要にできる。そ
れ故、透明板使用による問題を解消できるばかりでな
く、ＢＧＡ型配線基板を用いる場合より一層信頼性を向
上させ、小型化、軽量化し、製品を安価にすることがで
きる。According to the third aspect of the present invention, a transparent plastic package housing having a chip area recess formed on one surface is formed, and a plating wiring is three-dimensionally formed on a predetermined surface near the chip area recess. By providing the BGA-type wirings respectively, the transparent plate can be made unnecessary. Therefore, not only can the problem caused by the use of the transparent plate be solved, but also the reliability can be further improved, the size and weight can be reduced, and the cost of the product can be reduced, as compared with the case where the BGA type wiring board is used.

【００２９】又、請求項４記載の発明では透明プラスチ
ック製パッケージ筐体をレンズ一体型に成形することに
より、そのパッケージ筐体にレンズを強固に結合してや
はりＢＧＡ型透明プラスチック半導体パッケージを簡単
にレンズ付きにすることができる。そして、ＢＧＡ型配
線基板を用いる場合より一層信頼性を向上させ、小型
化、軽量化し、安価にすることができる。According to the fourth aspect of the present invention, the transparent plastic package housing is molded into a lens-integrated type, so that the lens is firmly connected to the package housing, so that the BGA transparent plastic semiconductor package can be easily formed. Can be fitted with a lens. Further, the reliability can be further improved, the size, the weight, and the cost can be reduced as compared with the case where the BGA type wiring board is used.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明を適用したＢＧＡ型配線基板使用による
ＢＧＡ型透明プラスチック半導体パッケージの縦断面図
である。FIG. 1 is a longitudinal sectional view of a BGA type transparent plastic semiconductor package using a BGA type wiring board to which the present invention is applied.

【図２】同ＢＧＡ型透明プラスチック半導体パッケージ
の製造工程におけるダイボンディング＆ワイヤーボンデ
ィング工程と透明プラスチック製パッケージ部モールデ
ィング工程を示す縦断面図である。FIG. 2 is a longitudinal sectional view showing a die bonding & wire bonding step and a transparent plastic package part molding step in the manufacturing process of the BGA type transparent plastic semiconductor package.

【図３】同ＢＧＡ型透明プラスチック半導体パッケージ
の製造工程における透明プラスチック製パッケージ部上
面研磨工程と外部端子取付工程を示す縦断面図である。FIG. 3 is a vertical sectional view showing a transparent plastic package upper surface polishing step and an external terminal attaching step in a manufacturing step of the BGA type transparent plastic semiconductor package.

【図４】同ＢＧＡ型透明プラスチック半導体パッケージ
の製造工程における個片カット工程を示す縦断面図であ
る。FIG. 4 is a longitudinal sectional view showing an individual cutting step in the manufacturing process of the BGA type transparent plastic semiconductor package.

【図５】同ＢＧＡ型透明プラスチック半導体パッケージ
の透明プラスチック製パッケージ部透視状態を示す上側
から見た斜視図である。FIG. 5 is a perspective view of the transparent plastic package portion of the BGA type transparent plastic semiconductor package as seen from above, in a transparent state;

【図６】同ＢＧＡ型透明プラスチック半導体パッケージ
の外部端子配置状態を示す下側から見た斜視図である。FIG. 6 is a perspective view showing the external terminal arrangement state of the BGA type transparent plastic semiconductor package as viewed from below.

【図７】本発明を適用したＢＧＡ型配線基板使用、レン
ズ付き透明プラスチック製パッケージ部有りのＢＧＡ型
透明プラスチック半導体パッケージの斜視図である。FIG. 7 is a perspective view of a BGA type transparent plastic semiconductor package using a BGA type wiring board to which the present invention is applied and having a transparent plastic package part with a lens.

【図８】同ＢＧＡ型透明プラスチック半導体パッケージ
のレンズ付き透明プラスチック製パッケージ部モールデ
ィング工程を示す縦断面図である。FIG. 8 is a longitudinal sectional view showing a molding process of a transparent plastic package part with a lens of the BGA type transparent plastic semiconductor package.

【図９】本発明を適用した透明プラスチック製パッケー
ジ筐体使用によるＢＧＡ型透明プラスチック半導体パッ
ケージの縦断面図である。FIG. 9 is a longitudinal sectional view of a BGA type transparent plastic semiconductor package using a transparent plastic package housing to which the present invention is applied.

【図１０】同ＢＧＡ型透明プラスチック半導体パッケー
ジの製造工程における透明プラスチック製パッケージ筐
体モールディング工程と立体メッキ配線工程を示す縦断
面図である。FIG. 10 is a longitudinal sectional view showing a transparent plastic package housing molding step and a three-dimensional plating wiring step in a manufacturing step of the BGA type transparent plastic semiconductor package.

【図１１】同ＢＧＡ型透明プラスチック半導体パッケー
ジの製造工程における外部端子取付工程とＣＣＤＩＣチ
ップ上にスタッドバンプを形成する工程を示す縦断面図
である。FIG. 11 is a longitudinal sectional view showing a step of attaching external terminals and a step of forming stud bumps on a CCDIC chip in a step of manufacturing the BGA type transparent plastic semiconductor package.

【図１２】同ＢＧＡ型透明プラスチック半導体パッケー
ジの製造工程における透明プラスチック製パッケージ筐
体に施した立体メッキ配線の内部接続部に対するバンプ
形成及び封止樹脂塗布工程とスタッドバンプボンディン
グ（ＳＢＢ）接続によるＣＣＤＩＣチップ搭載工程を示
す縦断面図である。FIG. 12 is a step of forming a bump on an internal connection portion of three-dimensional plated wiring applied to a transparent plastic package housing in a manufacturing process of the BGA type transparent plastic semiconductor package, applying a sealing resin, and connecting the stud bump bonding (SBB) CCDIC. It is a longitudinal cross-sectional view which shows a chip mounting process.

【図１３】同ＢＧＡ型透明プラスチック半導体パッケー
ジの製造工程における個片カット工程を示す縦断面図で
ある。FIG. 13 is a vertical sectional view showing an individual cutting step in the manufacturing process of the BGA type transparent plastic semiconductor package.

【図１４】本発明適用の透明プラスチック半導体パッケ
ージに使用する他の透明プラスチック製パッケージ筐体
を示す斜視図である。FIG. 14 is a perspective view showing another transparent plastic package housing used for the transparent plastic semiconductor package of the present invention.

【図１５】従来のリードフレーム使用による中空半導体
パッケージの縦断面図である。FIG. 15 is a longitudinal sectional view of a conventional hollow semiconductor package using a lead frame.

【符号の説明】[Explanation of symbols]

１０、３３、４４…透明プラスチック半導体パッケージ
１１、４０…ＢＧＡ型配線基板 １２、５３…ＣＣＤ
ＩＣチップ １３…絶縁基材 １４…配線パターン １
５…チップエリア １６、５５…内部接続部 １７、５
１、５９…外部接続部 １９…ワイヤー ２１、３５、
４５…モールド金型 ２２、３７、４６…キャビテイ
２３、３６、４７…上金型 ２４、４１…配置用凹所
２５、３９、４９…下金型 ２６…パーティングライン
面 ２７、３２…透明プラスチック製パッケージ部 ２
９、５２…ハンダボール ３４…レンズ ３８…突部成
形用凹所 ４２、６１…チップエリア用凹所 ４３、５
７…透明プラスチック製パッケージ筐体 ４８…成形用
突部 ５０、５８…立体メッキ配線 ５４…スタッドバ
ンプ ５６…バンプ ６０…外部端子用突起10, 33, 44: transparent plastic semiconductor package 11, 40: BGA type wiring board 12, 53: CCD
IC chip 13: insulating base material 14: wiring pattern 1
5: Chip area 16, 55: Internal connection part 17, 5
1, 59 ... external connection part 19 ... wire 21, 35,
45 ... Mold mold 22,37,46 ... Cavity
23, 36, 47 ... Upper die 24, 41 ... Arrangement recess
25, 39, 49: Lower mold 26: Parting line surface 27, 32: Transparent plastic package 2
9, 52: solder ball 34: lens 38: recess for forming a projection 42, 61: recess for chip area 43, 5
7 ... Transparent plastic package housing 48 ... Molding projection 50,58 ... Three-dimensional plating wiring 54 ... Stud bump 56 ... Bump 60 ... Projection for external terminal

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M109 AA01 BA03 CA21 DA07 EC11 GA01 5F041 AA42 AA43 AA47 CB22 CB31 DA07 DA25 DA34 DA43 DA55 DA57 DA74 DA75 DA81 DB08 5F061 AA01 BA03 CA21 DA06 FA01 5F088 BA01 BA10 BA15 BA18 BB03 EA06 JA03 JA06 JA09 JA10 JA12  ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M109 AA01 BA03 CA21 DA07 EC11 GA01 5F041 AA42 AA43 AA47 CB22 CB31 DA07 DA25 DA34 DA43 DA55 DA57 DA74 DA75 DA81 DB08 5F061 AA01 BA03 CA21 DA06 FA01 5F088 BA01 JA03 JA03 JA03 JA09 JA10 JA12

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 ＢＧＡ型配線基板の片面に受光又は発光
半導体素子を搭載し、その受光又は発光半導体素子の各
電極とＢＧＡ型配線の対応する内部接続部とを導電体を
用いてそれぞれ接続し、モールド成形によりその受光又
は発光半導体素子及び各接続用導電体と各接続用導電体
の接続箇所付近を透明プラスチックで樹脂封止してＢＧ
Ａ型配線基板の片面に透明プラスチック製パッケージ部
を設けることを特徴とするＢＧＡ型透明プラスチック半
導体パッケージ。1. A light-receiving or light-emitting semiconductor element is mounted on one surface of a BGA-type wiring board, and each electrode of the light-receiving or light-emitting semiconductor element is connected to a corresponding internal connection portion of the BGA-type wiring using a conductor. By molding, the light receiving or light emitting semiconductor element and each connection conductor and the vicinity of the connection portion of each connection conductor are resin-encapsulated with a transparent plastic to form a BG.
A BGA type transparent plastic semiconductor package, wherein a transparent plastic package portion is provided on one surface of an A type wiring board. 【請求項２】 透明プラスチック製パッケージ部をレン
ズ一体型に成形することを特徴とする請求項１記載のＢ
ＧＡ型透明プラスチック半導体パッケージ。2. The lens according to claim 1, wherein the transparent plastic package is molded into a lens-integrated type.
GA type transparent plastic semiconductor package. 【請求項３】 片面にチップエリア用凹所を設けた透明
プラスチック製パッケージ筐体を成形し、そのチップエ
リア用凹所付近の表面所定箇所に立体的にメッキ配線を
それぞれ施してＢＧＡ型配線を設け、そのチップエリア
に受光又は発光半導体素子を搭載し、その受光又は発光
半導体素子の各電極とＢＧＡ型配線の対応する内部接続
部とを導電体を用いてそれぞれ接続し、その各接続用導
電体と各接続用導電体の接続箇所付近を少なくとも樹脂
封止することを特徴とするＢＧＡ型透明プラスチック半
導体パッケージ。3. A package made of a transparent plastic package having a recess for a chip area on one side, and three-dimensionally plated wiring on a predetermined surface near the recess for a chip area to form a BGA type wiring. A light-receiving or light-emitting semiconductor element is mounted in the chip area, and each electrode of the light-receiving or light-emitting semiconductor element is connected to a corresponding internal connection portion of the BGA type wiring using a conductor. A BGA-type transparent plastic semiconductor package, characterized in that at least the vicinity of a connection point between a body and each connection conductor is sealed with a resin. 【請求項４】 透明プラスチック製パッケージ筐体をレ
ンズ一体型に成形することを特徴とする請求項３記載の
ＢＧＡ型透明プラスチック半導体パッケージ。4. The BGA type transparent plastic semiconductor package according to claim 3, wherein the transparent plastic package housing is molded into a lens integrated type.
JP1707899A 1999-01-26 1999-01-26 Bga type transparent plastic semiconductor package Pending JP2000216413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1707899A JP2000216413A (en) 1999-01-26 1999-01-26 Bga type transparent plastic semiconductor package

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Publication Number Publication Date
JP2000216413A true JP2000216413A (en) 2000-08-04

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ID=11933954

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JP2010161130A (en) * 2009-01-07 2010-07-22 Murata Mfg Co Ltd Photosensor module
JP2017028328A (en) * 2009-09-17 2017-02-02 コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． Method for manufacturing led module
JP2011141348A (en) * 2010-01-06 2011-07-21 Panasonic Corp Imaging device unit, lens barrel
JP2015056654A (en) * 2013-09-10 2015-03-23 菱生精密工業股▲分▼有限公司 Semiconductor device and method of manufacturing the same
JP2020025034A (en) * 2018-08-08 2020-02-13 ローム株式会社 Led package and led display device
CN110828641A (en) * 2018-08-08 2020-02-21 罗姆股份有限公司 LED assembly and LED display device

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