JP2000216308A - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JP2000216308A JP2000216308A JP11017113A JP1711399A JP2000216308A JP 2000216308 A JP2000216308 A JP 2000216308A JP 11017113 A JP11017113 A JP 11017113A JP 1711399 A JP1711399 A JP 1711399A JP 2000216308 A JP2000216308 A JP 2000216308A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- base plate
- heat
- radiating base
- power semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，電力用半導体装置
を搭載した耐熱性絶縁板に接合される放熱ベース板の逆
ソリを防止する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing a heat-radiating base plate bonded to a heat-resistant insulating plate on which a power semiconductor device is mounted from being reversely warped.
【０００２】[0002]
【従来の技術】図３を用いて，従来の電力用半導体装置
の要部構造を説明する。図３（ａ）に示すように，ダイ
オードやサイリスタなどの電力用半導体チップ６が，金
属酸化物などを厚さ約０．６ｍｍに焼成したセラミック
板等の熱伝導が良い耐熱性絶縁板４に，半田１０によっ
て接合されたものが，厚み約２ｍｍの銅の放熱ベース板
２に半田８によって接合される構成となっている。耐熱
性絶縁板４の構造は，例えば，厚さ約０．６ｍｍの窒化
アルミやアルミナなどのセラミック板４ａに，その周辺
部を除いた両面に，０．１〜０．３ｍｍの厚さのメタラ
イズ層４ｂ，４ｃが設けられている。このメタライズ層
を介して，半田などによって半導体チップや銅の放熱ベ
ース板が接合できるのであるが，セラミック板等の耐熱
性絶縁板と，銅などの放熱ベース板とを半田付けによっ
て接合したとき，それらの熱膨張係数の差が大きいほ
ど，図（ｃ）に示すように常温まで冷却している過程で
縮み寸法の差が大きい為，ソリが発生していた。2. Description of the Related Art The structure of a main part of a conventional power semiconductor device will be described with reference to FIG. As shown in FIG. 3A, a power semiconductor chip 6 such as a diode or a thyristor is formed into a heat-resistant insulating plate 4 having good heat conduction such as a ceramic plate obtained by firing a metal oxide or the like to a thickness of about 0.6 mm. , Solder 10 is joined to the copper radiation base plate 2 having a thickness of about 2 mm by the solder 8. The structure of the heat-resistant insulating plate 4 is, for example, a metal plate having a thickness of 0.1 to 0.3 mm formed on a ceramic plate 4a of about 0.6 mm in thickness such as aluminum nitride or alumina, excluding a peripheral portion thereof. Layers 4b and 4c are provided. Through this metallization layer, a semiconductor chip or a heat dissipation base plate of copper can be joined by soldering. When a heat-resistant insulating plate such as a ceramic plate and a heat dissipation base plate such as copper are joined by soldering, As the difference between the thermal expansion coefficients is larger, the difference in the shrinkage dimension during the process of cooling to room temperature is larger as shown in FIG.
【０００３】図３（ｂ）は，高温状態，例えば高温半田
の凝固点３１０℃以上での要部の形状を示しており，セ
ラミック板などの耐熱性絶縁板４と，放熱ベース板２，
との接合部で，半田が凝固する。この形状では，耐熱性
絶縁板４，放熱ベース板２は共に熱膨張している。この
接合部ＡＢ間の長さＬ１が，例えば３１０℃において５
０ｍｍであったものが，自然冷却後常温に戻ったとき，
収縮しようとする放熱ベース材２のＡＢ間に対応したＣ
Ｄ間の長さＬ２は，約４９．７７ｍｍになろうとする。
ここで，線膨張係数は，銅では１６ラ１０-6／ーＫ，セラ
ミックでは２ラ１０-6／ーＫである。FIG. 3B shows the shape of a main part in a high temperature state, for example, at a solidification point of a high temperature solder of 310 ° C. or higher.
The solder solidifies at the joint with the solder. In this shape, both the heat-resistant insulating plate 4 and the heat radiation base plate 2 are thermally expanded. The length L1 between the joints AB is, for example, 5 at 310 ° C.
When it returned to room temperature after natural cooling,
C corresponding to the distance between AB of the heat-dissipating base material 2 to be contracted
The length L2 between D tends to be about 49.77 mm.
Here, the linear expansion coefficient is 16 × 10 −6 / −K for copper and 2 × 10 −6 / −K for ceramic.
【０００４】接合された部分ＡＢ間の長さＬ１は，３１
０℃では，５０ｍｍ，２０℃でセラミックスでは４９．
９７ｍｍであり，その縮み寸法は，０．０３ｍｍである
が，銅ではＡＢ間に対応したＣＤ間の長さは，前記のよ
うに３１０℃と２０℃とでは，その縮み寸法が０．２３
ｍｍであり，上面と下面との差０．２ｍｍが生じる。The length L1 between the joined portions AB is 31
50. At 0.degree. C., 50.degree.
97 mm, and the shrinkage dimension is 0.03 mm. In copper, the length between the CDs corresponding to the area between the ABs is, as described above, at 310 ° C. and 20 ° C., the shrinkage dimension is 0.23 mm.
mm, and a difference of 0.2 mm between the upper surface and the lower surface occurs.
【０００５】[0005]
【発明が解決しようとする課題】このため，サイズの大
きい電力用半導体装置では，図３（ｃ）のように，放熱
ベース板の湾曲が発生する。この湾曲は，フィンへの取
付密着度を悪くし，電力用半導体装置とフィンとの間に
熱伝導による放熱を阻害する空気層を生じることにな
り，逆ソリと称して極力避けなければならないものであ
る。本発明は，従来の半導体チップを搭載する耐熱性絶
縁板と，放熱ベース板との熱膨張係数の違いによって生
じる放熱ベース板の逆ソリを防止するのが本発明の課題
である。Therefore, in a power semiconductor device having a large size, the heat radiation base plate is curved as shown in FIG. 3 (c). This curvature deteriorates the degree of adhesion to the fins, and creates an air layer between the power semiconductor device and the fins that hinders heat dissipation due to heat conduction. It is. SUMMARY OF THE INVENTION It is an object of the present invention to prevent reverse warpage of a heat-dissipating base plate caused by a difference in thermal expansion coefficient between a conventional heat-resistant insulating plate on which a semiconductor chip is mounted and a heat-dissipating base plate.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するた
め，請求項１記載の発明は，電力用半導体チップを搭載
した耐熱性絶縁板と，放熱ベースとを接合するため，次
のような手段を用いる。すなわち，耐熱性絶縁板と放熱
ベース板との間に，耐熱性絶縁板のメタライズ層の厚み
よりも厚く，放熱ベース板より薄い銅等の金属ペレット
を熱膨張緩衝剤として，半田付けなどによって接合され
る。接合される熱膨張緩衝材は，製造工程中の半田凝固
点温度と常温との温度差によって生じる湾曲方向に働く
力を吸収する役割を果たしている。Means for Solving the Problems To solve the above-mentioned problems, the invention according to claim 1 provides the following means for joining a heat-resistant insulating plate on which a power semiconductor chip is mounted and a heat radiation base. Is used. That is, a metal pellet, such as copper, which is thicker than the metallized layer of the heat-resistant insulating plate and thinner than the heat-radiating base plate, is joined between the heat-resistant insulating plate and the heat-radiating base plate by soldering or the like as a thermal expansion buffer. Is done. The thermal expansion buffer material to be joined plays a role of absorbing a force acting in a bending direction caused by a temperature difference between a solder solidification point temperature and a normal temperature in a manufacturing process.
【０００７】請求項２記載の発明は，電力用半導体チッ
プを搭載したセラミック板の裏面に，セラミックス板の
厚みと略同等の厚みのメタライズ層を設けて，このメタ
ライズ層と放熱ベース板とが半田付けなどによって接合
される。セラミック板の厚さと略同等のメタライズ層
と，接合に使用される半田の層が熱膨張緩衝の役割を果
たしている。According to a second aspect of the present invention, a metallized layer having a thickness substantially equal to the thickness of the ceramic plate is provided on the back surface of the ceramic plate on which the power semiconductor chip is mounted, and the metallized layer and the heat radiation base plate are soldered. It is joined by attaching. A metallized layer having a thickness substantially equal to the thickness of the ceramic plate and a solder layer used for bonding serve as a buffer for thermal expansion.
【０００８】[0008]
【発明の実施の形態】図１は請求項１の発明の実施形態
である。放熱ベース板２は，例えば厚さ２ｍｍ程度の銅
板である。４は耐熱性絶縁板で，中央には約０．６ｍｍ
の厚さのセラミックス板４ａが設けられ，このセラミッ
ク板４ａの両面には，周辺部を除いて銅などによって
０．１〜０．３ｍｍの厚さにメタライズ層４ｂ，４ｃが
設けられている。メタライズ層４ｂには，電力用半導体
チップ６が半田１０などによって接合され，メタライズ
層４ｃは，セラミック板４ａのメタライズ層４ｃの厚さ
よりも厚く，放熱ベース板２より薄い厚さの銅などの金
属ペレット１２を介して，放熱ベース板２に半田１４，
１６などによって接合されている。FIG. 1 shows an embodiment of the first aspect of the present invention. The heat radiation base plate 2 is, for example, a copper plate having a thickness of about 2 mm. 4 is a heat-resistant insulating plate, about 0.6 mm in the center.
Is provided on both sides of the ceramic plate 4a. Metallized layers 4b and 4c are provided on both surfaces of the ceramic plate 4a with a thickness of 0.1 to 0.3 mm by copper or the like except for peripheral portions. The power semiconductor chip 6 is joined to the metallized layer 4b by solder 10 or the like, and the metallized layer 4c is made of a metal such as copper having a thickness larger than the thickness of the metallized layer 4c of the ceramic plate 4a and smaller than the thickness of the heat dissipation base plate 2. Solder 14 is attached to heat dissipation base plate 2 through pellet 12
16 and the like.
【０００９】図１に示した金属ペレット１２とセラミッ
クス板４ａの熱膨張係数の比は，（１６．５ラ１０-6）
／（２ラ１０-6）であり，約８倍である。このため，製
造工程中の半田付けで，熱膨張した状態から自然冷却中
に，金属ペレット１２とセラミック板４ａは収縮し，半
田凝固点温度を通過し，金属ペレット１２とセラミック
板４ａは接合する。温度の低下とともに，金属ペレット
１２もセラミック板４ａも収縮するが，その縮み寸法
（寸法の変化分）の大きさは，セラミック板４ａは金属
ペレット１２よりも小さいため，以下に述べるような状
態が見られる。The ratio of the coefficient of thermal expansion between the metal pellet 12 and the ceramic plate 4a shown in FIG. 1 is (16.5 × 10 −6 ).
/ (2 × 10 −6 ), which is about 8 times. For this reason, during the soldering during the manufacturing process, the metal pellet 12 and the ceramic plate 4a shrink during natural cooling from a thermally expanded state, pass through the temperature of the solder solidification point, and the metal pellet 12 and the ceramic plate 4a are joined. As the temperature decreases, both the metal pellet 12 and the ceramic plate 4a shrink. However, since the size of the shrinkage dimension (a change in the size) of the ceramic plate 4a is smaller than that of the metal pellet 12, the following state may occur. Can be seen.
【００１０】金属ペレット１２の上面（半田１６に接し
た面）は，金属ペレット１２の下面（半田１４に接した
面）に比較すると，縮み寸法が小さいセラミック板４ａ
が固着している影響を受けて縮み寸法が小さく，下面は
上面より寸法の変化が大きい。高温から常温へと近づく
につれて，上面が凸に，下面が凹に変形が生じる。上面
の凸の変形した部分に半田１６が，下面の凹に変形した
部分には半田１４がそれぞれ変形し，温度変化により生
じる金属ペレット１２の形状変化分を吸収し，熱膨張緩
衝作用をもつ。このようにして，金属ペレット１２と半
田１４，１６に助けられて，セラミック板４と放熱ベー
ス板２は，平面度が保持される。The upper surface of the metal pellet 12 (the surface in contact with the solder 16) is smaller than the lower surface of the metal pellet 12 (the surface in contact with the solder 14).
The size of the shrinkage is small due to the effect of sticking, and the change in the size of the lower surface is larger than that of the upper surface. As the temperature approaches from normal to normal, the upper surface becomes convex and the lower surface becomes concave. The solder 16 is deformed on the convexly deformed portion of the upper surface and the solder 14 is deformed on the concavely deformed portion of the lower surface, and absorbs the shape change of the metal pellet 12 caused by the temperature change, and has a thermal expansion buffering action. In this manner, the flatness of the ceramic plate 4 and the heat radiation base plate 2 is maintained by the metal pellets 12 and the solders 14 and 16.
【００１１】図２は，請求項２記載の発明の実施の形態
である。５は耐熱性絶縁板で，中央のセラミック板５ａ
の両面にメタライズ層５ｂ，５ｃが設けられている。そ
して，半導体チップ６を接合するセラミック板５ａの上
面メタライズ層５ｂは，４ｂと略同等の厚さである。ま
た，下面メタライズ層５ｃはセラミック板５ａの厚さと
略同等の厚さに設けられている。FIG. 2 shows an embodiment of the present invention. Reference numeral 5 denotes a heat-resistant insulating plate, and a central ceramic plate 5a.
Are provided with metallized layers 5b and 5c on both sides. The upper metallized layer 5b of the ceramic plate 5a to which the semiconductor chip 6 is bonded has a thickness substantially equal to 4b. The lower metallization layer 5c is provided with a thickness substantially equal to the thickness of the ceramic plate 5a.
【００１２】作用は，前記の図１で説明した場合と類似
の形状変化分を，半田８の変化によって吸収するのであ
る。従来例との相違点は，下面メタライズ層５ｃが，従
来例の下面メタライズ層４ｃの０．１〜０．３ｍｍ厚さ
に対して，セラミック板の厚さ０．６ｍｍと略同等であ
り，格段に湾曲変形量が大きくなっている。このこと
は，金属ペレット１２と類似の作用をもつが，金属ペレ
ット１２よりも上面の拘束力が大きいために，下面の凹
変形への変形量は金属ペレット１２の場合より小さい。
熱膨張，収縮による下面メタライズ層５ｃの下面凹変形
が生じるのに必要な体積を確保するために，下面メタラ
イズ層５ｃの厚みを増加させている。下面凹変化に対し
て，半田８が変形して，放熱ベース板２の湾曲を防止す
る作用をする。The effect is to absorb a change in shape similar to that described with reference to FIG. The difference from the conventional example is that the lower surface metallized layer 5c is substantially equivalent to the thickness of the ceramic plate of 0.6 mm with respect to the thickness of the lower surface metallized layer 4c of the conventional example of 0.1 to 0.3 mm. The amount of bending deformation is large. This has an effect similar to that of the metal pellet 12, but since the upper surface has a larger binding force than the metal pellet 12, the amount of deformation of the lower surface to concave deformation is smaller than that of the metal pellet 12.
The thickness of the lower metallized layer 5c is increased in order to secure a volume necessary for the lower metallized layer 5c to be concavely deformed by thermal expansion and contraction. The solder 8 is deformed in response to the change of the lower surface concave portion, and serves to prevent the heat radiation base plate 2 from bending.
【００１３】[0013]
【発明の効果】以上の説明のように，本発明は，セラミ
ックのような熱膨張係数の小さい絶縁板と，金属の放熱
ベース板とが接合されたときに，放熱ベース板の逆そり
を防止して，放熱効果を高め，同時に放熱ベース板の厚
さを増やす必要がないので，省資源を指向した装置を具
体化することが可能である。As described above, according to the present invention, when an insulating plate having a small coefficient of thermal expansion such as ceramic is joined to a metal radiating base plate, the warping of the radiating base plate is prevented. As a result, it is not necessary to increase the heat radiation effect and at the same time increase the thickness of the heat radiation base plate, so that it is possible to embody a resource saving oriented device.
【図１】本発明の実施形態を示す電力用半導体装置の要
部構造断面図である。FIG. 1 is a sectional view of a main part structure of a power semiconductor device according to an embodiment of the present invention.
【図２】本発明の他の実施形態を示す電力用半導体装置
の要部構造断面図である。FIG. 2 is a cross-sectional view of a main part structure of a power semiconductor device according to another embodiment of the present invention.
【図３】従来例の電力用半導体装置の要部構造断面図で
ある。（ａ）は，各要素を接合する前の構造説明図であ
る。（ｂ）は，各要素を接合した半田凝固点付近の温度
における形状を説明するための図である。（ｃ）は，各
要素を接合した常温での形状変化分を拡大して示した図
である。FIG. 3 is a cross-sectional view of a main part structure of a conventional power semiconductor device. (A) is a structural explanatory view before each element is joined. (B) is a diagram for explaining the shape at a temperature near the solder solidification point where the elements are joined. (C) is an enlarged view of the shape change at room temperature in which the respective elements are joined.
２ 放熱ベース板 ４ 耐熱性絶縁板（両面の導電層を含む） ４ａ セラミック板 ４ｂ 上面メタライズ層 ４ｃ 下面メタライズ層 ５ 耐熱性絶縁板（両面の導電層を含む） ５ａ セラミック板 ５ｂ 上面メタライズ層 ５ｃ 下面メタライズ層 ６ 電力用半導体チップ ８ 半田 １０ 半田 １２ 金属ペレット １４ 半田 １６ 半田 2 Heat dissipation base plate 4 Heat resistant insulating plate (including conductive layers on both surfaces) 4a Ceramic plate 4b Upper metallized layer 4c Lower metallized layer 5 Heat resistant insulating plate (including conductive layers on both surfaces) 5a Ceramic plate 5b Upper metallized layer 5c Lower surface Metallized layer 6 Power semiconductor chip 8 Solder 10 Solder 12 Metal pellet 14 Solder 16 Solder
Claims (2)
縁板と，放熱ベース板との間に，耐熱性絶縁板に設けら
れメタライズ層の厚みより厚く，放熱ベース板より薄い
熱膨張緩衝材を介して接合した電力用半導体装置。1. A thermal expansion buffer, which is provided on a heat-resistant insulating plate and is thicker than a metallized layer and thinner than a heat-radiating base plate, is provided between a heat-resistant insulating plate on which a power semiconductor chip is mounted and a heat radiating base plate. Power semiconductor device joined via a wire.
クス板の裏面に，セラミックス板の厚みと略同等の厚み
のメタライズ層を設けて，このメタライズ層と，放熱ベ
ース板とを接合した電力用半導体装置。2. A power semiconductor device in which a metallized layer having a thickness substantially equal to the thickness of a ceramic plate is provided on a back surface of a ceramic plate on which a power semiconductor chip is mounted, and the metallized layer is joined to a heat dissipation base plate. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11017113A JP2000216308A (en) | 1999-01-26 | 1999-01-26 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11017113A JP2000216308A (en) | 1999-01-26 | 1999-01-26 | Power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000216308A true JP2000216308A (en) | 2000-08-04 |
Family
ID=11934990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11017113A Pending JP2000216308A (en) | 1999-01-26 | 1999-01-26 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000216308A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956646B (en) * | 2005-10-19 | 2010-07-28 | 信越化学工业株式会社 | Heat-generating electronic part cover and cover mounting method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192341A (en) * | 1990-11-24 | 1992-07-10 | Hitachi Ltd | Semiconductor device |
| JPH0590444A (en) * | 1991-09-26 | 1993-04-09 | Toshiba Corp | Ceramic circuit board |
-
1999
- 1999-01-26 JP JP11017113A patent/JP2000216308A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192341A (en) * | 1990-11-24 | 1992-07-10 | Hitachi Ltd | Semiconductor device |
| JPH0590444A (en) * | 1991-09-26 | 1993-04-09 | Toshiba Corp | Ceramic circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956646B (en) * | 2005-10-19 | 2010-07-28 | 信越化学工业株式会社 | Heat-generating electronic part cover and cover mounting method |
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