JP2000216244A - Semiconductor device and manufacture of it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time and processes required for correcting/adjusting of a semiconductor integrated circuit, by forming a second metal wiring on a first metal wiring through the first metal wiring, protruding part, and a second insulating film on a first insulating film, with the first and second metal wirings and the second insulating film forming a capacitor. SOLUTION: A polysilicon film 7 is formed in protruding form on a first insulating film 5 on a semiconductor substrate 1, and a first metal wiring 9 is formed on the insulating film 5 and the polysilicon film 7. A second insulating film 11 is formed on the first metal wiring 9, polysilicon film 7, and first insulating film 5, while a second metal wiring 13 is formed on the first metal wiring 9 through the second insulating film 11. Those first metal wiring 9, second insulating film 11, and second metal wiring 13 on the polysilicon film 7 form a capacitor. Thus, the time and processes required for correcting/adjusting a semiconductor integrated circuit are reduced as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a capacitor and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art First, the structure of a conventional semiconductor device having a capacitor will be described with reference to FIGS. FIG. 3 is a plan view of a conventional semiconductor device having a capacitor, and FIG. 4 is a sectional view of the capacitor taken along line BB '. In a conventional capacitor, a diffusion layer 102 in a semiconductor substrate 101 is used as a first electrode and a polysilicon formed on an element isolation region 103 and an oxide film 105 via an oxide film 105 formed on the semiconductor substrate 101. The film 107 is configured as the second electrode. When forming the capacitance of the semiconductor integrated circuit, a plurality of redundant capacitors are formed in advance, and the size of the capacitance is adjusted by cutting the unnecessary metal wiring 109 of the capacitor according to the situation of the circuit design. . This is because the wiring layout structure requires a large capacity or becomes unnecessary. This method is called a laser cutting method. next,
A process of forming a capacitor on a semiconductor substrate and adjusting the capacitor by a laser cutting method will be described in detail with reference to FIG. First, a gate oxide film 105 and a polysilicon film 107 are formed on a semiconductor substrate 101 by a manufacturing process of a MOS transistor, and a capacitor composed of an N-type diffusion layer 102, a gate oxide film 105, and a polysilicon film 107 is formed. Is done. Next, the metal wiring 109 is connected to the formed capacitor, and the uppermost wiring 110 is connected to the metal wiring 109 to form a semiconductor integrated circuit. Circuits for semiconductor integrated circuits
When the capacitance is changed by changing the wiring, an opening 117 is formed by opening the protective film 115 of the uppermost wiring 110. Thereafter, the wiring connected to the unnecessary capacitor is cut by the laser to change the entire capacitance. Alternatively, by changing the mask pattern at the time of photolithography, the optimum wiring is selected to optimize the capacitance.

[0003]

In the above-described conventional method of forming a capacitor, a capacitor is formed by a MOS transistor manufacturing process. In order to adjust the change in capacitance by changing the circuit layout, unnecessary capacitance is cut by cutting the uppermost layer wiring by, for example, a laser cutting method. However, if the entire capacitance cannot be adjusted only by cutting off the redundant capacitors, it is necessary to return to the lowermost layout and change the layout. For this reason, the change of the capacitance value must be changed to the lowest layer, which takes time. In addition, there is a problem that the layout structure is complicated and the accuracy of the capacitor is deteriorated. Therefore, an object of the present invention is to minimize the time and process required for circuit correction / adjustment of a semiconductor integrated circuit by forming a capacitor in an upper layer using a conventional multilayer wiring process.

[0004]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a projection formed on a first insulating film on a semiconductor substrate and a first insulating film. A first metal wiring formed on the film and the convex portion, a second metal film formed on the first metal wiring, the convex portion and the first insulating film, and a first metal wiring via the second insulating film And a second metal wiring formed thereon, wherein the first metal wiring, the second insulating film, and the second metal wiring form a capacitor. Further, the features of the method of manufacturing a semiconductor device according to the present invention include a step of forming a convex portion on a first insulating film on a semiconductor substrate, and a step of forming a first metal wiring on the first insulating film and the convex portion. A second metal wiring on the first metal wiring, the convex portion and the first insulating film.
Forming an insulating film; forming a second metal wiring on the first metal wiring via the second insulating film;
Forming a capacitor composed of an insulating film and a second metal wiring; and cutting the second metal wiring to form a desired wiring. According to the feature of the present invention, by providing the step structure in the upper layer wiring, it is possible to form a capacitor composed of metal wiring / insulating film / metal wiring, and to change the layout of the upper layer when adjusting the capacitance. Thus, the capacity can be adjusted.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention shown in the present invention will be described below with reference to FIGS. FIG. 1 is a plan view of a semiconductor device having a capacitor according to the present invention, and FIGS. 2A to 2C are cross-sectional views taken along line AA 'showing the steps of manufacturing the capacitor. First, as shown in FIG. 1, a semiconductor device according to the present invention has a polysilicon film 7 formed on an insulating film 5 on a semiconductor substrate 1.
And a metal wiring 9 formed on the insulating film 5 and the polysilicon film 7, and a metal wiring 9, the polysilicon film 7 and the insulating film 5.
An insulating film formed on the insulating film, and a metal wiring formed on the metal wiring via the insulating film;
No. 3 is characterized by forming a capacitor. Further, a plurality of capacitors are formed on the semiconductor substrate 1. This is because, when the capacitance of the semiconductor integrated circuit is formed, a redundant capacitance is formed in advance, and when the capacitance of the integrated circuit becomes excessively large due to the circuit design, the metal wiring 13 of the unnecessary capacitance portion is cut off. The size of the capacity is adjusted. This method is called a laser cutting method. Next, a process of forming a capacitance on a semiconductor substrate and adjusting the capacitance by a laser cutting method will be described in detail with reference to FIGS.

First, as shown in FIG. 2A, an element isolation region 3 is formed on a semiconductor substrate 1 by, for example, a LOCOS method. Further, an insulating film 5 is formed on the element isolation region 3 and other elements. Further, a polysilicon film 7 is formed on the insulating film 5 as a sheet-shaped step before forming the metal wiring. The step is formed by depositing polysilicon, silicon nitride or silicon oxide, and performing photolithography / etching.
Next, as shown in FIG. 2B, an insulating film 11 is deposited as an interlayer insulating film for insulation from the upper metal wiring. After the deposition of the insulating film 11, a flattening process of the insulating film 11 is performed. Usually, this planarization process is performed by RIE (reactive ion etching) or CMP (chemical mechanical polishing). At this time, the interlayer insulating film 11 on the polysilicon film 7 having the step structure is the same as the gate oxide film. It is desirable that the film be formed thin so as to have a film thickness of the order. The thickness controls the thickness of the polysilicon film 7 according to the required capacitance of the capacitor.
Next, as shown in FIG. 3C, after the formation of the insulating film 11, the upper metal wiring 13 is formed. At this time, the wiring on the polysilicon film 7 is formed in a sheet shape. Thereby, a capacitor is formed by the upper metal wiring 13, the lower metal wiring 9 and the insulating film 11. By arbitrarily changing the sheet surface of the upper metal wiring 13, the capacitance of the capacitor can be arbitrarily changed. Since the capacitance of the circuit increases in the wiring layout process, the protection film 15
Is opened and the wiring connected to the unnecessary capacitor is cut by the laser to adjust the capacity of the semiconductor integrated circuit.

In this case, when the entire capacitance cannot be adjusted only by cutting off the redundant capacitor, the capacitance of the circuit can be adjusted only by changing the upper layer wiring layout. As a result, the time and process required for circuit correction / adjustment of the semiconductor integrated circuit can be reduced as much as possible. In the present invention, a sheet-shaped wiring is formed on the planarized insulating film. For this reason, since the capacitor has a flat two-layer structure, it is possible to provide a capacitor with high accuracy close to the design value. Further, the same effect can be obtained when a capacitor is formed by using intermediate wiring layers without using the uppermost layer wiring shown in the present embodiment. It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit thereof.

[0008]

As described above, according to the present invention, since the capacitor of the present invention is formed in a multilayer wiring process, the time required for changing the capacitance of the capacitor can be reduced. Also,
Since the capacitance value can be controlled only by changing the upper layer wiring, a capacitor that is substantially the same as the initially designed capacitor can be formed, and a semiconductor integrated circuit having a high-precision capacitor can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device having a capacitor according to the present invention.

FIG. 2 is a sectional view sequentially showing a method of manufacturing a semiconductor device having a capacitor according to the present invention.

FIG. 3 is a plan view of a conventional semiconductor device.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Diffusion layer 3 Element isolation region 5 Insulating film 7 Polysilicon film 9 Lower metal wiring 11 Insulating film 13 Upper metal wiring 15 Insulating film 17 Opening

Claims (8)

[Claims] 1. A convex portion formed on a first insulating film on a semiconductor substrate, a first metal wiring formed on the first insulating film and the convex portion, the first metal wiring, and the convex portion. And a second insulating film formed on the first insulating film, and a second metal wiring formed on the first metal wiring via the second insulating film. . 2. The semiconductor device according to claim 1, wherein the first metal wiring, the second insulating film, and the second metal wiring on the projection form a capacitor. 3. The semiconductor device according to claim 1, wherein said first metal wiring and said second metal wiring are completely insulated by said second insulating film. 4. A first metal wiring, a second insulating film, and a second metal wiring on the projection form a plurality of capacitors,
2. The semiconductor device according to claim 1, wherein at least one of said capacitors is electrically disconnected from said second metal wiring. 5. The semiconductor device according to claim 1, wherein said second metal wiring is an uppermost wiring. 6. A MOS transistor further below the first insulating film, wherein a thickness of the second insulating film sandwiched between the first metal layer and the second metal layer is equal to a gate of the MOS transistor. 2. The semiconductor device according to claim 1, wherein the thickness is about the thickness of the oxide film. 7. A step of forming a convex portion on a first insulating film on a semiconductor substrate; a step of forming a first metal wiring on the first insulating film and the convex portion; Forming a second insulating film on the convex portion and the first insulating film, and forming a second metal wiring on the first metal wiring via the second insulating film;
A method for manufacturing a semiconductor device, comprising a step of forming a capacitor including a metal wiring, the second insulating film, and the second metal wiring. 8. The method according to claim 8, wherein a plurality of said capacitors are formed and said second capacitor is formed.
8. The method of manufacturing a semiconductor device according to claim 7, wherein an unnecessary region of the capacitor is electrically cut by cutting a metal wiring.