JP2000215672A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate bit line select means sequentially in units of the number of I/O configurations by connecting the output of the bit line select means with the input of a plurality bit line select means through a precharge control means and inputting a control signal also to other precharge control means through a timing control means. SOLUTION: A precharge signal is transmitted to a signal line PC2b with a time lag set by a timing control circuit 161 after an operation of a precharge control circuit 140 is started. All column gates connected with the output of a precharge control circuit 141 are selected and turned on to start precharge. Subsequently, a precharge control signal connected with a signal line. PC3b is operated with a time difference in addition to a timing control circuit 162 and the output signal line PC3b thereof. Since a time difference can be set equal to the time required for starting precharge after each precharge control circuit is turned on, the peak of the bit line current can be shifted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a bit line precharge.

[0002]

2. Description of the Related Art In a semiconductor memory device, before or after data input / output is performed by being connected to a memory cell or after performing an operation called precharge for keeping a bit line at a predetermined voltage, data on the bit line is reset. Prepare for the next read / write operation. By performing this precharge operation, data input / output to / from the memory cell and data retention can be performed stably, and the speed of data input / output to / from the memory cell can be improved.

[0003] The precharge is generally performed by adding a precharge circuit to the bit line and setting the bit line to a predetermined potential in an organization that does not perform a read / write operation.
Japanese Patent Application Laid-Open No. 06195977 discloses a technique in which the addition of a precharge circuit to a bit line is stopped and the bit line is precharged using a data writing circuit.

FIG. 4 is a circuit diagram showing a part of a conventional semiconductor memory device of a precharge method using a data writing circuit. 400 in FIG. 4 represents a memory cell,
The memory cell 400 is connected to a word line and bit lines BL and BLb. Row decoder 420 receives address signal X-
Addr. And the word driver 430 drives the selected word line. Bit line pair BL1, BL1b is connected to data bus pair DB, DBb via column gate circuit 440. The output of the decode value selection circuit 450 is connected to the Nch transistor gate electrode of the column gate circuit. Decode value selection circuit 4
Reference numeral 50 denotes an OR gate, and an OR gate 451
Is connected to the output of the column decoder 470, and the other input is a signal sel. The column decoder circuit 470 receives the address signal Y-Addr. Select the column gate circuit corresponding to. A sense amplifier 480 and an I / O circuit 490 are connected to the data buses DB and DBb.
I / O circuit 490 provides signal Wr. En, the signal Pr. En,
The signal Dout is input and the signal Din is output.

The operation of FIG. 4 will be described.

Now, X-Addr. And Y-Addr. Memory cell 400 connected to BL1 and BL1b
Is selected and a data read operation is performed. The data held by the selected memory cell is transmitted from the bit line pair to the data buses DB and DBb via the column gates, amplified by the sense amplifier 480, and then I / O circuit 490
Output from At this time, all the memory cells connected to the selected word line are in the active state, and the data is output to the bit line pair to which each is connected.

In the case of FIG. 4, the bit line pair is at a High level, a Low level, or a potential state opposite thereto.
However, since the column gate is OFF, it is not connected to the data bus and does not malfunction. Such a state in which data is output and not connected to the data bus is hereinafter referred to as a pseudo read state. After the read operation, the selected word line is in a non-selected state, BL1, B
The column gate connected to L1b is also turned off, and BL1 and BL1b are also turned off. At this point, the bit line pair to which all the memory cells that were active at the time are connected is in a potential state according to the data that the memory cell has. After all the word lines and column gates are in the non-selected state, the precharge signal Pr. En
Shifts from the inactive state to the active state, and both of the two outputs connected to the data bus of the data write circuit change the potential to the precharge level and the signal sel.
Changes from the inactive state to the active state, the output of the decode value selection circuit 450 turns on all the column gates regardless of the output of the column decoder. As a result, all the bit lines are connected to the output of the data write circuit via the data bus, and all the bit lines are precharged to the precharge level of the data write circuit. After completion of the precharge, the signal sel shifts to the non-selection state, the output of the decode value selection circuit changes according to the output of the column decoder circuit, and the precharge signal Pr. En shifts to the non-selected state, and the data writing circuit stops outputting the precharge level. When the precharge is completed, X-Addr. And Y-Ad
dr. The read operation to the memory cell designated by is performed. The read operation is performed by repeating this operation cycle.

The same applies to a data write operation. Data is written by connecting a selected bit line to a data bus via a column gate circuit, and the other bit lines are in a pseudo read state. After the data writing is completed, a precharge operation is performed.

[0009]

However, the conventional precharge method has a disadvantage that the current flows through a large number of bit lines at a time when precharge is performed, so that the peak current becomes extremely large.

If the peak current exceeds the electromigration resistance of the power supply wiring material in the memory cell array, the wiring is broken. The electromigration tolerance indicates the amount of current that can flow per unit area. To avoid exceeding this, widen the wiring, increase the thickness of the wiring layer (increase the cross-sectional area), or use a word. It is conceivable to reduce the number of memory cells connected to a line to reduce the number of bit lines precharged at the same time. However, the method of increasing the thickness of the wiring layer has a significant effect on the product characteristics, and the method of increasing the wiring width has a disadvantage of increasing the chip size. The method of reducing the number of memory cells connected to a word line also increases the number of word line decoders and increases the chip size.

In the technique of performing bit line precharge using a data write circuit, in addition to the problem of the peak current of the bit line precharge, the size of a transistor for driving the data bus of the data write circuit is increased or reduced. There are drawbacks such as the need to provide a circuit. This is because, in a semiconductor memory device in which a precharge circuit is added to a bit line, a data write operation is performed on one bit line, so that one bit line is designed with a size capable of driving the capacity of the data bus. On the other hand, in a semiconductor memory device that performs precharge using a data write circuit, it is necessary to drive a plurality of bit lines at the time of precharge, and a transistor having a larger size than the former must be used. It is.

Therefore, in the present invention, there is a margin for the electromigration resistance by suppressing the peak current at the time of precharging. That is, since the wiring is not miniaturized or the number of memory cells connected to the word line is not reduced, high integration is achieved. Possible, high-stability semiconductor memory device with a margin for noise, and when precharging is performed using a data writing circuit, there is no need to increase the size of the transistor driving the data bus of the data writing circuit. Therefore, a semiconductor memory device which can be highly integrated is provided.

[0013]

According to the semiconductor memory device of the present invention, a plurality of memory cells arranged in a matrix are connected to a word line and a bit line, respectively, according to the input / output data configuration in the plurality of memory cells. And word line selecting means for selecting at least one or more memory cells, and the bit line is connected to data input / output means via bit line connecting means, and the bit line is precharged. A predetermined voltage is obtained before or after the data read / write operation by the operation. The precharge operation is performed in a semiconductor memory device performed by setting the output of the data write circuit to a precharge level and controlling the bit line connection means. Connecting the output of the bit line selection means and the inputs of the plurality of bit line connection means via precharge control means, The control signal input to the control means is also input to the other precharge control means via the timing control means, so that the bit line connection means is sequentially operated in units of input / output configuration during the precharge operation. Features.

According to another semiconductor memory device of the present invention, a plurality of memory cells arranged in a matrix are connected to a bit line, and a precharge operation for setting a predetermined voltage to the bit line before or after a read / write operation is performed. In the semiconductor memory device in which the precharge operation is performed by a control signal input to the precharge means connected to the bit line, the number of the bit lines for performing the precharge is divided for each input / output configuration number unit. The control signal is sequentially transmitted to each of the precharge units via the timing control unit.

Another semiconductor memory device of the present invention performs precharge by adding precharge means to a bit line, and at the same time, performs precharge by using a data write circuit. And a common control signal input to the precharge means and the precharge control means, so that the precharge means and the precharge control means simultaneously use the same bit line. It is characterized by being precharged.

Another semiconductor memory device according to the present invention is a semiconductor memory device which performs precharge using the data write circuit according to the above-mentioned invention, wherein the precharge of the precharged bit line group is completed. The precharge of the next bit line group is started after the selected column connection unit is deselected.

Another semiconductor memory device of the present invention is a semiconductor memory device which performs precharge by using both the data write circuit of the above invention and a precharge circuit added to a bit line. The precharge of the next bit line group is started after the precharge of the group is completed or precharged to a predetermined potential and the connection means is deselected.

[0018]

When precharging is performed using a data write circuit, a column decoder output and a column gate input are connected via a precharge control circuit, and a precharge signal input to the precharge control circuit is output. By transmitting the signals sequentially with a time difference, the precharge start time is shifted for each bit line group.

When precharging is performed by adding a precharge circuit to a bit line, the precharge circuit is divided for each input / output configuration and the precharge signal input to each precharge circuit group is divided. It is transmitted sequentially with a time difference.

Further, when precharging is performed using the data write circuit, the column gate is controlled so that one bit line is connected to one data bus.

[0021]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention. In FIG. 1, reference numeral 100 denotes a data write circuit, and reference numerals 100, 111, 112, and 113 denote bit line clamp circuits composed of Pch transistors. A source electrode is a power supply potential, a drain electrode is a bit line, and a gate electrode is a drain electrode. Bit line pair is connected to the other bit line. Reference numerals 120 and 121 denote memory cells which are connected to a bit line pair and a word line SWL which is an output of a row selecting means. 130, 131, 133, and 134 are transfer gates, and 132 and 135 are inverters.
One of the column gates 131, 132 or 133, 134, 135 constitutes a column selecting means. One of the column gates is connected to a bit line, and the other is a data bus DB1,
Connected to DB1b to DBn, DBnb. n is the same number of input / output configurations and is an arbitrary number now. 140 and 141 are precharge control circuits whose outputs are connected to column gates, one of the inputs is connected to the output of the column decoder, and the other input is connected to precharge signals PC1b and PC2b.
150 and 151 are column decoder circuits for address signals C
The output is connected to the precharge control circuit with the input of the address and the redundant signal. 160, 16
Reference numeral 1 162 denotes a timing control circuit which comprises two stages of inverters in FIG. The timing control circuit 160 receives the signal line PCb as input and outputs PC1b as output. Similarly, the timing control circuit 161 receives the signal line PC1b as an input and
2b is output and the timing control circuit 162 outputs the signal line P
C2b is input and PC3b is output.

In FIG. 1, data read and write operations are the same as those of the conventional semiconductor memory device. When reading and writing of data are completed and a precharge period is reached, SWL is deselected and the column gates are all closed once. When all the column gates are turned off, the precharge signal is input to the signal line PCb and the data write circuit 100
Are all at the precharge level. At the same timing as the output of the data write circuit 100 precharges the data bus, the timing control circuit 160
As a result, the precharge signal input to the 1000th line PCb is output to the signal line PC1b. Therefore, all the column gates connected to the output of the first precharge control circuit 140 are turned on, and the precharge is started. After the precharge control circuit 140 starts operating, a precharge signal is transmitted to the signal line PC2b with a delay of the time set by the timing control circuit 161.
All the column gates connected to the output of 41 are selected and turned on to start precharge. Thereafter, the timing control circuit 163 and its output signal line PC3b,
Although not shown, the precharge control signal connected to the signal line PC3b also operates with a time difference. As described above, the time when each precharge control circuit is turned on and the precharge is started can have a settable time difference, and the peak of the bit line current due to the precharge can be shifted. Therefore, the overall peak current at the time of bit line precharge can be reduced.

The above-described timing control circuit 160 in FIG. 1 does not need to depend on the circuit configuration. For example, the data bus is precharged by a separate circuit, and the data bus is precharged before the bit line precharge is performed. In such cases, the start of precharge in the data write circuit and the operation timing of the precharge control circuit 140 may be the same. Also, the timing control circuit need not have the configuration as shown in FIG. 1 as long as the same effect can be obtained. For example, the signal line PC1b
And the signal line PC2b may be connected by a switch such as a transfer gate, and the switch may be sequentially turned on with a time difference.

The circuit shown in FIG. 2 is a circuit diagram showing one embodiment of the data write circuit. 2 shows a portion corresponding to the data write circuit 100 in FIG.
Is a write circuit for data buses DB1 and DB1b, circuit 220 is a data write circuit for DB2 and DB2b, and circuit 230 is a data write circuit for the nth data bus pair. Data1
Is a signal line for transmitting data coming from the input / output circuit, to which the inverter 200 and the transmission gate 201 are connected. Transmission gate 202 is connected to the output of inverter 200. The gate electrode inputs of the transmission gates 201 and 202 are common,
The precharge signal PCb is input to the Nch side gate, and the output of the inverter 240 that outputs an inverted signal of the precharge signal PCb is connected to the Pch side gate electrode. The input of the inverter 205 for driving the data bus DB1 is connected to the other end of the transmission gate 201, and the input of the inverter 206 for driving the data bus DB1b is connected to the other end of the transmission gate 202. The connection line between the transmission gate 201 and the input of the inverter 205 is connected to the drain electrode of the Nch transistor 203, and the source electrode of the Nch transistor 203 is connected to the ground potential. The connection line between the transmission gate 202 and the input of the inverter 206 is also N
The drain electrode of the channel transistor 204 is connected, and N
The source electrode of the channel transistor 204 is connected to the ground potential. The gate electrodes of the Nch transistors 203 and 204 are commonly connected to the output of the inverter 240 to receive an inverted signal of the precharge signal PCb.

The operation of FIG. 2 is as follows. At the time of data write operation, the precharge signal PCb is set to the non-selected state h.
It is at the high level. In this state, transmission gates 201 and 202 are on, Nch transistors 203 and 204 are off, and signal Dat
a1 is output complementarily to DB1 and DB1b. When the precharge signal PCb becomes the selected low level after the end of the data write period and the precharge signal PCb becomes the selected low level, the transmission gates 201 and 202 are turned off and the Nch transistors 203 and 204 are turned on and the inverter is turned on. L of 205 and 206 inputs
ow level. As a result, the inverters 205, 20
6 goes high and the data buses DB1, D
B1b is the power supply potential which is the precharge level. Thereafter, as described with reference to FIG. 1, when the column gate circuit is turned on and the bit line is connected to the data bus, the bit line is precharged.

In FIG. 2, the precharge level is set to the high level.
When the channel transistor is used, the source electrode is connected to the power supply potential, and the gate electrode is connected to the precharge signal line PCb. When the precharge level is set to a value other than the power supply potential or the ground potential, it is possible to utilize the Vth of the transistor.

FIG. 3 is a circuit diagram showing one embodiment of another semiconductor memory device of the present invention. FIG. 3 shows a bit line precharge circuit, a bit line potential clamp circuit and a bit line equalize circuit, which are precharge means. Pch transistors 301 and 304 in FIG. , The drain electrode is connected to the bit line, and the gate electrode is connected to the ground potential. The Pch transistors 302 and 303 are bit line precharge circuits in which the source electrode is connected to the power supply potential and the drain electrode is connected to the bit line. The gate electrode is connected to the precharge signal line Pc1b, and its conduction is controlled by a control signal. The Pch transistor 305 is connected so that the bit line pair can be short-circuited by an equalizing circuit.

The gate electrode is connected to a precharge signal line PC
1b, and its conduction is controlled. 306 is a memory cell and SWL connected to the memory cell is a word line. FIG. 3 shows a precharge / equalize circuit connected to a precharge signal line PC1b assuming a 4-bit input / output semiconductor memory device.
Although the number of bit line pairs is limited to four for BL4 and BL4b, eight are connected when the input / output configuration is 8 bits, and 16 for 16 bits. The circuit 310 is a timing control circuit which is a timing control means. The precharge signal line PC1b is input to the circuit 310, and a control signal in-phase and delayed with respect to the precharge signal line PC1b is output to the precharge signal line PC2b. The signal is transmitted to the precharge / equalize circuit group for the next four bit lines.

The operation of FIG. 3 will be described.

In the circuit of FIG. 3, bit lines BL1, BL
It is assumed that data read operations of 1b to BL4 and BL4b are performed. At this time, the selected bit line is connected to a data bus (not shown) via a selected column gate (not shown). Although a plurality of memory cells (not shown) connected to the word lines are activated, the bit lines connected to the respective memory cells are in a pseudo read state not connected to the data bus. Next, after the data reading period ends, the word line and the selected column gate (not shown) shift to the non-selected state. At this time, the bit line from which data was read and the bit line which was in the pseudo read state are in a potential state corresponding to the data held in the memory cell. In this state, when a precharge signal is applied to the precharge signal line PC1b, precharge circuits 302 and 303 connected to the precharge signal line PC1b first connect the bit lines to the power supply potential to start precharge. You. At the same time, the equalizing circuit 305 conducts, and the bit line pair is short-circuited to make the bit line pair the same potential, thereby increasing the precharge speed. When the precharge signal is delayed from PC1b by the timing control circuit 310 and transmitted to the precharge signal line PC2b, a precharge circuit / equalize circuit group connected to the PC2b (not shown) starts precharging / equalizing the bit line. . PC2b
Is in the selected state after the delay time set by the timing control circuit 310, so that the peaks of the bit line currents at the time of precharging of PC1b and PC2b do not overlap.

From the above, the peak current at the time of precharging the bit lines as a whole can be made lower than that of the conventional semiconductor memory device, so that a margin can be secured for the electromigration resistance.

FIG. 5 is a graph showing the bit line current of the conventional semiconductor memory device and the semiconductor memory device of the present invention. The distribution diagrams (5-A-1) to (5-A-
Until 3), the waveform of the conventional semiconductor memory device, (5-B-
1) to (5-B-3) are waveforms of the semiconductor memory device of the present invention.

In the semiconductor memory device of the present invention and the conventional semiconductor memory device, the word lines SWL1 and SWL2 shown in (5-A-1) and (5-B-1) and the column gate selection signal Col
Umn-Gate1 and Column-Gate2 have the same waveform. First, the word line SWL <b> 1 is in the selected state. Word line SWL2 remains unchanged in the non-selected state. After the word line SWL1 is deselected, the column gate selection signal Column-Gate1 changes from the selected state to the non-selected state. Column-Gat
e2 remains unselected. After the word line and the column gate are deselected, the precharge signal PCb changes from the non-selected state to the selected state. In the conventional semiconductor memory device, when the PCb is in the selected state, the column gate selection signals Column-Gate1 and Column-Gate1 are set.
2 turns ON, and precharge starts. However, in the semiconductor memory device of the present invention, as shown in (5-B-1), the precharge signal PCb is substantially divided into a plurality of times and becomes the selected state. The current waveform of one bit line of the conventional semiconductor memory device is shown in (5-A-2), and the current waveform of one bit line of the semiconductor memory device of the present invention is (5-B-
It is the same if one focuses on 2). But,
If all the precharged bit lines have been reached (5
While (A-2) simply increases by the number of bit lines, (5-B-2) has a waveform with a low current peak and a width.

FIG. 5 (5-A-3) is a waveform showing the total sum of bit line currents at the time of precharge of the conventional semiconductor memory device.
(5-B-3) is a waveform showing the sum of bit line currents at the time of precharge of the semiconductor memory device of the present invention. In both cases, the power supply voltage is 3.6 V, and the bit line Low level side potential becomes the ground potential when data is read.
It is an example of a result when a memory cell is connected, and (5-A
-3) has a peak current that greatly exceeds 100 mA indicated by the dotted line, whereas (5-B-3) has a peak current of 100 mA or less. The magnitude of this peak current can be changed by setting the timing control circuit,
It can be smaller or larger than (5-B-3).

FIG. 6 is a timing chart showing another embodiment of the semiconductor memory device of the present invention. SWL1 and SWL in FIG.
2 indicates the state of the word line. PCPb, PCP1
Waveforms indicated by b to PCP3b indicate precharge signals corresponding to the PCb waveform of (5-B-1) in FIG.
For example, the precharge signal waveform input to the signal line PCb in the circuit diagram of FIG. 1 and PCP1b correspond to the signal waveform transmitted to PC1b. The waveforms indicated by CG1 and CG2 are shown in FIG.
Column-Gate1, Column-Gate
2 corresponds to the waveform shown in FIG.
3 shows the output waveforms of the reference numerals 40 and 141.

The waveform of PCPb in FIG. 6 is represented by (5-B-
The difference is that the waveform is shorter than the PCb waveform of 1) and that the timing is set so that the PCP1b is in the selected state after the PCPb is in the non-selected state.

How the FIG. 1 operates at the timing of FIG. 6 will be described. After SWL1 changes from the selected state to the non-selected state (SWL2 remains in the non-selected state), the precharge signal PCPb changes to the selected state to perform data bus precharge. When the data bus precharge is performed by another circuit as described above, PCPb is not required. When PCPb is completely terminated, PCP1b changes from the non-selected state to the selected state, and the precharge control circuit having PCP1b as input operates to make all the column gates connected to its output conductive. The timing relationship between PCP1b and CG1 is indicated by an arrow in FIG. Therefore, the bit line connected to the column gate that has become conductive is precharged. At this time, only one (one pair) bit line is connected to each data bus. Next, when PCP1b is deselected, all bit lines that have been precharged until then are disconnected from the data bus. Thereafter, PCP2b changes from a non-selected state to a selected state, a precharge control circuit using PCP2b as an input operates, and all the column gates connected to the output thereof become conductive, and a bit line corresponding to each data bus is connected. Connect. PCP2 as above
The relationship between b and CG2 is indicated by an arrow in FIG. Therefore, the connected bit line is precharged. At this time, only one (one pair) bit line is connected to each data bus. Hereinafter, the same applies to the PCP 3b shown in FIG.

The column shown by (5-b-1) in FIG.
The difference between the waveforms of the n-Gates 1 and 2 and the waveforms of the CGs 1 and 2 in FIG. 6 means that the number of bit lines connected to each data bus and precharged is one or more. . In the waveform of FIG. 5, the bit lines for which precharging is started are sequentially connected for each divided unit, and finally all the bit lines are connected to the data bus. In FIG. 6, only one bit line is always connected to each data bus.

The following effects can be obtained by the above difference in waveform.

When performing a data write operation, only one bit line is connected to each data bus. For this reason, the data bus driving transistor of the data writing circuit may be set to a minimum size that can drive the data bus and the capacity of one bit line. However, if one or more bit lines are connected to the data bus at the time of precharge, the data bus capacity must be set to a size that can drive the capacity of multiple bit lines. The size must be set larger than the size of the data bus driving transistor.

However, by using the timing shown in FIG. 6, the size of the data driving transistor may be the minimum size required at the time of data writing, and may be made larger than that, or another transistor may be connected only at the time of precharging. No need to configure. This is because, as described above, only one bit line is connected to each data bus during the precharge operation. Therefore, even in a semiconductor memory device that performs precharge using a data writing circuit, the data writing circuit does not need to be large and high integration can be achieved.

[0042]

By using the semiconductor memory device according to the present invention, the bit line precharge circuit can be eliminated, high integration can be achieved, and the peak current at the time of bit line precharge can be suppressed low. A margin is provided for the migration resistance, and finer wiring (higher integration) can be achieved. In addition, since a margin can be provided for noise, a semiconductor memory device that can be highly stabilized can be manufactured. Furthermore, high integration is possible because there is no need to increase the size of the data bus driving transistor of the data writing circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing an example of a data write circuit of the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention.

FIG. 4 is a circuit diagram showing an embodiment of a conventional semiconductor memory device.

FIG. 5 is a waveform chart showing bit line currents of the conventional semiconductor memory device and the semiconductor memory device of the present invention.

FIG. 6 is a timing chart showing another embodiment of the semiconductor memory device of the present invention.

[Explanation of symbols]

100 Data write circuit 110-113 Bit line potential clamp circuit 120, 121 Memory cell 130, 131, 133, 134 Transfer gate 132, 135 Inverter 140, 141 · Precharge control circuits 150, 151 ··· Column decoders 160 to 162 ··· Timing control circuits 200, 205 and 206 ··· Inverters 201 and 202 ··· Transfer gates 203 and 204 ··· Nch transistors 210 to 230 ··· Data write circuits 301 and 304 ··· Bit line potential clamp circuits 302 and 303 ··· Bit line precharge circuit 305 ··· Bit line equalize circuit 310 ··· Timing control circuit 450 ··· Decode value selection Times BL1, BL1b~BLn, BLnb ··· bit line pair DB, DBb, DB1, DB1b~DBn, DBnb
... Data bus pair PCb, PC1b to PC3b ... Precharge signal lines Data1 to Dataan ... Write data signal line SWL ... Word line

Claims (5)

[Claims] A plurality of memory cells arranged in a matrix are connected to a word line and a bit line, respectively, and at least one or more memory cells according to an input / output data configuration in the plurality of memory cells are selected. The bit line is connected to the data input / output means via the bit line connection means, and the bit line is set to a predetermined value before or after the data read / write operation by the precharge operation. In a semiconductor memory device in which the precharge operation is performed by setting the output of the data writing circuit to a precharge level and controlling the bit line connection means, the output of the bit line selection means and the output of the The input of the plurality of bit line connection means is connected via the precharge control means, and the control signal inputted to the precharge control means is controlled by the timing. Via the control means By inputting to other said precharge control means, a semiconductor memory device, characterized in that for successively operating the bit line connection means during said precharge operation input and output configuration unit number. 2. A plurality of memory cells arranged in a matrix are each connected to a bit line, and a precharge operation is performed on the bit line to a predetermined voltage before or after a read / write operation. In a semiconductor memory device which performs the control by a control signal input to a precharge means connected to a bit line, the number of the bit lines to be precharged is divided into input / output configuration units, and the control signal is subjected to timing control. A semiconductor memory device characterized in that the data is sequentially transmitted to each of the precharge means via the means. 3. A semiconductor memory device according to claim 1, wherein the precharge is performed by adding a precharge means to the bit line and the precharge is performed by using a data write circuit at the same time. And a control signal input to the precharge means and the precharge control means are shared to make the precharge means and the precharge control means the same. A semiconductor memory device characterized in that said bit lines are precharged simultaneously. 4. The semiconductor memory device according to claim 1,
A semiconductor memory device characterized in that after the precharge of a precharged bit line group is completed and the selected column connection means is deselected, the precharge of the next bit line group is started. 5. The semiconductor memory device according to claim 3, wherein
It is characterized in that precharging of the precharged bit line group is completed or precharged to a predetermined potential, and after the column connection means is deselected, precharging of the next bit line group is started. Semiconductor storage device.