JP2000181439A - Interlace image processing method and interlace image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the degradation in image quality even when an original picture is outputted after enlargement, reduction or deformation by using the signals formed by discarding the values below a quantization bit number relating to one of the data after the quantization of even and odd field and rounding-off the values below the quantization bit number relating to the other. SOLUTION: A capturing control section 14 stores the digital RGB signals of the respective fields into an image memory 22 through an image quality improvement processing section 20 in accordance with the synchronizing signal from a synchronization separation section 10 and the field signals from a field identification section 12. An image quality improvement processing section 22 executes dithering on a time base. Namely, the image quality improvement processing section 20 captures the digital RGB signals in accordance with the signal from the capturing control section 14 and executes the processing to discard the values below the predetermined prescribed quantization bit number if the field to be processed is the even field. The processing section executes the processing to round-off the values below the predetermined prescribed quantization bit number if the field to be processed is the odd field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlaced image processing method and an interlaced image processing apparatus, and more particularly to a method of dividing an image regarded as one image in one frame into a time axis of an even field and an odd field.
The present invention relates to an interlaced image processing method and an interlaced image processing device for synthesizing and displaying one frame again.

[0002]

2. Description of the Related Art A palette reference type drawing apparatus has been proposed as a drawing apparatus equipped with a method of outputting a color interlaced image. Such a drawing device is an original picture designed with a limited number of colors from the original picture designed in advance from a full-color original picture with a certain algorithm so as to be inferior to the original image on human vision with some algorithm. The number of bits per pixel of the image memory is reduced by storing the color set having a limited number of colors in the palette memory and referring to the color set.

[0003] This palette reference type drawing apparatus has a problem in that when full-color images such as video signals are stored in an image memory in real time and transferred to a display memory without delay, appropriate color reproduction cannot be performed. . This is because it is difficult to execute the above-described color-reduction algorithm that is inferior to human vision at low cost in real time.

In order to solve such a problem, a fixed palette in which R (red), G (green), and B (blue) are regularly allocated is used to draw a full-color image taken in real time from the outside. The number of bits per pixel has been reduced by mechanically truncating the lower bits of the quantized bits of each pixel of RGB, and stored in the image memory.

More specifically, R,
G and B have 5 bits, 5 bits and 5 bits, respectively, whereas the image memory has 8 bits per pixel (256 bits).
Color), R, G,
3 bits, 3 bits, which are upper bits of each B data,
Only two bits are stored in the image memory as the color number data of the pixel, and at the time of drawing, the three bits, three bits, and two bits are each set to be extended to eight bits by a certain method in a palette memory which is regularly set. Was drawn in the display memory with reference to the.

[0006]

As described above, the 5-bit, 5-bit, and 5-bit RGB separate data used at the time of drawing are composed of truncated lower bits of 2 bits, 2 bits, and 3 bits. The value is fixedly generated by the extended method. Generally, it is a repetition of upper bits or a default value, for example, 0. However, since the truncated original data cannot be restored, the image displayed on the display device is a 256-color, light image even if the display memory can display full color.

As a technique for solving such technical problems,
For example, a method of increasing the apparent number of colors by performing a dithering process on an input image and storing the image in an image memory is generally known. Such techniques include scaling,
This is effective when displaying without performing deformation or the like.

However, when the original picture stored in the image memory is displayed after being enlarged, reduced, or deformed, the dither pattern is crushed, enlarged, or thinned out, resulting in a mosaic pattern or aliasing (regular pattern). ) Occurs, and the image quality is degraded because the dithering effect is canceled or overemphasized.

The present invention has been made on the basis of the above circumstances, and has an interlaced image processing method, an interlaced image processing apparatus, and a computer capable of suppressing a decrease in image quality even when an original picture is enlarged, reduced or deformed and output. It is an object to provide a readable storage medium.

[0010]

In order to achieve the above object, an interlaced image processing method according to the present invention quantizes an interlaced image constituting one frame by an even field and an odd field for each field and stores the quantized image in an image memory. In the interlaced image processing method for storing and outputting an interlaced image from the original picture stored in the image memory, any one of the quantized data of the even field and the quantized data of the odd field may be used. A value smaller than a predetermined quantization bit number is discarded, and a value smaller than a predetermined quantization bit number is rounded off and stored in the image memory.

[0011] The interlaced image processing apparatus of the present invention comprises:
A / D conversion means for performing an analog-to-digital conversion of an interlaced image constituting one frame by the even-numbered field and the odd-numbered field, and one of the analog-to-digital converted even-field data and odd-field data Image quality improvement processing means for truncating a value equal to or less than a predetermined quantization bit number for one, and rounding and outputting a value equal to or less than a predetermined quantization bit number for the other; and And image storage means for storing the output signal from each field for each field.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described. The dithering process is a method of stochastically reproducing and expressing data that is to be discarded when an input image is quantized, is redistributed to a plurality of pixels and added. For example, considering that a black and white image is dithered in units of two vertical pixels, assuming that two pixels have the same color and each have a value of 10.5, one of the two pixels has a fractional part 0 to be discarded. .5 is redistributed and added to the other, so that one is 10 and the other is 11,
The human eye sees 10.5 averaged over two pixels.

In an interlaced image, even-numbered lines and odd-numbered lines have a large correlation, so that two vertical pixels can be regarded as having substantially the same color. Assuming that the even and odd lines are of the same color, applying the dithering will result in a pixel value of 1
In the case of 0.5, if one pixel of an even line is set to 10 and one pixel of an odd line is set to 11, the average of two pixels appears to human eyes as 10.5. This means that when quantizing the pixels of the even lines, values smaller than the number of quantization bits are simply discarded. When quantizing the pixels of the odd lines, the values smaller than the number of quantization bits are rounded off (to a binary number). Means to round to zero when applied).

Further, in the interlaced image, even lines correspond to even fields, odd lines correspond to even fields, and even and odd fields are alternately transferred on the time axis. When quantizing the constituent pixels, values less than the number of quantization bits are truncated, and when quantizing the pixels forming the odd field, the values less than the quantization bits are rounded off, so that the interlaced image is dithered on the time axis. This means that the processing has been performed.

In this way, even if the image dithered on the time axis is enlarged, reduced, or deformed at the time of display, the image is processed in a two-dimensional space, but no processing is performed on the time axis. Since there is no dither pattern, the dither pattern is not enlarged.

Next, referring to FIG. 1, a normal dithering process is performed on the original picture to enlarge it by a factor of two, and a dithering process on the time axis according to the present invention is performed twice. This will be described in comparison with the case where the size is enlarged.

FIG. 1A shows two pixels of an original picture, the value of which is 10.5. FIG. 1B shows the dithering of the two pixels shown in FIG. The values after processing are shown, and their values are 10 and 11. When the dithered image is displayed after being subjected to a normal enlargement process, the image becomes as shown in FIG. 9C. The image after dithering is displayed by being enlarged twice in units of one pixel. Has become. On the other hand, when the image is displayed after being subjected to the enlargement processing of the present invention, the result is as shown in FIG. 11D. Becomes Therefore,
When performing the dithering process on the time axis of the present invention,
Even if the original picture is enlarged and displayed, the dither pattern is not enlarged and becomes like a mosaic pattern. Similarly, when the original picture is reduced or deformed, the dithering effect is not canceled out or overemphasized. Although the above description has been made with respect to a black-and-white image, a RGB color image is used for a color image.
By processing each of them in the same way, the same processing as for a black and white image can be performed.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of an image reproducing apparatus using the interlaced image processing method of the present invention.

The image reproducing apparatus according to the present embodiment includes a sync separation unit 10, a field identification unit 12, a capture control unit 14
, An RGB decoder 16, an A / D converter 18, an image quality improvement processor 20, an image memory 22, and a palette memory 2.
4, a palette reference unit 26, a display memory 28, a drawing controller 30, a display controller 32, a D / A
It comprises a conversion unit 34 and a display device 36.

In this embodiment, an interlaced image signal such as a TV signal from a television, a VTR signal from a video camera, and a VDR signal from a laser disk is used as an input image signal. Hereinafter, these signals are collectively referred to as analog video signals.

The sync separation section 10 separates an input analog video signal into a video signal and a sync signal. The field identification unit 12 identifies whether the analog video signal is a signal of an even field or a signal of an odd field, and outputs the result as a field signal. The RGB decoder 16 separates the analog video signal into R (red), G (green), and B (blue) signals. A
The / D converter 18 quantizes the analog RGB signal and converts it into a digital RGB signal. The capture control unit 14
Synchronization signal from sync separation section 10 and field identification section 1
Image quality improvement processing unit 2 based on the field signal from
0, the digital R of each field is stored in the image memory 22.
Stores a GB signal. These digital RGB signals become image signals of the original picture at the time of color conversion.

The image quality improvement processing section 20 performs a dithering process on a time axis, which is a feature of the present invention. That is, the image quality improvement processing unit 20 captures the digital RGB signals based on the signal from the capture control unit 14 and, if the field to be processed is an even field, discards a value equal to or less than a predetermined quantization bit number. Do
If the field is an odd field, a process of rounding off a predetermined number of quantization bits or less is performed. These processes will be described later in detail.

The image memory 22 stores digital RGB signals (hereinafter also referred to as color number data) after the image quality improvement processing in a continuous area. The palette memory 24 has a table for converting color number data into actual color data.
Store the data. The palette memory 24 has a data width of 8 bits and a full-color color set (256 colors) corresponding to the number of colors per pixel of the image memory 22.
Color). In the present embodiment, the palette memory 24 includes a plurality of color sets, and the image memory 22
Any one of the color sets is selected according to the original picture stored in. The palette reference unit 26 converts the color number data from the image memory 22 into an address, extracts the corresponding color data from the palette memory 24 using the address, and outputs the color data to the display memory 28. The display memory 28 has a continuous area for each field and stores a signal of each field.

The drawing controller 30 includes a CP (not shown).
In accordance with an instruction from the U or the like, the palette reference unit 26 is instructed which color set of the palette memory 24 is to be used, and the designated palette memory 24 is referred to, so that the original picture stored in the image memory 22 is referred to. Is converted to color and written into the display memory 28. Further, the drawing controller 30 also performs processing for enlarging, reducing, and deforming the image. For example, a process of reducing the image by skipping the read address, or enlarging the image by redundantly reading the same portion of the read address is performed. Further, the drawing controller 3
0 controls the display memory 28 based on the synchronization signal,
The data in the even field is output as data in the even field, and the data in the odd field is output as data in the odd field.

The display controller 32 includes a display memory 28
When outputting data from the display device, it controls which field of the even field or the odd field is to be read, and controls the timing of extracting a signal from the display memory in accordance with the characteristics of the display device. Also,
The display controller 32 sends a synchronization signal to the display device 36. The D / A converter 34 converts a digital signal from the display memory 28 into an analog signal and outputs the analog signal to the display device 36. The display device 36 displays an analog signal from the D / A converter 34 on the screen based on the synchronization signal.

Next, the dithering processing on the time axis in the image quality improvement processing section 20 will be described in detail. The image quality improvement processing unit 20 performs digital RGB data after A / D conversion, for example, digital RiG data having a quantization bit number of 5 bits.
When iBi data is input, in this embodiment, since one pixel of the image memory is 8 bits, if the input digital RiGiBi data is of an even field, Rm [2: 0] <= Ri [4: 2] Gm [2: 0] <= Gi [4: 2] Bm [1: 0] <= Bi [4: 3] (Here, name indicates a part of data (bus). [ms
b: lsb]. This is the data of name
It indicates bits from the lsb bit (the least significant bit is 0) to the msb bit. ). In this processing, for the R (red) and G (green) data of each color, the lower 2 bits (0th bit and 1st bit) of 5 bits are discarded, and the upper 3 bits, that is, from the second bit, Up to the 4th bit is newly changed from the 0th bit to the 2nd bit.
For the (blue) signal, the lower 3 bits (0th bit to 2nd bit) of the 5 bits are truncated, and the upper 2 bits, that is, the 3rd and 4th bits are newly added to the 0th bit and the 1st bit. Is what you do.

When the input digital RiGiBi signal is of an odd field, Rm [2: 0] <= Ri [4: 2] ++ Ri [1] Gm [2: 0] <= Gi [4: 2] ++ Gi [1] Bm [1: 0] <= Bi [4: 3] ++ Bi [2] This processing is performed for each of the colors R
(Red) and G (green) data out of 5 bits
The lower 2 bits (0th bit and 1st bit) are discarded, and the upper 3 bits, that is, the 2nd to 4th bits are newly changed from the 0th bit to the 2nd bit, and the value of the bit to be discarded to this value In the present embodiment, rounding is performed by adding the value of the first bit. Similarly, in the case of the B (blue) signal, the lower 3 bits (from the 0th bit to the 2nd bit) are discarded and the upper 2 bits are removed.
Bits, that is, the third and fourth bits are newly
The rounding process is performed by adding the value of the bit to be truncated, that is, the value of the second bit in this embodiment, to the first bit and the first bit. The sign of “++” is
It is assumed that this addition process performs an overclip process described later.

FIG. 3 is a circuit diagram showing an example of the image quality improvement processing section. The image quality improvement processing unit 20 includes an R signal processing unit 201, a G signal processing unit 202, and a B signal processing unit 203.
However, since the processing contents of each signal processing unit are substantially the same, the R signal processing unit 201 will be described below,
The description of the G signal processing unit 202 and the B signal processing unit 203 will be omitted.

As shown in the figure, the R signal processing unit 201 of the image quality improvement processing unit 20 includes an AND circuit 40 and an adder 42.
And an overclip circuit 44. The AND circuit 40 calculates the logical product of the value of the field signal and the value of the first bit of the digital R signal, and outputs the result to the adder 42. The adder 42 calculates the 5 of the input digital R signal.
The value of the upper three bits of the bits is added to the value sent from AND circuit 40, and the result is output. At this time, the adder 42 outputs a carry signal (cy signal) when the output value becomes “1000” due to carry as a result of the addition. The overclip circuit 44 performs overclip processing and includes three OR circuits. One of the output signals of the adder 42 and the cy signal are added to the input of each OR circuit.

Next, the operation of the R signal processing unit 201 will be described. When 5-bit digital R data is input,
If this input signal is for an even field, for example,
Assuming that the field signal is "0", the lower 2 bits are discarded and the value of the upper 3 bits is output as it is. On the other hand, if the input signal is for an odd field,
Since the field signal is "1", the value of the first lower bit is rounded off, and the value is added to the value of the upper three bits and output. As a result of the addition, when the output value becomes 4-bit “1000” due to a carry, the adder 4
2 outputs a cy signal "1". When receiving the cy signal, the overclip circuit 44 performs an overclip process. That is, the overclip circuit 44 sets c
Upon receiving the y signal, the output value is forcibly output as 3-bit "111". When the cy signal is not received, the overclip circuit 44 outputs
2 is output as it is. The processing for the even field and the odd field may be reversed.

Next, the operation of the image reproducing apparatus according to this embodiment will be described.

The input analog video signal is separated into a video signal and a synchronization signal by a synchronization separation unit 10, the synchronization signal is sent to a capture control unit 14, and the video signal is sent to a field identification unit 12. The field identification unit identifies whether the video signal is of an even field or an odd field, and sends the result to the capture control unit 14.

On the other hand, the analog video signal captured by the RGB decoder 16 is separated into color signals for each field and sent to the A / D converter 18. Analog RGB
The A / D converter 18 converts the analog RGB signal
The GB is converted into a 5-bit digital signal and sent to the image quality improvement processing unit 20. If the input 5-bit, 5-bit, and 5-bit RGB signals are of even-numbered fields based on the signal from the capture control unit 14, the image enhancement processing unit 20 determines that each of the lower 2 bits of the RG signal is Is rounded down, R is 3 bits and G is 3 bits of data, and for the B signal, the lower 3 bits are rounded down and output as 2 bits of data. On the other hand, RG
If the B signal is for an odd field, the RG signal is rounded off from the second lower bit and output as 3-bit data, and the B signal is rounded off from the lower third bit to 2 bits. Output as bit data. The input 5 bits, 5 bits,
The 5-bit RGB signal is stored in the image memory 22 as a 3-bit, 3-bit, 2-bit, 8-bit data. The drawing controller 30 is a CPU (not shown)
Based on instructions from the above, the signal (original picture) stored in the image memory 22 is subjected to enlargement, reduction, or deformation processing and stored in the display memory 28. At this time, the signal of the image memory 22 is converted into a color signal to be actually displayed by the palette reference section 26 and stored in the display memory 28. The digital signal stored in the display memory 28 is converted from a digital signal into an analog signal under the control of the display controller 32, sent to a display device 36 together with a synchronization signal, and displayed on a screen.

When the input image is enlarged, reduced or deformed, the drawing controller 30 controls these processes. That is, for example, when reducing an image, the image is reduced by setting every other read address, and the image is enlarged by reading the same portion of the read address redundantly. At this time, in the present embodiment, when enlarging as described above, FIG.
One unit consisting of two pixels shown in (b) is doubled as a unit, that is, one unit of one pixel of an even field and one pixel of an odd field adjacent in the sub-scanning direction is used as a unit. Enlarge and display. By performing such enlargement processing, it is possible to prevent the dither pattern generated by the conventional enlargement processing from being enlarged and becoming a mosaic pattern.

Also, when the image is reduced or deformed, the dithering process is performed separately on the even field and the odd field, so that the deterioration of the image quality can be suppressed as in the case of enlargement. . Other points of the reduction processing and the deformation processing according to the present embodiment are substantially the same as those of the conventional processing method, and thus detailed description of these processing is omitted.

As described above, according to the above-described embodiment, the quantized data of the even field is truncated to a value equal to or less than a predetermined number of quantized bits, and the quantized data of the odd field is quantized. Since the dithering process is performed by rounding off a value equal to or less than a predetermined quantization bit number for the data of (i), the image quality of the output image is improved even when there is a restriction on color display such as a game machine. be able to. For example, even if a palette that can display only 256 colors is used because the bit width of the image memory is 8 bits, R is 3 bits and G is
R is 4 bits, G is 4 bits, and B is 3 bits, which is an image with 3 bits and B2 bits, up to a maximum of 1 bit. One bit of information is added to each color. An effect approximately equivalent to the above is obtained. As a result, the output image can be made closer to a natural image.

Further, according to the present embodiment, the value of the predetermined number of quantization bits or less is cut off for the signal of the even field, and the value of the predetermined number of quantization bits or less is rounded off for the signal of the odd field. Since dithering processing is performed, even when the input image is enlarged, reduced or deformed, the dithering effect is canceled or
It is possible to prevent the image quality from being deteriorated due to excessive emphasis.

It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist. For example, in the above-described embodiment, the capture control unit 14 and the drawing controller 32 are separately provided as hardware. However, the present invention
The present invention is not limited to this, and these control functions may be provided in a single control unit. In the above-described embodiment, the image memory 22, the palette memory 24, and the display memory 32 are separately provided as hardware. However, the present invention is not limited to this, and these may be provided on a single memory.

In the above embodiment, the case where the input signal is an analog video signal has been described. However, the present invention is not limited to this. If the input signal is an interlaced image, analog RGB It may be a separate signal, a digital RGB separate signal, or a digital video signal. When the input image signal is a digital video signal, a digital sync separation unit and a field identification unit are provided. The field signal is generated by the field identification unit and sent to the capture control unit. The RGB separate signal is input to the image quality improvement processing unit. Is done.

Further, in the above embodiment, the bit width of the image memory is 8 bits, but the present invention is not limited to this, and may be, for example, 16 bits or 24 bits. In the present embodiment, 8 bits of the color number data are 3 bits for R, 3 bits for G, and 2 bits for B. This is because even if the information of B (blue) is smaller than that of R (red) and G (green), a color close to the original color can be reproduced when seen by human eyes. Therefore, depending on the specific circumstances, the 8 bits of the color data are, for example, 2 bits for R, 3 bits for G, 3 bits for B, or R for 3 bits.
Can be 3 bits, G is 2 bits, and B is 3 bits.

Further, according to the present invention, a program for realizing the functions of the above-described embodiments may be stored in a storage medium, and the program stored in the storage medium may be read out and executed using a computer. As a storage medium, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, or the like can be used.

[0042]

As described above, according to the present invention, one of the quantized data of the even field and the quantized data of the odd field is equal to or less than a predetermined number of quantization bits. By truncating the value and using the signal obtained by rounding off the value equal to or smaller than the predetermined quantization bit number for the other, it is possible to improve the image quality, and to enlarge, reduce, or deform the original picture. In addition, it is possible to provide an interlaced image processing method, an interlaced image processing device, and a computer-readable storage medium capable of suppressing a decrease in image quality.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention,
(A) shows two pixels of the original picture, (b) shows the result of dithering the two pixels shown in (a), and FIG. (C) shows the result of normal enlargement processing. (D) shows what is displayed after performing the enlargement processing of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an image reproducing apparatus using an interlaced image processing method according to the present invention.

FIG. 3 is a circuit diagram illustrating an example of an image quality improvement processing unit.

[Description of Signs] 10 Synchronization separation unit 12 Field identification unit 14 Capture control unit 16 RGB decoder 18 A / D conversion unit 20 Image quality improvement processing unit 22 Image memory 24 Palette memory 26 Palette reference unit 28 Display memory 30 Drawing controller 32 Display controller 34 D / A conversion unit 36 Display device

Claims (4)

[Claims] 1. An interlace image processing for quantizing an interlaced image constituting one frame by an even field and an odd field for each field, storing the quantized image in an image memory, and outputting an interlaced image from an original picture stored in the image memory. In the method, any one of the quantized data of the even field and the quantized data of the odd field is truncated to a value less than a predetermined number of quantization bits, and the other is a predetermined value. An interlaced image processing method, wherein a value equal to or smaller than a predetermined number of quantization bits is rounded and stored in the image memory. 2. The method according to claim 1, wherein the interlaced image is a color image, and the image memory has an 8-bit width per pixel.
2. The interlaced image according to claim 1, wherein the signal of each field stored in the image memory is 3 bits for R (red), 3 bits for G (green), and 2 bits for B (blue). Processing method. 3. A / D conversion means for performing an analog-to-digital conversion of an interlaced image constituting one frame by an even-numbered field and an odd-numbered field for each field; Image quality improvement processing means for truncating a value equal to or less than a predetermined quantization bit number for one of the data and rounding off a value equal to or less than a predetermined quantization bit number for the other, An interlaced image processing apparatus, comprising: image storage means for storing output data from the image quality improvement processing means for each field. 4. The interlaced image is a color image, the image storage means has one pixel having an 8-bit width, and the signal of each field stored in the image storage means has R (red) of 3 bits, G (Green) is 3 bits, B
4. The interlace image processing device according to claim 3, wherein (blue) is 2 bits.