JP2000163993A - Circuit and method for testing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which has a memory circuit part inside and reduces the proportion of a test circuit. SOLUTION: A BIST circuit 5 comprises an address and access signal generating means 2, a data generating means 3, a memory circuit part maximum address storage means 6, an address deciding means 7, address and access signal control means 81 and 82, refresh generating means 91 and 92, data comparison signal control means 43 and 44, and comparing means 41 and 42 which are as many as memory circuit parts and a single BIST control means 1. With plural test circuits which number as many as the memory circuits need not be provided independently and redundant test circuits, when memory circuit parts are incorporated, can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device test circuit and a semiconductor memory device test method.

[0002]

2. Description of the Related Art In recent years, in electronic equipment using a semiconductor integrated circuit device, a semiconductor manufacturing process has been miniaturized, and a plurality of systems are mixedly mounted on one chip to develop a large-scale and highly integrated semiconductor integrated circuit device. Is becoming possible. Among them, a semiconductor device having a plurality of large-capacity, multi-bit-width memory circuits for realizing high functionality is realized by increasing the read / write data width to multiple bits and improving the data transfer rate inside the semiconductor integrated circuit device. Integrated devices have been developed.

However, when testing a semiconductor integrated device having a plurality of large-capacity and multi-bit-width memory circuits, a method of directly accessing the memory circuit from the outside and performing the test is considered. Allocating all the width data bits to the external terminals limits the number of terminals of the semiconductor integrated circuit device, and it is difficult to design specifications and layout. Further, since a large number of data comparators of the memory inspection device are required, the memory inspection device becomes expensive and the inspection cost increases.

For this reason, in recent years, as an inspection means for solving these problems, a test address is added at the time of inspection to divide multi-bit width data into small bit widths, and external access is possible directly with a small bit width. A means for providing a test circuit and an inspection algorithm for performing an inspection by directly accessing from the outside are implemented as a test circuit, built in the semiconductor device, a memory circuit inspection is performed inside the semiconductor memory device, and the inspection result is output to the outside. BIST (Bu
ilt In Self Test) means are employed.

FIG. 14 shows a configuration of a conventional test circuit of a semiconductor integrated circuit device incorporating two memory circuits having different configurations of data bit width and address bit width. In FIG. 14, the semiconductor integrated circuit device includes a memory circuit unit 203, a self-test circuit unit (hereinafter, referred to as a BIST (Built In Self Test) circuit unit) 201 that performs an inspection of the memory circuit 203, a memory circuit unit 204. And a BIST circuit unit 202 for inspecting the memory circuit unit 204.

The memory circuit section 203 includes a memory circuit 121
, An address access signal multiplex 211,
During normal operation (BIST1 enable signal a is disabled)
, The address access signal multiplex 211 selects the normal address access signal input b, the data multiplex 131 selects the normal data input c and the normal data output d, and accesses the memory circuit 121 and data It allows reading and writing.

When the BIST1 enable signal a is enabled, the address access signal multiplex 211 and the data multiplex 131 select the address access signal e and the data input / output f, g connected to the BIST circuit section 201. , BIST circuit unit 201 can read and write data.

The BIST circuit section 201 comprises an address / access signal generation circuit 21, a comparison circuit 41, a data generation circuit 31, and a BIST control circuit 14,
When the ST enable signal is enabled, the BIST control circuit 14 controls the address / access signal generation circuit 21, the data generation circuit 31, and the comparison circuit 41 in accordance with a built-in inspection algorithm, and performs reading / writing to the memory circuit unit 203. . During a write operation, the address / access signal generation circuit 21 generates an address for writing data to the memory circuit unit 203 and a write access signal, the data generation circuit 31 generates data to be written to the memory circuit unit 203, and the comparison circuit 41 It is enabled. At the time of a read operation, the address / access signal generation circuit 21 generates an address for reading data from the memory circuit unit 203 and a read access signal, the data generation circuit 31 generates expected value data read from the memory circuit unit 203, and a comparison circuit. Reference numeral 41 compares the expected value data generated by the data generation circuit 31 with the data read from the memory circuit unit 203 and returns the comparison result to the BIST control circuit 14. The BIST control circuit 14 , The presence or absence of an error in the inspection result is output to the outside as a first BIST result i.

The memory circuit section 204 includes a memory circuit 122
An address access signal multiplex 212;
A data multiplex 132, the configuration of the data bit width and the address bit width of the memory circuit 122 is different from that of the memory circuit 121 of the memory circuit section 203, and the address bit width of the address access signal multiplex 212 is 203 and the data bit width of the data multiplex 132 is different from that of the memory circuit unit 2.
03 is different from the data multiplex 131, the switching signal between the address access signal multiplex 212 and the data multiplex 132 is a BIST2 enable signal, and the address access signal and the data input / output are B when the BIST2 enable signal is enabled.
Except for being connected to the IST circuit unit 202, the same operation as that of the memory circuit unit 203 is performed.

The BIST circuit section 202 includes an address / access signal generation circuit 22, a comparison circuit 42, a data generation circuit 32, and a BIST control circuit 15. The address / bit signal width of the address / access signal generation circuit 22 is B.
The address bit width of the address / access signal generation circuit 21 of the IST circuit section 201 is different from that of the address bit width of the comparison circuit 41 and the data bit width of the data generation circuit 31 of the BIST circuit section 201. That the enable signal of the BIST control circuit 15 is a BIST2 enable signal, and that the address access signal and the data input / output are
4, except that it is connected to the test circuit 201.

In the conventional example configured as described above,
Since the BIST circuit units 201 and 202 for inspecting the memory circuit units are provided in the memory circuit units 203 and 204, respectively, the inspection can be performed independently regardless of the address and data bit width configuration of the memory circuit.

[0012]

However, in a conventional test circuit of a semiconductor integrated circuit device having a plurality of memory circuits, since a plurality of memory circuit sections are built in, the same number of BIST circuit sections as the built-in memory circuit sections are provided. Therefore, the ratio of the test circuit in the semiconductor integrated circuit device increases.

An object of the present invention is to reduce redundant test circuits when a plurality of memory circuits are incorporated and to provide a test method therefor.

[0014]

The test circuit of the present invention comprises:
In a semiconductor integrated circuit in which a single BIST circuit section and a plurality of memory circuit sections are formed on the same chip,
A circuit unit, a single address and access signal generating means for generating a maximum address and an access signal of the plurality of memory circuit units for inspection of the plurality of memory circuit units;
A single data generating means for generating test data having a maximum data bit width of the plurality of memory circuit units for testing the plurality of memory circuit units, and storing a maximum address value for each of the plurality of memory circuit units A single memory circuit unit maximum address storage unit, and that the address generated by the address and access signal generation unit is equal to or greater than an address set by the memory circuit unit maximum address storage unit for each of the plurality of memory circuit units. A single address discriminating means for generating the same number of refresh operation signals as the plurality of memory circuit units, and the plurality of refresh operation signals generated by the address discriminating means are generated by the address and access signal generating means. The plurality of memory circuits for disabling addresses and accesses Address and access signal control means of the same number as the plurality of memory circuit units for generating a refresh signal in response to the plurality of refresh operation signals generated by the address determination means; The same number of data comparison signal control units as the plurality of memory circuit units for disabling the read data comparison signals of the plurality of memory circuit units by the plurality of refresh operation signals, and propagation from the plurality of data comparison signal control units. The same number of comparing means as the plurality of memory circuit units for comparing each of the data generated by the data generating means with the read data comparison signal and the data read from the plurality of memory circuit units; The address and access signal generating means according to And controlling the data generation means and the plurality of data comparison signal control means to inspect the plurality of memory circuit parts, and output the presence or absence of an error in the plurality of memory circuit parts based on a comparison result returned by the plurality of comparison means. And a single BIST control means.

Further, the test method of the present invention is characterized in that the BIS
In a test method for a semiconductor integrated circuit in which a T circuit unit and the plurality of memory circuit units are formed on the same chip, when writing data to all memory regions of the plurality of memory circuit units, the plurality of address and access signals and A data input is generated in the BIST circuit portion, and the data input is simultaneously written in parallel to the memory cells of the plurality of memory circuit portions to be subjected to the write test. It is independently determined for each of the plurality of memory circuit units whether the address value to be attempted is equal to or greater than a maximum address, and when the address value is equal to or greater than the maximum address, the addresses and access signals of the plurality of memory circuit units are independently held, and A refresh signal is generated in place of the writing stage to independently refresh the memory circuit section. A step that, after completion of the step of the write and refresh, the step of changing an address and access signals and data input of a plurality of memory circuit unit, and repeating until the maximum address of the plurality of memory circuit sections.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a semiconductor integrated circuit in which a single BIST (Built In Self Test) circuit section and a plurality of memory circuit sections are formed on the same chip. The circuit unit includes a single address and access signal generating unit that generates a maximum address and an access signal of the plurality of memory circuit units for testing the plurality of memory circuit units, and a circuit for testing the plurality of memory circuit units. A single data generating means for generating test data having a maximum data bit width of the plurality of memory circuit sections, and a single memory circuit section maximum address storage means for storing a maximum address value for each of the plurality of memory circuit sections And the address generated by the address and access signal generating means is equal to or smaller than the address set by the memory circuit section maximum address storing means. And a plurality of refresh operation signals generated by the plurality of memory circuit units and generating the same number of refresh operation signals as the plurality of memory circuit units. The same number of address and access signal control means as the plurality of memory circuit units for disabling the address and access generated by the address and access signal generation means, and the plurality of refresh operation signals generated by the address determination means Refreshing means for generating the same refresh signal as the plurality of memory circuit units; and disabling the read data comparison signals of the plurality of memory circuit units by the plurality of refresh operation signals generated by the address determining means. Multiple notes The same number of data comparison signal control units as the circuit units, and the data generated by the data generation unit and read out from the plurality of memory circuit units by the read data comparison signal propagated from the plurality of data comparison signal control units. Controlling the address and access signal generating means, the data generating means, and the plurality of data comparing signal controlling means in accordance with a check algorithm, by controlling the plurality of memory circuit sections for performing the comparison for each data; And a single BIST control unit for inspecting the memory circuit unit and outputting the presence / absence of an error in the plurality of memory circuit units based on the comparison result returned by the plurality of comparison units.

According to a second aspect of the present invention, in a semiconductor integrated circuit in which a single BIST circuit section and a plurality of memory circuit sections are formed on the same chip, the BIST circuit section includes the plurality of memory circuit sections. A single address and access signal generating means for generating a maximum address and an access signal of the plurality of memory circuits for the inspection of the memory, and disabling the generation of the address and the access signal at the time of the pause inspection of the plurality of memory circuits. A single data generating means for generating test data having a maximum data bit width of the plurality of memory circuit units for testing the plurality of memory circuit units, and storing a maximum address value for each of the plurality of memory circuit units A single memory circuit unit having a maximum address storage means to be stored, and an address generated by the address and access signal generation means. A single address discriminating means for discriminating, for each of the plurality of memory circuit portions, that the address is equal to or greater than the address set by the memory circuit portion maximum address storage means, and generating the same number of refresh operation signals as the plurality of memory circuit portions; A plurality of refresh operation signal control units as many as the plurality of memory circuit units that do not propagate the plurality of refresh operation signals generated by the address determination unit during a pause test of the plurality of memory circuit units;
The same number of addresses and accesses as in the plurality of memory circuit units for disabling the addresses and accesses generated by the address and access signal generation means by the plurality of refresh operation signals transmitted from the plurality of refresh operation signal control means. Signal control means, the same number of refresh generation means as the plurality of memory circuit units for generating refresh signals based on the plurality of refresh operation signals transmitted from the plurality of refresh operation signal control means, and the plurality of refresh operation signal controls Means for disabling read data comparison signals of the plurality of memory circuit units by the plurality of refresh operation signals propagated from the means, the same number of data comparison signal control units as the plurality of memory circuit units, and the plurality of data comparison signals Transfer from the control means The same number of comparing means as the plurality of memory circuit units for comparing each of the data generated by the data generating means with the read data comparison signal and the data read from the plurality of memory circuit units; Controlling the address and access signal generation means, the data generation means, the plurality of data comparison signal control means, and the plurality of refresh operation signal control means in response to the plurality of memory circuit sections, A test circuit for a semiconductor integrated circuit device incorporating a plurality of memory circuits, comprising a single BIST control means for outputting the presence / absence of an error in the plurality of memory circuit units based on the comparison result returned by (1).

The invention according to claim 3 of the present invention is characterized in that the single address and access signal generating means can generate more than the maximum address of the plurality of memory circuit units. 4 is a test circuit of a semiconductor integrated circuit device having a built-in memory circuit.

The invention according to claim 4 of the present invention is characterized in that the plurality of memory circuit sections are embedded DRAM (embedded-DEAM), and the semiconductor integrated circuit having a built-in plurality of memory circuits according to claim 1 to 3 is provided. It is a test circuit of a circuit device.

The invention according to claim 5 of the present invention is characterized in that
In a method for testing a semiconductor integrated circuit in which an IST circuit unit and the plurality of memory circuit units are formed on the same chip, when writing data to all memory regions of the plurality of memory circuit units, the plurality of address and access signals and A data input is generated in the BIST circuit portion, and the data input is simultaneously written in parallel to the memory cells of the plurality of memory circuit portions to be subjected to the write test. It is independently determined for each of the plurality of memory circuit units whether the address value to be attempted is equal to or greater than a maximum address, and when the address value is equal to or greater than the maximum address, the addresses and access signals of the plurality of memory circuit units are independently held, and A refresh signal is generated in place of the writing stage to independently refresh the memory circuit section. And changing the address, the access signal, and the data input of the plurality of memory circuit units after completing the writing and refreshing steps, up to the maximum address of the plurality of memory circuit units. A test method for a semiconductor integrated circuit device having a plurality of memory circuits according to claim 1.

[0021] The invention described in claim 6 of the present invention is characterized in that:
In a method for testing a semiconductor integrated circuit in which an IST circuit section and the plurality of memory circuit sections are formed on the same chip, when reading data in an entire memory area from the plurality of memory circuit sections, an address of the plurality of memory circuit sections may be read. Generating an access signal and expected read value data in the BIST circuit unit, and simultaneously reading data in parallel from memory cells of the plurality of memory circuit units to be read-checked; Independently comparing the data read from the unit and the read expected value data for each of the plurality of memory circuit units;
In the reading step, it is independently determined for each of the plurality of memory circuit units whether an address value to be read-tested to the plurality of memory circuit units is equal to or larger than a maximum address,
When the number is equal to or greater than the maximum address, the addresses and access signals of the plurality of memory circuit units are independently held, a refresh signal is generated to refresh the memory circuit units independently, and the read data and the read data are read in the comparing step. Returning a match result to the BIST circuit unit without comparing expected value data, and, after completing the comparing and refreshing step, changing address and access signals and read expected value data of the plurality of memory circuit units. 5. The test method for a semiconductor integrated circuit device having a plurality of memory circuits according to claim 1, wherein the test is repeated up to the maximum address of the plurality of memory circuit units.

The invention according to claim 7 of the present invention is characterized in that:
In a test method for a semiconductor integrated circuit in which an IST circuit section and the plurality of memory circuit sections are formed on the same chip, when reading and writing data continuously in all memory areas of the plurality of memory circuit sections, the plurality of memory circuits The address, access signal and read expected value data of the
Reading data from the memory cells of the plurality of memory circuit units to be read and inspected in parallel at the same time in the ST circuit unit; and reading the data read from the plurality of memory circuit units in the reading step and the read operation. A step of independently comparing expected value data for each of the plurality of memory circuit units; and a step of reading the plurality of memory circuit units in the reading step to determine whether an address value to be read and checked is greater than or equal to a maximum address. It is determined independently for each circuit unit, and when it is equal to or more than the maximum address, the addresses and access signals of the plurality of memory circuit units are held independently, a refresh signal is generated to refresh the memory circuit unit independently, and In the comparing step, the read result is not compared with the read expected value data, and Returning to the path section, generating the address, access signal and data input of the plurality of memory circuit sections in the BIST circuit section, and parallelizing the data input to the memory cells of the plurality of memory circuit sections to be subjected to write inspection. In the writing step at the same time, it is independently determined for each of the plurality of memory circuit units whether the address value to be written to the plurality of memory circuit units in the writing step is equal to or larger than the maximum address. In some cases, independently holding addresses and access signals of the plurality of memory circuit units, generating a refresh signal in place of the writing stage to independently refresh the memory circuit unit, and after completing the writing stage, Changing addresses, access signals, and expected read value data of a plurality of memory circuit units Floor to a plurality memory circuit built-in test method of a semiconductor integrated circuit device of claim 1, wherein a repeated until the maximum address of the plurality of memory circuit sections.

The invention according to claim 8 of the present invention is characterized in that
In a test method for a semiconductor integrated circuit in which an IST circuit section and the plurality of memory circuit sections are formed on the same chip, an address, an access signal, and a refresh signal are transmitted to the plurality of memories by a pause signal generated in the BIST circuit section. 3. The test method for a semiconductor integrated circuit device having a plurality of memory circuits therein according to claim 2, wherein said plurality of memory circuit units are simultaneously set in a pause state without being generated in a circuit unit.

According to a ninth aspect of the present invention, the method of
In a test method for a semiconductor integrated circuit in which an IST circuit section and the plurality of memory circuit sections are formed on the same chip, a state where an address value generated in the BIST circuit section is larger than a maximum address of the plurality of memory circuit sections. 5. The method according to claim 1, wherein said plurality of memory circuit units are simultaneously refreshed.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. Embodiment 1 FIG. 1 shows a test circuit of a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to an embodiment of the present invention.

In FIG. 1, reference numerals 161 and 162 denote two memory circuit units having different configurations of data bit width and address bit width, and reference numeral 5 denotes a single BIST circuit unit for inspecting the memory circuit units 161 and 162. An address, an access signal, and a refresh signal each having a unique bit width are independently connected from the BIST circuit unit 5 to the memory circuit units 161 and 162, and test data generated by the BIST circuit unit 5 is stored in the memory circuit units 161 and 162. 162 to the memory circuit unit 1
Data read from 61 and 162 are independently connected to the BIST circuit section 5 with data output lines with a unique bit width.

In the memory circuit section 161, 121 is a memory circuit, 111 is an address access signal multiplex, and 131 is a data multiplex. When the address access signal multiplex 111 is a BIST enable, a refresh signal is sent to the memory circuit 121.
The configuration and operation are the same as those of the conventional example except that the propagation is added.

In the memory circuit section 162, 122 is a memory circuit, 112 is an address / access signal multiplex, 132 is a data multiplex, and the data bit width and the address bit width are the same as those of the memory circuit section 1.
The configuration and operation are the same as those of the memory circuit unit 161 except that the memory circuit unit 161 is different from the memory circuit unit 161.

The BIST circuit section 5 comprises the following components. Reference numeral 2 denotes an address access signal generating circuit having an address bit width capable of generating a larger address value among the maximum address values of the memory circuit units 161 and 162. To generate the same address and access signal.

Reference numeral 3 denotes a data generation circuit which can generate a larger data bit width in the memory circuit units 161 and 162, and generates the same test data to the memory circuit units 161 and 162.

Reference numeral 6 denotes a memory circuit section maximum address storage circuit which stores the maximum address values of the memory circuit sections 161 and 162, respectively. Reference numeral 7 denotes an address discriminating circuit for discriminating, for each of the memory circuit portions 161, 162, that the address generated by the address / access signal generating circuit 2 is equal to or greater than the address set by the memory circuit portion maximum address storage circuit 6. The memory circuit unit 161,
162 are generated independently.

Reference numeral 81 denotes an address / access signal control circuit of the memory circuit section 161. An address generated by the address / access signal generation circuit 2 based on a refresh operation signal of the memory circuit section 161 generated by the address discrimination circuit 7. And the access signal is disabled.

Reference numeral 82 denotes an address access signal control circuit of the memory circuit section 162, which is an address generated by the address access signal generation circuit 2 based on a refresh operation signal of the memory circuit section 162 generated by the address discrimination circuit 7. And the access signal is disabled.

A refresh generation circuit 91 of the memory circuit section 161 generates a refresh signal of the memory circuit section 161 in accordance with a refresh operation signal of the memory circuit section 161 generated by the address discriminating circuit 7.

Reference numeral 92 denotes a refresh generation circuit of the memory circuit section 162, which generates a refresh signal of the memory circuit section 162 according to a refresh operation signal of the memory circuit section 162 generated by the address discriminating circuit 7.

Numeral 41 denotes a comparison circuit which reads data from the memory circuit section 161 and a data generation circuit 3 when enabled.
Are compared, the result is output, and the match result is output when disabled.

Numeral 42 denotes a comparison circuit which reads data from the memory circuit section 162 and a data generation circuit 3 when enabled.
Are compared, the result is output, and the match result is output when disabled.

Reference numeral 43 denotes a data comparison signal control circuit of the memory circuit section 161 which disables the comparison circuit 41 of the memory circuit section 161 by a refresh operation signal of the memory circuit section 161 generated by the address discriminating circuit 7. .

A data comparison signal control circuit 44 of the memory circuit section 162 disables the comparison circuit 42 of the memory circuit section 162 by a refresh operation signal of the memory circuit section 162 generated by the address discriminating circuit 7. .

Reference numeral 1 denotes a BIST control circuit, which corresponds to the address / access signal generation circuit 2, the data generation circuit 3, and the data comparison signal control circuit 4 according to a check algorithm.
The memory circuits 161 and 162 are controlled by controlling the memory circuits 161 and 162, and the presence or absence of an error in the memory circuits 161 and 162 is output based on the comparison result returned by the comparison circuits 41 and 42.

The operation of the maximum address storage circuit 6, the address discriminating circuit 7, the address / access signal control circuits 81 and 82, and the refresh generation circuits 91 and 92 in the memory circuit portion of FIG. 1 will be described with reference to the control flow shown in FIG. .

FIG. 2 shows a control flow of an address and an access signal at the time of read / write access to the memory circuit units 161 and 162, and is stored in the memory circuit unit maximum address storage circuit 6 at 300 in FIG. The maximum address value of the memory circuits 161 and 162 is always set in the address discriminating circuit 7, and the address value generated from the address / access signal generating circuit 2 is input to the address discriminating circuit 7 in 301.

First, the control flow of access to the memory circuit section 161 is as follows. The maximum address value of the memory circuit section 161 in which the address value generated by the address / access generation circuit 2 is set at 300 If it is larger, a refresh operation signal is generated from the address discrimination circuit 7, and the control flow of 306 is executed to
In step 6, the address / access control circuit 81 is disabled by the refresh operation signal, and the address / access signal is not propagated to the memory circuit unit 161.
At step 8, the refresh generation circuit 91 is enabled by the refresh operation signal, a refresh signal is generated in the memory circuit section 161 and access to the memory circuit section 161 is stopped to enter the refresh state. On the other hand, 302
If the address value generated by the address / access generation circuit 2 is smaller than the maximum address value of the memory circuit section 161 set at 300, the refresh operation signal is not generated from the address determination circuit 7. ,
At 304, the address / access control circuit 81 is enabled and propagates the address and access signal to the memory circuit section 161 and disables the refresh generation circuit 91 to generate data to the memory circuit section 161. Write and read access of the test data generated by the circuit 3 is performed.

The control flow of access to the memory circuit section 162 is as follows. The maximum address value of the memory circuit section 162 in which the address value generated by the address / access generation circuit 2 is set in the step 300 If it is larger, a refresh operation signal is generated from the address determination circuit 7 and the control flow of 307 is executed,
At 7, the address / access control circuit 82 is disabled by the refresh operation signal, and the address / access signal is not transmitted to the memory circuit unit 162.
At 9, the refresh generation circuit 92 is enabled by the refresh operation signal, a refresh signal is generated in the memory circuit section 162, and access to the memory circuit section 162 is stopped to bring the memory circuit section 162 into a refresh state.

On the other hand, at 303, the address value generated from the address / access
If the address value is smaller than the maximum address value of the memory circuit section 162 set in the above, the refresh operation signal is not generated from the address determination circuit 7 and the control flow of 305 is executed.
At 305, the address access control circuit 82 is enabled, propagates the address and access signal to the memory circuit section 162, disables the refresh generation circuit 92, and sends the test data generated by the data generation circuit 3 to the memory circuit section 162. Write and read access.

Since the control flow after 302 and 303 is controlled independently of the memory circuit units 161 and 162, unless the maximum address value of the memory circuit units 161 and 162 is exceeded, each of the memory circuit units 161 and 162 Read and write access to the memory circuits 161 and 162 with the same address and access signal generated by the address / access signal generation circuit 2
When the maximum address value is exceeded, the refresh states are independently set, and the data written in the memory circuit units 161 and 162 can be held.

Next, the operation of the data generation circuit 3, the data comparison signal control circuits 43 and 44, and the comparison circuits 41 and 42 of FIG. 1 will be described with reference to the control flow shown in FIG. FIG. 3 shows the BIS at the time of reading to the memory circuit units 161 and 162.
3 shows a control flow of the comparison circuits 41 and 42 of the T circuit section 5, and when a read access is made at 400 in FIG.
The data read from the memory circuit units 161 and 162 are input to the comparison circuits 41 and 42 according to the control flow shown in FIG.

First, the comparison control flow for the memory circuit unit 161 is based on the access control flow for the memory circuit unit 161 after 302 in FIG.
When the read access is made to the maximum address or more, a refresh operation signal is generated from the address discriminating circuit 7 to put the memory circuit section 161 into a refresh state, no data is read, and the data is generated from the BIST control circuit 1 at 401. The data comparison signal is disabled in the data comparison signal control circuit 43 by the refresh operation signal, the control flow of 405 is executed, and
At 05, the comparison circuit 41 is disabled, and returns a match result to the BIST control circuit 1 regardless of the expected value of the test data generated by the data generation circuit 3.

On the other hand, the memory circuit section 302 after 302 in FIG.
In the case where read access is performed below the maximum address of the memory circuit section 161 according to the access control flow for 61, a refresh operation signal is not generated from the address discriminating circuit 7, and read access is executed to the memory circuit section 161. At 401, the data comparison signal generated from the BIST control circuit 1 is enabled by the data comparison signal control circuit 43, and the control flow of item 403 is executed. The expected value of the test data generated by the generating circuit 3 is compared with the data read from the memory circuit unit 161, and the comparison result is returned to the BIST control circuit 1.

The comparison control flow for the memory circuit unit 162 is based on the access control flow for the memory circuit unit 162 after 303 in FIG.
When the read access is made to the maximum address or more, the refresh operation signal is generated from the address discriminating circuit 7, the memory circuit portion 162 is set in the refresh state, no data is read, and the data is generated from the BIST control circuit 1 at 402. The data comparison signal is disabled by the data comparison signal control circuit 44 according to the refresh operation signal, and the control flow of 406 is executed.
At 06, the comparison circuit 42 is disabled, and returns a match result to the BIST control circuit 1 irrespective of the expected value of the test data generated by the data generation circuit 3.

On the other hand, the memory circuit unit 1 after 303 in FIG.
If the read access is performed below the maximum address of the memory circuit unit 162 in accordance with the access control flow for the memory access unit 62, the refresh operation signal is not generated from the address discriminating circuit 7, and the read access is executed to the memory circuit unit 162. At 402, the data comparison signal generated from the BIST control circuit 1 is enabled by the data comparison signal control circuit 44, and the control flow of item 404 is executed. At 404, the comparison circuit 42 is enabled, and The expected value of the test data generated by the generating circuit 3 is compared with the data read from the memory circuit unit 162, and the comparison result is returned to the BIST control circuit 1.

Since the control flows 401 and 402 are controlled independently of the memory circuit units 161 and 162, the memory circuits 161 and 162 do not exceed the maximum address value of the memory circuit units 161 and 162. In response to the same address and access signal generated by the address / access signal generating circuit 2, each independent data read is compared with an expected value of test data generated by the data generating circuit and each independent comparing circuit Comparisons are made at 41 and 42, and the comparison result is returned to the BIST control circuit 1. When the comparison result exceeds the maximum address value of the memory circuit units 161 and 162, each of them becomes a refresh state independently, no data is read, and the comparison circuits 41 and 42 A BIST control circuit independently outputs a match result regardless of the expected value of the test data generated by the data generation circuit 3. Return to.

Here, the plurality of memory circuit units are mixed D
RAM (embedded-DEAM). This (Embodiment 1)
According to this, as a test circuit for inspecting a plurality of memory circuit units, a BIST control circuit, a data generation circuit, and an address / access signal generation circuit in the BIST circuit unit are provided, and the plurality of memory circuit units are provided as in the related art. Read and write operations, and an effective effect of greatly reducing the number of test circuits in the BIST circuit portion can be obtained.

(Embodiment 2) FIG. 4 shows (Embodiment 1).
Built-in multiple memory circuits incorporating two memory circuits having different configurations of data bit width and address bit width according to an embodiment of the present invention in which a function capable of simultaneously setting the memory circuit units 161 and 162 into a pause state is added to the embodiment. 1 shows a configuration of a test circuit of the semiconductor integrated circuit device.

In FIG. 4, reference numerals 161 and 162 denote two memory circuit units having different data bit widths and address bit width configurations, and 52 denotes the memory circuit units 161 and 162.
Is a single BIST circuit unit that performs the inspection described above, and has the same connection configuration as that of the first embodiment.

In the BIST circuit section 52, reference numeral 23 denotes an address / access signal generation circuit provided with a function of controlling generation of an address and an access signal in the address / access signal generation circuit 2 of the first embodiment; A refresh operation signal control circuit for controlling a refresh operation signal of the memory circuit section 161 generated from the address determination circuit 7 by the pause signal, and a refresh operation signal 152 for the memory circuit section 162 generated by the address determination circuit 7 by the pause signal 12 is a refresh operation signal control circuit for controlling the BIS of the first embodiment.
The T control circuit 1 comprises a BIST control circuit having a function of generating the pause signal capable of controlling the address / access signal generation circuit 23 and the refresh operation signal control circuits 151 and 152 during a pause test. I have.

Here, the data generation circuit 3, the maximum address storage circuit 6 in the memory circuit section, the address discriminating circuit 7, the address / access signal control circuits 81 and 82 in the memory circuit sections 161 and 162, and the refreshing of the memory circuit sections 161 and 162 are performed. Generating circuits 91 and 92, memory circuit units 161 and 162
Of the comparison circuits 41 and 42 and the data comparison signal control circuits 43 and 44 of the memory circuit units 161 and 162 (Embodiment 1)
Since it has the same function as described above, the description is omitted.

FIG. 5 is a control flow chart showing the read / write access operations of the maximum address storage circuit 6, the address determination circuit 7, the address / access signal control circuits 81 and 82, and the refresh generation circuits 91 and 92 in FIG. This will be described with reference to FIG.

FIG. 5 shows a control flow of an address and an access signal at the time of read / write access to the memory circuit units 161 and 162 controlled by the pause signal, and 300 to 309 show FIG. 2 of the first embodiment. Of 300
309, unless the BIST control circuit 12 generates a pause signal.
1 and the same operation as in the first embodiment is performed.

However, when a pause signal is generated from the BIST control circuit 12, the control flow from 601 to 602 branches from the control flow of 601 at 302 and 303 regardless of the presence or absence of the refresh operation signal generated by the address determination circuit 7. , An address / access signal generating circuit 2 based on the pause signal.
3 and a refresh operation signal control circuit 151,1 for controlling a refresh operation signal.
52 are simultaneously disabled, and the address access signal control circuits 81 and 82 and the refresh generation circuit 91,
Reference numeral 92 denotes a disabled state, and the memory circuit 16
1, 162 are simultaneously in a pause state.

The operation of the data generation circuit 3, the data comparison signal control circuits 43 and 44, and the comparison circuits 41 and 42 in FIG. 4 at the time of read comparison is the same as the control flow shown in FIG. 3 of the first embodiment. Therefore, the description is omitted.

In this case, the plurality of memory circuit units are embedded D
RAM (embedded-DEAM). This (Embodiment 2)
According to the embodiment, in addition to the useful effects of the first embodiment, the memory circuit units 161 and 162 can be used at any time as a test circuit for inspecting a pause state of a plurality of memory circuit units.
Can be brought into a pause state at the same time.

(Embodiment 3) The address access signal generation circuits 2 and 23 of (Embodiment 1) and (Embodiment 2)
The BIST control circuits 1 and 12 provide the address / access signal generation circuits 2 and 23 with the maximum address of the memory circuits 161 and 162 by expanding the address bit width of the When the control is performed so as to generate an address equal to or larger than the value, the test circuit of the semiconductor integrated circuit device of the present invention simultaneously refreshes the memory circuits 161 and 162 in accordance with the above-described operations of the first and second embodiments. It becomes possible to.

Next, (Embodiment 4) to (Embodiment 8)
Now, a test method using the test circuit of the semiconductor integrated circuit device according to the first embodiment and the second embodiment will be described.

(Embodiment 4) FIGS. 6 and 7 show two different configurations of the data bit width and the address bit width according to (Embodiment 1), (Embodiment 2) and (Embodiment 3) of the present invention. 10 is a control flow showing a write test method of a semiconductor integrated circuit device having a plurality of memory circuits incorporating a memory circuit, and the following description is based on the assumption that the maximum address value of the memory circuit portion is larger than the maximum address value of the memory circuit portion 162. explain.

FIG. 6 is a write control flow of the BIST control circuits 1 and 12 at the time of address increment.
At 0, the address is set to 0. At 701, the test data generated in the memory circuit units 161 and 162 are written in parallel. At 702, it is determined whether the address of the memory circuit unit 161 is the maximum address. If the address is not the maximum address, the address is incremented at 703, and the memory circuit unit 161 performs steps 701 to 703.
Memory circuit section 16 until the address of
The operation of writing the test data generated in steps 1 and 162 in parallel is repeated. At this time, if the generated address exceeds the maximum address of the memory circuit portion 162, the plurality of built-in memory circuits having the configurations of the first embodiment, the second embodiment, and the third embodiment are provided. The test circuit of the semiconductor integrated circuit device refreshes the memory circuit portion 162 as described above and holds the written test data.

FIG. 7 is a write control flow of the BIST control circuits 1 and 12 at the time of address decrement.
4 sets the address to the maximum address of the memory circuit unit 161, writes test data generated in the memory circuit units 161 and 162 in parallel at 705, and determines whether the address of the memory circuit unit 161 is 0 at 706. If the address of the memory circuit unit 161 is not 0, the address is decremented at 707, and from 705 to 707 is decremented until the address of the memory circuit unit 161 becomes 0.
The operation of writing the test data generated in steps 1 and 162 in parallel is repeated. At this time, when the generated address exceeds the maximum address of the memory circuit portion 162, the test circuit of the semiconductor integrated circuit device having the configuration of the first embodiment or the second embodiment is as described above. Memory circuit section 16
2 is refreshed and the written test data is held.

(Embodiment 5) FIGS. 8 and 9 show two different configurations of the data bit width and the address bit width according to (Embodiment 1), (Embodiment 2) and (Embodiment 3) of the present invention. It is a control flow showing a read test method of a semiconductor integrated circuit device having a built-in memory circuit, and will be described below assuming that the maximum address value of the memory circuit portion is larger than the maximum address value of the memory circuit portion 162.

FIG. 8 is a read control flow at the time of address increment of the BIST control circuits 1 and 12.
At 0, the address is set to 0. At 711, data is read out in parallel from the memory circuit units 161, 162. At 712, the read data is compared with the generated expected value, and the result is returned to the BIST control circuit. , 713, it is determined whether the address of the memory circuit section 161 is the maximum address.
The address is incremented at 14 and 711 to 7
The operation of reading data from the memory circuit units 161 and 162 in parallel until the address of the memory circuit unit 161 reaches the maximum address up to 14 is repeated.

At this time, if the generated address exceeds the maximum address of the memory circuit portion 162, the semiconductor integrated circuit having the configuration of the first embodiment, the second embodiment, and the third embodiment As described above, the test circuit of the circuit device refreshes the memory circuit section 162 and inhibits reading and comparison.

FIG. 9 is a read control flow of the BIST control circuits 1 and 12 at the time of address decrement.
At 5 the address is set to the maximum address of the memory circuit section 161, data is read in parallel from the memory circuit sections 161, 162 at 716, the read data is compared with the expected value generated at 717, and the result is obtained. Returning to the BIST control circuit, it is determined at 718 whether the address of the memory circuit unit 161 is 0. If the address of the memory circuit unit 161 is not 0, the address is decremented at 719,
The operation of reading and comparing data from the memory circuit units 161 and 162 in parallel from 16 to 719 is repeated until the address of the memory circuit unit 161 becomes 0.

At this time, if the generated address exceeds the maximum address of the memory circuit portion 162, the semiconductor integrated circuit having the configuration of the first embodiment, the second embodiment, and the third embodiment As described above, the test circuit of the circuit device refreshes the memory circuit section 162 and inhibits reading and comparison.

(Embodiment 6) FIGS. 10 and 11 show (Embodiment 1), (Embodiment 2) and (Embodiment 3) of the present invention.
Is a control flow showing a test method for continuously reading and writing data at the same address in a semiconductor integrated circuit device incorporating two memory circuits having different configurations of data bit width and address bit width according to the present invention. The following description will be made on the assumption that the value is larger than the maximum address value of the circuit unit 162.

FIG. 10 is a control flow for continuously reading and writing data at the same address in the BIST control circuits 1 and 12 at the time of address increment. The address is set to 0 at 720 and the memory circuit sections 161 and 162 at 721. The data is read in parallel, the read data is compared with the generated expected value in 722, the result is returned to the BIST control circuit, and the test data generated in the memory circuit units 161 and 162 is written in parallel in 723, At 724, it is determined whether the address of the memory circuit unit 161 is the maximum address,
If the address of the memory circuit unit 161 is not the maximum address, the address is incremented at 725, and data is read in parallel from 721 to 725 from the memory circuit units 161 and 162 until the address of the memory circuit unit 161 reaches the maximum address. The operation of writing the test data generated by the comparison is repeated.

At this time, if the generated address exceeds the maximum address of the memory circuit section 162, the semiconductor integrated circuit having the configuration of the first embodiment, the second embodiment, and the third embodiment The test circuit of the circuit device refreshes the memory circuit section 162 as described above, and inhibits reading, comparison, and writing.

FIGS. 10 and 11 show semiconductors incorporating two memory circuits having different data bit widths and address bit widths according to the first embodiment, the second embodiment, and the third embodiment of the present invention. 9 is a control flow showing a test method for continuously reading and writing at the same address of the integrated circuit device, wherein the maximum address value of the memory circuit unit is
The following description is made on the assumption that the address is larger than the maximum address value of 2.

FIG. 11 is a control flow for continuously reading and writing data at the same address at the time of address decrement of the BIST control circuits 1 and 12. In 730, the address is set to the maximum address of the memory circuit section 161. Data is read in parallel from the memory circuits 161 and 162,
At 732, the read data is compared with the generated expected value, and the result is returned to the BIST control circuit. At 733, the test data generated in the memory circuit units 161 and 162 are written in parallel. It is determined whether the address of the memory circuit unit 161 is 0, and if the address of the memory circuit unit 161 is not 0, the address is decremented at 735 until the address of the memory circuit unit 161 becomes 0 from 731 to 735. The operation of reading and comparing data in parallel from 161 and 162 and writing the generated test data is repeated.

At this time, if the generated address exceeds the maximum address of the memory circuit section 162, the semiconductor integrated circuit having the configuration of the first embodiment, the second embodiment, and the third embodiment The test circuit of the circuit device refreshes the memory circuit section 162 as described above, and inhibits reading, comparison, and writing.

(Embodiment 4) (Embodiment 5)
According to the sixth embodiment, as a test method for inspecting a plurality of memory circuit units, read / write access is performed up to a maximum address in a plurality of mounted memory circuit units, so that memories having different memory capacities can be used. On the other hand, it is possible to access the entire area of the plurality of memory circuit units to be mounted without worrying about the refresh operation, and it is possible to obtain an effective effect that the inspection algorithm of the BIST control circuit can be easily created.

(Embodiment 7) FIG. 12 shows a test involving a refresh operation of a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to (Embodiment 3) of the present invention. It is a control flow showing a method.

FIG. 12 is a control flow for performing the write, refresh and read operations of the BIST control circuits 1 and 12, and the test data generated at 900 according to the control flow of FIG. 6 or FIG. Is written in parallel to all areas of the memory circuits 161, 162, and 9
At B01, the BIST control circuits 1 and 12 generate an address larger than the maximum address value of the memory circuit units 161 and 162 at any time from the address / access signal generation circuits 2 and 21 (third embodiment). As described above, the test circuit of the semiconductor integrated circuit device having a plurality of memory circuits with the configuration of FIG.
62 can be simultaneously refreshed, and in 902 the data in all areas of the memory circuits 161 and 162 are read out in parallel according to the control flow of FIG. 8 or FIG. , The comparison result is returned to the BIST control circuits 1 and 12.

According to the seventh embodiment, as a test method for checking the refresh operation of a plurality of memory circuit units, an arbitrary address is generated only by generating an address larger than the maximum address of a plurality of memory circuit units to be mounted. A plurality of memory circuit units mounted in time can be simultaneously placed in the refresh state, and an effective effect of improving the efficiency of inspection involving a refresh operation can be obtained.

(Embodiment 8) FIG. 13 shows a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to (Embodiment 2) and (Embodiment 3) of the present invention. 5 is a control flow showing a test method involving a pause operation of FIG.

FIG. 13 is a control flow for performing write, pause, and read operations of the BIST control circuit 12.
At 910, the test data generated according to the control flow of FIG. 6 or FIG.
1, 162 are written in parallel to all areas,
By generating a pause signal from the ST control circuit 12 at an arbitrary time, the test circuit of the semiconductor integrated circuit device having the configuration of the second embodiment or the third embodiment allows the memory circuit section 161 to operate as described above. , 162 can be put into a pause state at the same time, and at 902 FIG.
Alternatively, according to the control flow of FIG.
The data of all the areas 62 are read out in parallel and compared in parallel with the test data generated, and the comparison result is returned to the BIST control circuits 1 and 12.

According to this (Embodiment 8), as a test method for inspecting the pause operation of a plurality of memory circuit sections,
The pause signal generated from the BIST control circuit 12 makes it possible to simultaneously put a plurality of memory circuit units mounted in an arbitrary state into a pause state at an arbitrary time, thereby improving the efficiency of the inspection involving the pause state. The effect is obtained.

[0086]

According to the configuration of the first aspect of the present invention, the plurality of memory circuit units having different address bit widths and data bit widths can be read / written in parallel by a single BIST circuit unit.

According to the configuration of claim 2 of the present invention, the plurality of memory circuit units having different address bit widths and data bit widths can be read / written in parallel by a single BIST circuit unit, and can be simultaneously set in the pause state. it can.

According to the third aspect of the present invention, when an address value exceeding the maximum address of a plurality of memory circuit units is generated, the plurality of memory circuit units can be simultaneously refreshed.

According to the configuration of the fourth aspect of the present invention, when a plurality of memory circuit sections are mounted, the ratio of the BIST circuit section to the chip can be greatly reduced.

According to the configuration of the fifth aspect of the present invention, the plurality of memory circuit sections have the maximum data bit width without worrying about the address bit width and the data bit width of each of the plurality of memory circuit sections. By writing up to the address,
An inspection for writing data in parallel to all regions of the plurality of memory circuit units can be realized.

According to the configuration of claim 6 of the present invention, the maximum data bit width can be obtained from the plurality of memory circuit units without worrying about the address bit width and the data bit width of each of the plurality of memory circuit units. By reading up to the address, it is possible to realize a test for reading data in parallel from all regions of the plurality of memory circuit units.

According to the configuration of claim 7 of the present invention, the maximum number of data bit widths can be obtained from the plurality of memory circuit units without considering the address bit width and the data bit width of each of the plurality of memory circuit units. By reading and writing up to the address, it is possible to realize an inspection for reading and writing data in all areas of the plurality of memory circuit units in parallel.

According to the eighth aspect of the present invention, the BIS
While the T circuit section is generating the pause signal, the plurality of memory circuit sections can be paused at the same time, thereby improving the efficiency of the inspection involving the pause state.

According to the ninth aspect of the present invention, the BIS
While the T circuit section is generating an address larger than the maximum address of the plurality of memory circuit sections, the plurality of memory circuit sections can be simultaneously in the refresh state, thereby improving the efficiency of inspection involving refresh. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a test circuit of a semiconductor integrated circuit device including two memory circuits having different data bit widths and address bit widths according to a first embodiment of the present invention;

FIG. 2 is a control flow chart of an address and an access signal at the time of read / write access to two memory circuit units 161 and 162 having different configurations of a data bit width and an address bit width according to the first embodiment of the present invention;

FIG. 3 shows BIST circuit units 5 and 52 at the time of reading to two memory circuit units 161 and 162 having different configurations of data bit width and address bit width in (Embodiment 1) and (Embodiment 2) of the present invention. Control flow chart of the comparison circuits 41 and 42 of FIG.

FIG. 4 incorporates two memory circuits having different data bit widths and address bit widths according to the second embodiment of the present invention to which a function capable of simultaneously setting the memory circuit portions 161 and 162 in a pause state is added. Diagram of test circuit of semiconductor integrated circuit device

FIG. 5 shows an address and access signal at the time of read / write access to two memory circuit units 161 and 162 having different configurations of a data bit width and an address bit width controlled by a pause signal in (Embodiment 2) of the present invention. Control flow diagram

FIG. 6 (Embodiment 1) to (Embodiment 3) of the present invention.
Flow chart showing a write test method at the time of address increment of a semiconductor integrated circuit device having two built-in memory circuits having different data bit widths and address bit widths according to the present invention.

FIG. 7 (Embodiment 1) to (Embodiment 3) of the present invention.
Flow chart showing a write test method at the time of address decrement of a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to the present invention.

FIG. 8 (Embodiment 1) to (Embodiment 3) of the present invention.
Flow chart showing a read test method at the time of address increment of a semiconductor integrated circuit device incorporating two memory circuits having different configurations of data bit width and address bit width according to the method.

FIG. 9 (Embodiment 1) to (Embodiment 3) of the present invention.
Flow chart showing a read test method at the time of address decrement of a semiconductor integrated circuit device incorporating two memory circuits having different configurations of the data bit width and the address bit width according to the above.

FIG. 10 shows the same address at the time of address increment in a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to the first to third embodiments of the present invention. Flow chart showing a test method for continuous reading and writing on a PC

FIG. 11 is the same at the time of address decrement of a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to the first to third embodiments of the present invention. Control flow diagram showing test method for continuous reading and writing by address

FIG. 12 is a test method including a refresh operation of a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to the first to third embodiments of the present invention. Control flow diagram showing

FIG. 13 is a control flow chart showing a test method with a pause operation of a semiconductor integrated circuit device incorporating two memory circuits having different data bit widths and address bit widths according to (second embodiment) of the present invention;

FIG. 14 is a configuration diagram of a test circuit of a semiconductor integrated circuit device incorporating two memory circuits having different configurations of a data bit width and an address bit width in a conventional embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 BIST control circuit 2 Address / access signal generation circuit 3 Data generation circuit 41, 42 Comparison circuit 43, 44 for comparing read data and outputting the result Data comparison signal control circuit 5 BIST circuit section 6 Memory circuit section maximum address storage circuit 7 Address discriminating circuits 81, 82 Address / access signal control circuits 91, 92 Refresh generating circuits 161, 162 Memory circuit sections 111, 112 having different configurations of data bit width / address bit width Address / access signal multiplex 121, 122 Memory circuit 131 , 132 Data multiplex 52 BIST circuit section 12 BIST control circuit 151, 152 Refresh operation signal control circuit controllable by pause signal 23 Address access signal generation circuit controllable by pause signal

Claims (9)

[Claims] In a semiconductor integrated circuit in which a single self-test circuit section and a plurality of memory circuit sections are formed on the same chip, the self-test circuit section includes a plurality of test circuits for testing the plurality of memory circuit sections. A single address and access signal generating means for generating a maximum address and an access signal of the memory circuit section, and generating test data having a maximum data bit width of the plurality of memory circuit sections for testing the plurality of memory circuit sections; A single data generation unit, a single memory circuit unit maximum address storage unit for storing a maximum address value for each of the plurality of memory circuit units, and an address generated by the address and access signal generation unit, It is determined for each of the plurality of memory circuit units that the address is equal to or more than the address set by the unit maximum address storage unit. A single address discriminating means for generating the same number of refresh operation signals as the plurality of memory circuit portions, and an address and access generated by the address and access signal generating means by the plurality of refresh operation signals generated by the address discriminating means; And the same number of address and access signal control means as the plurality of memory circuit sections, and the same number of memory circuit sections as the plurality of memory circuit sections generating a refresh signal by the plurality of refresh operation signals generated by the address determination means. Refresh generating means; and the same number of data comparison signal control means as the plurality of memory circuit sections for disabling the read data comparison signals of the plurality of memory circuit sections by the plurality of refresh operation signals generated by the address determination means. , The compound The plurality of memory circuit units performing a comparison for each of the data generated by the data generation unit and the data read from the plurality of memory circuit units by a read data comparison signal propagated from the data comparison signal control unit; The same number of comparison units, the address and access signal generation unit, the data generation unit, and the plurality of data comparison signal control units are controlled according to a check algorithm to check the plurality of memory circuit units, and the plurality of comparison units A single BI that outputs the presence or absence of an error in the plurality of memory circuit units based on the comparison result returned
A test circuit for a semiconductor integrated circuit device comprising ST control means. 2. A semiconductor integrated circuit in which a single self-test circuit section and a plurality of memory circuit sections are formed on the same chip, wherein the self-test circuit section includes a plurality of memory circuits for testing the plurality of memory circuit sections. A single address and access signal generating means for generating a maximum address and an access signal of the memory circuit section and disabling generation of the address and access signal at the time of a pause check of the plurality of memory circuit sections; and A single data generating means for generating test data having a maximum data bit width of the plurality of memory circuit units for testing, and a single memory circuit unit for storing a maximum address value for each of the plurality of memory circuit units The maximum address storage means and the address generated by the address and access signal generation means store the maximum address in the memory circuit unit. A single address discriminating means for discriminating for each of the plurality of memory circuit portions that the address is equal to or more than the address set by the address storage device and generating the same number of refresh operation signals as the plurality of memory circuit portions; The plurality of generated refresh operation signals are not propagated during a pause test of the plurality of memory circuit units. The same number of address and access signal control means as the plurality of memory circuit units for disabling the address and access generated by the address and access signal generation means by the plurality of refresh operation signals, and the plurality of refresh operation signal control means Said plurality propagated from The same number of refresh generation units as the plurality of memory circuit units for generating a refresh signal by a refresh operation signal, and reading of the plurality of memory circuit units by the plurality of refresh operation signals transmitted from the plurality of refresh operation signal control units The same number of data comparison signal control units as the plurality of memory circuit units for disabling the data comparison signal; and the data generated by the data generation unit based on the read data comparison signal propagated from the plurality of data comparison signal control units. And the same number of comparing units as the plurality of memory circuit units for performing a comparison for each data read from the plurality of memory circuit units, and the address and access signal generating unit, the data generating unit, A plurality of data comparison signal control means and the plurality of refresh signals; A single BIST control unit that controls the operation signal control unit, inspects the plurality of memory circuit units, and outputs the presence or absence of an error in the plurality of memory circuit units based on a comparison result returned by the plurality of comparison units. Test circuits for semiconductor integrated circuit devices. 3. The test circuit for a semiconductor integrated circuit device according to claim 1, wherein said single address and access signal generating means can generate more than a maximum address of said plurality of memory circuit units. 4. The integrated memory circuit according to claim 1, wherein the plurality of memory circuit units are embedded DRAM (e).
4. The test circuit for a semiconductor integrated circuit device according to claim 1, wherein the test circuit is a mbedded-DEAM. 5. A method for testing a semiconductor integrated circuit in which said self-test circuit section and said plurality of memory circuit sections are formed on the same chip, wherein data is written to all memory areas of said plurality of memory circuit sections. A plurality of addresses, access signals and data inputs are generated in the self-test circuit section, and the data inputs are simultaneously written in parallel to the memory cells of the plurality of memory circuit sections to be write-tested. It is independently determined for each of the plurality of memory circuit units whether an address value to be subjected to a write test to the memory circuit unit is equal to or greater than a maximum address. When the address value is equal to or greater than the maximum address, the address and access of the plurality of memory circuit units are determined. Signal is held independently, and a refresh signal is generated in place of the writing step to generate the refresh signal. After the step of independently refreshing the memory circuit section and the step of writing and refreshing are completed, the step of changing the address and the access signal and the data input of the plurality of memory circuit sections is performed up to the maximum address of the plurality of memory circuit sections. 5. The test method for a semiconductor integrated circuit device according to claim 1, wherein the test is repeated. 6. A method for testing a semiconductor integrated circuit in which said self-test circuit section and said plurality of memory circuit sections are formed on a same chip, wherein when reading data of an entire memory area from said plurality of memory circuit sections, Generating addresses and access signals and read expected value data of a plurality of memory circuit units in the self-test circuit unit, and simultaneously reading data in parallel from memory cells of the plurality of memory circuit units to be read-checked; A step of independently comparing the data read from the plurality of memory circuit sections in the reading step and the read expected value data for each of the plurality of memory circuit sections; and a step of reading the plurality of memory circuit sections in the reading step. It is independently determined for each of the plurality of memory circuit units whether the address value to be Discriminating, when the address is equal to or more than the maximum address, independently holding the addresses and access signals of the plurality of memory circuit units, generating a refresh signal to refresh the memory circuit unit independently, and comparing the read data in the comparing step. Returning the match result to the self-test circuit unit without comparing the read expected value data with the self-test circuit unit, and after completing the comparing and refreshing step, the addresses and access signals of the plurality of memory circuit units and the read expected value data are read. 5. The test method for a semiconductor integrated circuit device according to claim 1, wherein the step of changing is repeated up to a maximum address of said plurality of memory circuit units. 7. A method for testing a semiconductor integrated circuit in which said self-test circuit section and said plurality of memory circuit sections are formed on the same chip, wherein data in all memory areas of said plurality of memory circuit sections are continuously read and written. Generating the address, access signal and read expected value data of the plurality of memory circuit units in the self-test circuit unit, and simultaneously reading data from the memory cells of the plurality of memory circuit units to be read-checked in parallel. Independently comparing the data read from the plurality of memory circuit units in the reading step and the read expected value data for each of the plurality of memory circuit units; and the plurality of memory circuit units in the reading step It is determined for each of the plurality of memory circuit units whether an address value to be read and inspected is equal to or greater than a maximum address. Independently judging, when the address is equal to or more than the maximum address, the addresses and the access signals of the plurality of memory circuit units are independently held, a refresh signal is generated, the memory circuit units are independently refreshed, and the comparison is performed. Returning a match result to the self-test circuit unit without comparing the read data and the read expected value data; and generating, in the self-test circuit unit, addresses and access signals and data inputs of the plurality of memory circuit units; A step of simultaneously writing the data inputs in parallel to the memory cells of the plurality of memory circuit units to be written-checked, and an address value to be written-checked to the plurality of memory circuit units in the writing step is greater than or equal to a maximum address Is determined independently for each of the plurality of memory circuit units, and the Sometimes, independently holding addresses and access signals of the plurality of memory circuit sections, generating a refresh signal in place of the writing step to independently refresh the memory circuit section, and after completing the writing step, 5. The method according to claim 1, wherein the step of changing the address, the access signal, and the read expected value data of the memory circuit section is repeated up to the maximum address of the plurality of memory circuit sections.
The test method of the semiconductor integrated circuit device according to the above. 8. A method for testing a semiconductor integrated circuit in which said self-test circuit section and said plurality of memory circuit sections are formed on the same chip, wherein an address and an access signal are generated by a pause signal generated in said self-test circuit section. 3. The test method for a semiconductor integrated circuit device according to claim 2, wherein the plurality of memory circuit units are simultaneously set in a pause state without generating a refresh signal to the plurality of memory circuit units. 9. A method for testing a semiconductor integrated circuit in which said self-test circuit section and said plurality of memory circuit sections are formed on the same chip, wherein an address value generated in said self-test circuit section is said plurality of memory circuits. 5. The test method for a semiconductor integrated circuit device according to claim 1, wherein the plurality of memory circuit units are simultaneously set in a refresh state when the state is larger than the maximum address of the unit.