JP2000150544A - Mounting method - Google Patents

Mounting method

Info

Publication number
JP2000150544A
JP2000150544A JP33671999A JP33671999A JP2000150544A JP 2000150544 A JP2000150544 A JP 2000150544A JP 33671999 A JP33671999 A JP 33671999A JP 33671999 A JP33671999 A JP 33671999A JP 2000150544 A JP2000150544 A JP 2000150544A
Authority
JP
Japan
Prior art keywords
wafer
chip
substrate
tape
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33671999A
Other languages
Japanese (ja)
Other versions
JP3197884B2 (en
Inventor
Mitsuo Usami
光雄 宇佐美
Kunihiro Tsubosaki
邦宏 坪崎
Kunihiko Nishi
邦彦 西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP33671999A priority Critical patent/JP3197884B2/en
Publication of JP2000150544A publication Critical patent/JP2000150544A/en
Application granted granted Critical
Publication of JP3197884B2 publication Critical patent/JP3197884B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]

Abstract

PROBLEM TO BE SOLVED: To provide a method by which a semiconductor device which can be handled easily can be manufactured by stably producing a thin chip at a low cost. SOLUTION: The thickness of a wafer 105 stuck to a tape 107 is reduced by uniformly etching the wafer 105 by moving an etchant at a high speed in the lateral direction against the surface of the wafer 105, by rotating the wafer 105 or moving the wafer 105 forward and backward in the lateral direction in a plane at a high speed. Then a thin chip 105' obtained by dicing the thinned wafer is fixed on a substrate 102 by heating and press-contacting the chip 105' with the substrate 102 by means of a heating head 106. Therefore, the thin chip 105' can be formed stably at a low cost and can be fixed to the substrate 102 without causing cracks in the chip 105'.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に極めて薄い半導体装置を安定かつ低コス
トで形成するのに好適な半導体装置の製造方法に関す
る。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device suitable for forming an extremely thin semiconductor device stably and at low cost.

【0002】[0002]

【従来の技術】従来の半導体装置の組立技術としては、
たとえば「LSIハンドブック」(社団法人電子通信学
会編株式会社オーム社、昭和59年11月30日発行、
第406頁〜416頁)などに記載されており、これら
従来の半導体装置の組立て技術では、直接ハンドリング
を行っても、割れないほぼ200μm以上の厚さを有す
る半導体チップが扱われていた。
2. Description of the Related Art Conventional semiconductor device assembly techniques include:
For example, "LSI Handbook" (edited by the Institute of Electronics and Communication Engineers, Ohmsha Co., Ltd., issued on November 30, 1984,
(Pages 406 to 416), etc., and these conventional semiconductor device assembling techniques deal with a semiconductor chip having a thickness of about 200 μm or more, which does not crack even when directly handled.

【0003】[0003]

【発明が解決しようとする課題】周知のように、半導体
ウエハを薄くする手段としては、研磨法が広く用いられ
ている。しかし、研磨法によって半導体ウエハを均一
に、たとえば5%以内の加工精度で加工するためには、
ウエハと研磨装置の並行出しを、高精度かつ高い再現性
で行わなう必要があり、このような極めて高い並行出し
を行うためには、極めて高価な装置が必要であり、実用
は困難であった。
As is well known, a polishing method is widely used as a means for thinning a semiconductor wafer. However, in order to process the semiconductor wafer uniformly by the polishing method, for example, with a processing accuracy of 5% or less,
It is necessary to perform the parallel placement of the wafer and the polishing apparatus with high precision and high reproducibility. To perform such extremely high parallel placement, extremely expensive equipment is required, and practical use is difficult. Was.

【0004】また、半導体ウエハの厚さをモニタしなが
ら、研磨を行う方法も行われているが、広い範囲の厚さ
領域でこの方法を行うと、所要時間が著しく長くなって
生産性が低下してしまう。
There is also a method of performing polishing while monitoring the thickness of a semiconductor wafer. However, if this method is performed over a wide range of thickness, the required time becomes extremely long and the productivity is reduced. Resulting in.

【0005】また、半導体ウエハの厚さを、例えば0.
1μmの程度と極めて薄くなるまで研磨を行うと、半導
体ウエハ表面のデバイスが、研磨によって生ずるストレ
スのために破壊されてしまうという問題もあった。
[0005] Further, the thickness of the semiconductor wafer is set to, for example, 0.
When polishing is performed to a very thin thickness of about 1 μm, there is a problem that devices on the surface of the semiconductor wafer are destroyed due to stress caused by polishing.

【0006】さらに、このように薄くされた半導体チッ
プを、上記従来技術によって直接ハンドリングを行う
と、半導体チップ自体が破壊されてしまうという問題が
あり、高い歩留と低いコストで、半導体装置を形成する
のは困難であった。
Further, if the semiconductor chip thus thinned is directly handled by the above-mentioned conventional technique, there is a problem that the semiconductor chip itself is destroyed, and a semiconductor device is formed at a high yield and at a low cost. It was difficult to do.

【0007】本発明の目的は、従来技術の有する上記問
題を解決し、半導体チップの厚さを0.1から110μ
m程度まで薄くすることができ、かつ、このような極め
て薄いチップを、割れの発生なしにハンドリングするこ
とができる半導体装置の製造方法を提供することであ
る。
An object of the present invention is to solve the above-mentioned problems of the prior art and to reduce the thickness of a semiconductor chip from 0.1 to 110 μm.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be thinned to about m and can handle such an extremely thin chip without generating a crack.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、ウエハをテープに貼り付け、このウエハ
の表面方向内で高速度に回転若しくは横方向に往復運動
させながら、エッチ液と接触させることによって、ウエ
ハを均一にエッチングして膜厚を極めて小さくした後、
薄くされたウエハをダイジングして複数のチップに分割
し、これら各薄いチップを、対象基板に加熱圧順次接し
て固着させるものである。
In order to achieve the above-mentioned object, the present invention provides a method of attaching a wafer to a tape and rotating the wafer at high speed or reciprocating in a lateral direction within the surface direction of the wafer, while etching the wafer with tape. By contacting, the wafer is uniformly etched to make the film thickness extremely small,
The thinned wafer is diced and divided into a plurality of chips, and these thin chips are sequentially brought into contact with a target substrate under heating pressure to be fixed.

【0009】半導体ウエハが、この半導体ウエハの面内
方向において、急速度で回転若しくは往復運動しなが
ら、エッチ液と接触されるので、極めて均一にエッチン
グが行われ、凹凸や歪の発生なしに、極めて薄いウエハ
を得ることができる。
Since the semiconductor wafer is brought into contact with the etchant while rotating or reciprocating at a rapid speed in the in-plane direction of the semiconductor wafer, the etching is performed very uniformly, without any unevenness or distortion. An extremely thin wafer can be obtained.

【0010】このような極めて薄いウエハを分割して形
成された複数の薄いチップは、第1の基板であるテープ
上から順次分離されて、加熱および圧接されるため、チ
ップが極めて薄いにもかかわらず、割れの発生なしに上
記第2の基板上に固着することができる。特に、上記第
1の基板として軟質のテープを用いることにより、所望
のチップのみを上方に押し上げ、このチップのみを選択
的に加熱できるので、所望のチップを上記第2の基板へ
固着するのは極めて容易である。
The plurality of thin chips formed by dividing such an extremely thin wafer are sequentially separated from the tape as the first substrate and heated and pressed, so that the chips are extremely thin. Instead, it can be fixed on the second substrate without cracking. In particular, by using a soft tape as the first substrate, only a desired chip can be pushed upward and only this chip can be selectively heated. Therefore, it is difficult to fix the desired chip to the second substrate. Extremely easy.

【0011】さらに、上記第2の基板とチップとの固着
を、導電性接着剤を介して行うことによって、ワイヤボ
ンデイングは不要になり、工程の簡略化とコストの低減
に極めて有効である。
Furthermore, by bonding the second substrate and the chip via a conductive adhesive, wire bonding becomes unnecessary, which is extremely effective in simplifying the process and reducing the cost.

【0012】[0012]

【発明の実施の形態】以下、図面を用いて本発明の実施
例を説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0013】〈実施例1〉図1に示したように、薄い半
導体ウエハ105は、枠101によって保持されたテー
プ(日立化成株式会社製、HA−1506)107の上
に置かれ、この半導体ウエハ105は、ダイシング溝1
04によって複数のチップ105´に分離されている。
<Embodiment 1> As shown in FIG. 1, a thin semiconductor wafer 105 is placed on a tape (HA-1506, manufactured by Hitachi Chemical Co., Ltd.) 107 held by a frame 101. 105 is a dicing groove 1
04 separates into a plurality of chips 105 ′.

【0014】分離された各チップ105´は、加熱ヘッ
ド106によってテープ107の裏面から上方へ押し上
げられ、接着剤103が塗布された基板102に押しつ
けられて、当該基板102に加熱接着される。この接着
剤103は、有機物質と導電性粒子の複合材料からなる
異方導電性接着剤であるため、基板102に形成された
電極(図示せず)と薄型チップ105が有する電極(図
示せず)は、加圧と加熱によって互いに電気的に接続さ
れる。なお、上記チップ105´は、厚さが0.1〜1
0μm程度で、曲げることが可能な極めて薄いチップで
ある。厚さが0.1μmより小さいと、このチップ10
5´に各種半導体素子を形成するのが困難になり、10
μmより大きいと、曲げによって割れの生ずる恐れがあ
る。
Each separated chip 105 ′ is pushed upward from the back surface of the tape 107 by the heating head 106, pressed against the substrate 102 on which the adhesive 103 is applied, and heated and adhered to the substrate 102. Since the adhesive 103 is an anisotropic conductive adhesive made of a composite material of an organic substance and conductive particles, an electrode (not shown) formed on the substrate 102 and an electrode (not shown) of the thin chip 105 are provided. ) Are electrically connected to each other by pressurization and heating. The tip 105 'has a thickness of 0.1 to 1 mm.
It is a very thin chip that can be bent at about 0 μm. If the thickness is smaller than 0.1 μm, this chip 10
It becomes difficult to form various semiconductor elements in 5 ′,
If it is larger than μm, there is a possibility that cracking may occur due to bending.

【0015】また、上記テープ107は軟質であるた
め、加熱ヘッド106によってテープ107を加熱しな
がら上方へ押し上げることによって、テープ107上の
上記薄いチップ105´も押し上げられ、基板102と
均一かつ安定に接着される。
Further, since the tape 107 is soft, the tape 107 is pushed upward while being heated by the heating head 106, so that the thin chip 105 'on the tape 107 is also pushed up, and the tape 107 is uniformly and stably formed on the substrate 102. Glued.

【0016】図3は図1の平面構造を示す図であり、テ
ープ107は枠101によって保持され、ウエハ105
はダイシング溝104によってチップ105´に互いに
分離されている。ウエハ105の周囲304は枠101
の内側にあって、テープ107に平坦に接着されてい
る。枠101はステンレスまたはプラスチック材で形成
されている。ウエハ105の厚さは0.1から110μ
mと極めて薄いにもかかわらず、粘着剤によってテープ
107に強固に粘着されているため、ウエハ105をテ
ープ107に粘着した状態でダイシングを行っても、薄
いチップ105´がテープ107から、ばらばらに剥離
してしまうことはない。
FIG. 3 is a view showing the planar structure of FIG. 1, in which a tape 107 is held by a frame 101 and a wafer 105
Are separated into chips 105 ′ by dicing grooves 104. The periphery 304 of the wafer 105 is the frame 101
And is flatly adhered to the tape 107. The frame 101 is formed of stainless steel or a plastic material. The thickness of the wafer 105 is 0.1 to 110 μm
Even though the wafer 105 is extremely thin, since it is strongly adhered to the tape 107 by the adhesive, even when dicing is performed while the wafer 105 is adhered to the tape 107, the thin chips 105 ′ are separated from the tape 107. It does not peel off.

【0017】上記薄いチップ105´を基板102に固
着した後の状態を図4に示した。図4(1)は平面図、
図4(2)は断面図である。基板102の上には、位置
合わせされて薄いチップ105´が固着されている。薄
いチップ105´に形成された電極と基板102に形成
された電極は、フェースダウンボンデイングによって互
いに接続されている。しかし、ワイヤボンディングある
いは導電性ペーストによって互いに接続してもよい。
FIG. 4 shows a state after the thin chip 105 'is fixed to the substrate 102. FIG. 4A is a plan view,
FIG. 4B is a cross-sectional view. A thin chip 105 ′ is aligned and fixed on the substrate 102. The electrodes formed on the thin chip 105 ′ and the electrodes formed on the substrate 102 are connected to each other by face-down bonding. However, they may be connected to each other by wire bonding or conductive paste.

【0018】薄いチップの実装が、このように簡単かつ
容易にできるため、半導体装置の薄型化、高機能化およ
び低コスト化が促進されて、新しい応用展開をもたらす
ことができる。
Since thin chips can be mounted easily and easily in this manner, thinning, high performance, and low cost of semiconductor devices are promoted, and new applications can be developed.

【0019】なお、図4(3)は、図4(1)、(2)
に示した薄いチップ105´と基板102の接続部を拡
大して模式的に示した断面図である。図4(3)に示し
たように、パッド405は薄いチップ105´表面の、
パッシベーション膜408が除去された部分に設けられ
ており、導電性粒子406によって、基板102の表面
上に設けられた基板電極412に接続され、互いに導通
されている。基板102とチップ105´の間には有機
フィルム409が介在して設けられており、この有機フ
ィルム409の中に導電粒子410が含まれていて、こ
の導電性粒子410によって両者間が導通される。
FIG. 4C shows FIGS. 4A and 4B.
FIG. 3 is an enlarged cross-sectional view schematically showing a connection portion between a thin chip 105 ′ and a substrate 102 shown in FIG. As shown in FIG. 4C, the pad 405 is located on the surface of the thin chip 105 ′.
The passivation film 408 is provided in a portion where the passivation film has been removed, and is connected to the substrate electrode 412 provided on the surface of the substrate 102 by the conductive particles 406 and is electrically connected to each other. An organic film 409 is provided between the substrate 102 and the chip 105 ', and the organic film 409 contains conductive particles 410, and the conductive particles 410 allow conduction between the two. .

【0020】一方、従来法においては、図2に示したよ
うに、テープ203上のチップ202は、真空チャック
201によってハンドリングされて他の基板(図示せ
ず)上へ移動される。すなわち、テープ203の上に置
かれたチップ202は、ウエハのダイシングによって形
成された個別のチップであり、突き上げピン204によ
って突き上げられたチップ202は、真空チャック20
1によって吸引されて1個ずつ順次移動される。
On the other hand, in the conventional method, as shown in FIG. 2, a chip 202 on a tape 203 is handled by a vacuum chuck 201 and moved onto another substrate (not shown). That is, the chips 202 placed on the tape 203 are individual chips formed by dicing the wafer, and the chips 202 pushed up by the push-up pins 204 are placed on the vacuum chuck 20.
1 and are sequentially moved one by one.

【0021】テープ203には粘着剤が塗布されてお
り、紫外線(UV)照射または加熱によって、接着性は
低下しているが、なおわずかに接着性が残っているの
で、真空チャック201と連動して動作する突き上げピ
ン204によって、チップ202はテープ203から分
離できる。
An adhesive is applied to the tape 203, and the adhesiveness is reduced by ultraviolet (UV) irradiation or heating, but the adhesiveness is still slightly left. The chip 202 can be separated from the tape 203 by the push-up pin 204 that operates.

【0022】しかし、この突き上げピン204によって
上方へ突き上げる従来も方法では、チップ202の厚さ
が0.1から110μmと極めて薄い場合は、チップ2
02に割れが入りやすくなり、生産性が低下してしま
う。
However, in the conventional method in which the chip 202 is pushed upward by the push-up pin 204, if the thickness of the chip 202 is extremely thin, from 0.1 to 110 μm, the chip 2
02 is apt to crack and productivity is reduced.

【0023】〈実施例2〉本実施例はウエハを薄くする
方法を示す。
<Embodiment 2> This embodiment shows a method of thinning a wafer.

【0024】図5(1)に示したように、ウエハ105
は、枠101に貼られたテープ107上に粘着剤によっ
て固定されており、エッチ液ノズル501からエッチ液
502が滴下されて、ウエハ105の表面がエッチされ
る。エッチ液502としては、本実施例では水酸化カリ
ウムの水溶液(濃度40%)を用いたが、水酸化カリウ
ム以外のエッチ液を用いてもよい。
As shown in FIG. 5A, the wafer 105
Is fixed on a tape 107 affixed to the frame 101 with an adhesive, and an etchant 502 is dropped from an etchant nozzle 501 to etch the surface of the wafer 105. Although an aqueous solution of potassium hydroxide (concentration: 40%) is used as the etchant 502 in this embodiment, an etchant other than potassium hydroxide may be used.

【0025】この際、ウエハ105は毎分1.000回
転以上の高速度で回転されるので、図5(2)に示した
ように、エッチ液502は、ウエハ105の表面上を横
方向に高速度で移動する。そのため、ウエハ105の表
面は、段差やダメージの発生なしに均一にエッチされ、
ウエハ105は薄い膜になた。
At this time, since the wafer 105 is rotated at a high speed of not less than 1.000 revolutions per minute, as shown in FIG. Move at high speed. Therefore, the surface of the wafer 105 is uniformly etched without any step or damage,
The wafer 105 became a thin film.

【0026】同様に、図5(3)に示したように、ウエ
ハ105を毎分1、000往復以上の高速往復運動する
ことにより、エッチ液502はウエハ105の表面上を
横方向に高速度でに移動し、ウエハ105の表面は、段
差やダメージの発生なしに均一にエッチされ、薄膜化さ
れた。
Similarly, as shown in FIG. 5 (3), the etchant 502 is moved at a high speed in the lateral direction on the surface of the wafer 105 by reciprocating the wafer 105 at a high speed of 1,000 reciprocations per minute or more. As a result, the surface of the wafer 105 was uniformly etched without a step or damage, and was thinned.

【0027】〈実施例3〉図6は本発明の他の実施例を
示す工程図である。
<Embodiment 3> FIG. 6 is a process diagram showing another embodiment of the present invention.

【0028】図6(1)に示したように、枠101に貼
られたテープ107の上に、ウエハ105を固定した
後、上記実施例2に示した方法によってウエハ105を
薄くして、図6(2)に示す断面構造を形成し、さら
に、図6(3)に示したように、ウエハ105にダイシ
ング溝104を形成し、ウエハ105を複数のチップ1
05´に分割した。
As shown in FIG. 6A, after the wafer 105 is fixed on the tape 107 attached to the frame 101, the wafer 105 is thinned by the method described in the second embodiment. 6 (2), a dicing groove 104 is formed in the wafer 105 as shown in FIG. 6 (3), and the wafer 105 is
05 '.

【0029】次に、図6(4)に示したように、基板1
02にチップ105´を位置合わせした後、加熱ヘッド
106を下から押し当てて、所望のチップ105´を加
熱加圧し、図6(5)に示したように、基板102に薄
いチップ105´を移し、接着剤103を介して固着さ
せた。各チップ105´の特性は、分割前のウエハ状態
のときに、あらかじめ測定されており、良品と不良品が
それぞれ明確となっているので、良品のチップのみを選
択的に位置合わせし、基板102に移して固着した。
Next, as shown in FIG.
02, the heating head 106 is pressed from below to heat and press the desired chip 105 ′, and as shown in FIG. 6 (5), the thin chip 105 ′ is placed on the substrate 102. It was transferred and fixed via the adhesive 103. The characteristics of each chip 105 ′ are measured in advance in the wafer state before the division, and the non-defective products and the defective products are clearly defined. And fixed.

【0030】なお、実施例2および3においては、テー
プ107として実施例1に用いたと同じものを用いた
が、それ以外の各種テープを使用できることは、いうま
でもない。
In Examples 2 and 3, the same tape as that used in Example 1 was used as the tape 107, but it goes without saying that various other tapes can be used.

【0031】〈実施例4〉図7は本発明の他の実施例を
示す工程図であり、薄いチップの主面側を基板主面を対
向させて、フェースダウンボンデイングによって接合し
た例である。
<Embodiment 4> FIG. 7 is a process diagram showing another embodiment of the present invention, in which a thin chip main surface is joined by face-down bonding with the substrate main surface facing each other.

【0032】まず、図7(1)に示したように、第1の
枠101に貼られた第1のテープ107の上にウエハ1
05を固定し、図7(2)に示したように、上記実施例
2と同様にして、ウエハ105を薄くした。
First, as shown in FIG. 7A, the wafer 1 is placed on the first tape 107 attached to the first frame 101.
7 was fixed, and the wafer 105 was thinned in the same manner as in Example 2 as shown in FIG.

【0033】図7(3)に示したように、ウエハ105
の表面を下向きにして、第2の枠101´に貼られた第
2のテープ107´の表面に対向させて貼り合わせた。
As shown in FIG. 7C, the wafer 105
With the surface of the tape facing down and facing the surface of the second tape 107 'affixed to the second frame 101'.

【0034】上記第1のテープ107をウエハ105か
ら剥離して、ウエハ105が第2のテープ107´の表
面上に形成された構造とした後、図7(4)に示したよ
うに、ウエハ105にダイシング溝104を形成して、
複数のチップ105´に分離させた。
After the first tape 107 is peeled off from the wafer 105 to form a structure in which the wafer 105 is formed on the surface of the second tape 107 ', as shown in FIG. Forming a dicing groove 104 in 105;
The chips were separated into a plurality of chips 105 '.

【0035】次に、図7(5)に示したように、基板1
02に上記チップ105´を位置合わせして加熱ヘッド
106を下から押し当てて加熱加圧し、図7(6)に示
したように、基板102に薄いチップ105´を異方導
電性接着剤709を介して接着した。
Next, as shown in FIG.
2 and the heating head 106 is pressed from below to apply heat and pressure, and as shown in FIG. 7 (6), the thin chip 105 ′ is attached to the substrate 102 by the anisotropic conductive adhesive 709. Glued through.

【0036】本実施例によれば、チップ105´が第2
のテープ107´に移された後に基板102に移され
る。そのため、半導体チップ105´の表裏が上記実施
例1の場合とは逆になって、当初のウエハ105上面
が、基板102に固着された状態でも上面になる。した
がって、本実施例では、ウエハ105を薄くした後、所
望半導体素子をウエハ105の表面に形成すれば、この
半導体素子が、基板102の表面に形成されたチップ1
05´の表面に配置される。
According to the present embodiment, the chip 105 'is
Is transferred to the substrate 102 after being transferred to the tape 107 ′. Therefore, the front and back sides of the semiconductor chip 105 ′ are opposite to those in the first embodiment, and the upper surface of the wafer 105 initially becomes the upper surface even when it is fixed to the substrate 102. Therefore, in this embodiment, if the desired semiconductor element is formed on the surface of the wafer 105 after the wafer 105 is thinned, the semiconductor element is formed on the chip 1 formed on the surface of the substrate 102.
05 ′.

【0037】[0037]

【発明の効果】上記説明から明らかなように、本発明に
よって下記効果が得られる。
As apparent from the above description, the following effects can be obtained by the present invention.

【0038】(1)半導体ウエハの主面に沿って移動す
る高速なエッチ液によって、ウエハが薄くされるので、
膜厚が均一な薄いウエハを容易に得ることができ、歪や
欠陥が発生する恐れはない。
(1) Since the wafer is thinned by the high-speed etchant moving along the main surface of the semiconductor wafer,
A thin wafer having a uniform film thickness can be easily obtained, and there is no possibility that distortion and defects occur.

【0039】(2)薄いチップの、上記テープからの剥
離と基板上への接着が同一の工程で行われるため、薄い
チップを割ることなしに、基板上に固着できる。
(2) Since the peeling of the thin chip from the tape and the bonding to the substrate are performed in the same process, the thin chip can be fixed on the substrate without breaking the thin chip.

【0040】(3)所望のチップを選択的に加熱および
加圧して上記基板上に移すので、極めて容易かつ低コス
トで、薄いチップを基板へ実装できる。
(3) Since a desired chip is selectively heated and pressed and transferred onto the substrate, a thin chip can be mounted on the substrate extremely easily and at low cost.

【0041】(4)異方導電性接着剤によって基板に固
着することにより、ワイヤボンディングなしに、各チッ
プを基板上に接続できる。
(4) Each chip can be connected to the substrate without wire bonding by being fixed to the substrate with an anisotropic conductive adhesive.

【0042】(5)チップの厚さは、曲げが可能である
0.1から110μmと極めて薄くされるので、曲げに
強い薄いの半導体装置を実現できる。
(5) Since the thickness of the chip is extremely thin, from 0.1 to 110 μm, which enables bending, a thin semiconductor device which is strong against bending can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示す図、FIG. 1 shows an embodiment of the present invention;

【図2】従来の方法を説明するための図、FIG. 2 is a diagram for explaining a conventional method.

【図3】本発明の実施例を説明するための平面図、FIG. 3 is a plan view for explaining an embodiment of the present invention;

【図4】本発明を説明するための図、FIG. 4 is a diagram for explaining the present invention;

【図5】本発明におけるウエハの薄形化を説明するため
の図、
FIG. 5 is a diagram for explaining thinning of a wafer according to the present invention;

【図6】本発明の他の実施例を示す工程図、FIG. 6 is a process chart showing another embodiment of the present invention;

【図7】本発明の他の実施例を示す工程図。FIG. 7 is a process chart showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

101…枠、 101´…第2の枠、 102…基板、
103…接着剤、104…ダイシング溝、 105…
ウエハ、 105´…チップ、106…加熱ヘッド、
107…テープ、 107´…第2のテープ、201…
真空チャック、 202…チップ、 203…テープ、
204…突き上げピン、 304…ウエハの周囲、 4
05…パッド、406…電極間導電粒子、 408…パ
ッシベーション膜、409…有機フィルム、 410…
導電粒子、 412…基板電極、501…エッチ液ノズ
ル、 502…エッチ液。
101 ... frame, 101 '... second frame, 102 ... substrate,
103: adhesive, 104: dicing groove, 105:
Wafer, 105 ': chip, 106: heating head,
107 ... tape, 107 '... second tape, 201 ...
Vacuum chuck, 202: chip, 203: tape,
204: push-up pin, 304: around the wafer, 4
05: pad, 406: conductive particles between electrodes, 408: passivation film, 409: organic film, 410:
Conductive particles, 412: substrate electrode, 501: etch liquid nozzle, 502: etch liquid.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 ダイシングにより完全に分離され、ウエ
ハ状態のままの配置でダイシングテ−プに貼付された複
数のICチップを準備する工程と、配線が形成された基
板と前記ダイシングテ−プに貼付されたままの状態の前
記ICチップの1つとを対向させる工程と、前記基板に
対向する前記ICチップを選択的に加熱圧接することに
より、前記基板と前記ICチップとを固定する工程とを
有することを特徴とする実装方法。
A step of preparing a plurality of IC chips which are completely separated by dicing and are attached to a dicing tape in an arrangement in a wafer state; Having a step of facing one of the IC chips in a standing state and a step of fixing the substrate and the IC chip by selectively heating and pressing the IC chip facing the substrate. A mounting method characterized by the following.
【請求項2】 前記基板と前記ICチップとの固定は、
接着剤により行うことを特徴とする請求項1記載の実装
方法。
2. The fixing of the substrate and the IC chip,
2. The mounting method according to claim 1, wherein the mounting is performed using an adhesive.
【請求項3】 前記接着剤は、異方導電性接着剤である
ことを特徴とする請求項2記載の実装方法。
3. The mounting method according to claim 2, wherein the adhesive is an anisotropic conductive adhesive.
【請求項4】 完全に分離され、ウエハ状態のままの配
置でテ−プに貼付された複数のICチップを準備する工
程と、配線が形成された基板と前記テ−プに貼付された
ままの状態の前記ICチップの1つとを対向させる工程
と、前記基板に対向する前記ICチップを加熱ヘッドで
押し出して前記基板に圧接する工程とを有することを特
徴とする実装方法。
4. A step of preparing a plurality of IC chips which are completely separated and adhered to a tape in an arrangement in a state of a wafer, and wherein a substrate on which wiring is formed and the IC chip is adhered to said tape. And a step of extruding the IC chip facing the substrate with a heating head and pressing the IC chip against the substrate.
【請求項5】 前記加熱ヘッドは、表面が平坦であるこ
とを特徴とする請求項4記載の実装方法。
5. The mounting method according to claim 4, wherein the heating head has a flat surface.
【請求項6】 ダイシングにより完全に分離され、ウエ
ハ状態のままの配置でダイシングテ−プに貼付され、厚
さが0.1μm〜110μmの範囲である複数のICチ
ップを準備する工程と、配線が形成された基板と前記ダ
イシングテ−プに貼付されたままの状態の前記ICチッ
プの1つとを対向させる工程と、前記基板に対向する前
記ICチップを選択的に加熱圧接することにより、前記
基板と前記ICチップとを固定する工程とを有すること
を特徴とする実装方法。
6. A step of preparing a plurality of IC chips which are completely separated by dicing, adhered to a dicing tape in an arrangement in a wafer state, and have a thickness in a range of 0.1 μm to 110 μm; A step of causing the formed substrate to face one of the IC chips that are still attached to the dicing tape; and selectively heating and pressing the IC chip facing the substrate to form a contact with the substrate. Fixing the IC chip.
【請求項7】 完全に分離され、ウエハ状態のままの配
置でテ−プに貼付され、厚さが0.1μm〜110μm
の範囲である複数のICチップを準備する工程と、配線
が形成された基板と前記テ−プに貼付されたままの状態
の前記ICチップの1つとを対向させる工程と、前記基
板に対向する前記ICチップを加熱ヘッドで押し出して
前記基板に圧接する工程とを有することを特徴とする実
装方法。
7. A wafer which is completely separated and affixed to a tape in an as-wafer arrangement, and has a thickness of 0.1 μm to 110 μm.
Preparing a plurality of IC chips in the range of: a step of making the substrate on which the wiring is formed face one of the IC chips which is still attached to the tape; Extruding the IC chip with a heating head and pressing the IC chip against the substrate.
JP33671999A 1995-05-18 1999-11-26 Implementation method Expired - Fee Related JP3197884B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33671999A JP3197884B2 (en) 1995-05-18 1999-11-26 Implementation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33671999A JP3197884B2 (en) 1995-05-18 1999-11-26 Implementation method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP12023695A Division JP3197788B2 (en) 1995-05-18 1995-05-18 Method for manufacturing semiconductor device

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JP2000150544A true JP2000150544A (en) 2000-05-30
JP3197884B2 JP3197884B2 (en) 2001-08-13

Family

ID=18302092

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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2823012A1 (en) * 2001-04-03 2002-10-04 Commissariat Energie Atomique METHOD FOR THE SELECTIVE TRANSFER OF AT LEAST ONE ELEMENT FROM AN INITIAL MEDIUM TO A FINAL MEDIUM

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2823012A1 (en) * 2001-04-03 2002-10-04 Commissariat Energie Atomique METHOD FOR THE SELECTIVE TRANSFER OF AT LEAST ONE ELEMENT FROM AN INITIAL MEDIUM TO A FINAL MEDIUM
WO2002082502A3 (en) * 2001-04-03 2003-11-06 Commissariat Energie Atomique Method for selectively transferring at least an element from an initial support onto a final support
US6959863B2 (en) 2001-04-03 2005-11-01 Commissariat A L'engergie Atomique Method for selectively transferring at least an element from an initial support onto a final support
CN1322575C (en) * 2001-04-03 2007-06-20 法国原子能委员会 Method for selectively transferring at least an element for initial support onto a final support

Also Published As

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JP3197884B2 (en) 2001-08-13

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