JP2000132584A - Hdl input method and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an HDL description input system reducing the burden on a designer for the HDL(hardware description language) description and preventing a grammar error of the designer. SOLUTION: An HDL syntax data base 104a having the models of respective HDL syntaxes and an associated design data base 104b having connection information between circuits are installed. An HDL syntax generation part 100c generating the HDL syntax from the data base 104a with the reservation word of HDL which a designer inputs as a key, an associated description generation part 100d generating the HDL syntax from the model of the HDL syntax and circuit information when circuit information required for input exists in the data base 104b, an associated description correction part 100e correcting an affected HDL text file from the data base 104b when the correction of the generated HDL text file 104c affects the other HDL text file and a semantics check part 100f checking semantics having no problem in terms of a circuit, are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the development of a circuit design using HDL.

[0002]

2. Description of the Related Art The number of gates that can be mounted on one chip has been increasing due to the progress of semiconductor manufacturing technology. Under these circumstances, instead of the conventional design method based on gate-level circuit diagram input, a design method using HDL that can express functional levels higher than the gate level has been shifted. HDL
While the design method allows for a high level description, the designer can use HDL
There is the complexity of having to learn the grammar and input the circuit description that satisfies the function while paying attention to the syntax.

[0003] One method for solving the above problems is as follows.
Japanese Patent Application Laid-Open No. Hei 6-314314 discloses an input device for creating an HDL by giving a circuit function and a target value of a generated circuit.

[0004]

In circuit design using HDL, a designer must learn HDL grammar and input.

Therefore, it is necessary to input data while paying attention to the syntax of the HDL grammar. If there is little experience in HDL design, a description error is likely to occur.

If a description is changed due to a logic defect or a specification change, and other changes need to be corrected in connection with the change, even a designer skilled in HDL design may miss it.

Japanese Patent Application Laid-Open No. 6-314314 has a low degree of freedom in description, and does not cope with a change in description of a related part due to a logical change or the like.

[0008] The present invention is an HDL input system that solves the above-mentioned conventional problems and reduces the burden on designers.

[0009]

In order to solve the above-mentioned problems, the present invention provides a database having a model of each HDL syntax and a means of referring to a database having connection information between circuits. Using the HDL reserved words input by
A means for generating an HDL syntax from a database having DL syntax template information, and an HDL syntax generated from a HDL syntax template and circuit information when there is circuit information required for input in a database with connection information between circuits To do and the already created H
If the modification of the DL text file affects other HDL text files, there are two ways to modify the HDL text file that affects the database from the connection information between circuits, and to perform a semantics check on the circuit for problems. provide.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

<Description of FIG. 1> FIG. 1 is a configuration diagram of an HDL description input device.

The HDL input program 100a is stored in the main storage device 100. HDL stored in main storage device 100
CPU 101 for processing input program 100a, HDL
Display 10 for displaying an input screen of an input program
2. Keyboard 10 for designer to input HDL
3. An HDL syntax database 104a having template information for generating an HDL syntax from HDL reserved words, and an HDL text file 1 already created due to a function change, a logic defect, or the like.
04c is modified to another HDL text file 104c
If it is necessary to modify the HDL text file 104c, the HDL input program 100 and the related design database 104b having the input / output terminal information of the circuit and the related circuit name information for detecting the modification portion of the HDL text file 104c and modifying the HDL.
The hard disk 104 stores an HDL text file 104c generated from a. The devices are connected by a bus 105.

A designer (operator) inputs HDL reserved words and circuit information from the keyboard 103. The display 102 displays the HDL character string (reserved word or logical description) input by the designer on the input screen of the HDL input program 100a. The HDL input program 100a uses a character string input from the keyboard 103 as input data and
At 101, an instruction of the HDL input program 100a is executed. The HDL syntax is generated based on the information of the HDL syntax database 104a and the related design database 104b stored in the hard disk 104 according to the instruction.

When the designer determines that the HDL description has been completed, the designer instructs the HDL input program 100a to output the HDL text file 104c and outputs it to the hard disk 104.

<Description of FIG. 2> FIG. 2 is a configuration diagram of the HDL input program 100a.

The HDL input / output unit 100b includes a keyboard 10
The character string data which is a reserved word of HDL inputted from 3 is received. Next, the character string data is passed to each processing unit to control the HDL input program 100a. The HDL text file 104c created by the processing of the HDL input program 100a is output to the hard disk 104.

The input data of the HDL syntax generator 100c is character string data (reserved words) received from the HDL input / output unit 100b. HD using the received character string data as a key
The HDL syntax is generated from the template information of the corresponding character string data with reference to the L syntax database 104a and returned to the HDL input / output unit 100b.

The related description generator 100d receives character string data (reserved words and circuit names) related to the hierarchical description from the HDL input / output unit 100b. Using the received character string data (circuit name) as a key, the related design database 104b is searched, and if there is character string data (circuit name), information necessary for the HDL syntax is created from the related design database 104b. HL syntax template information is extracted from the HDL syntax database 104a using the (reserved word) as a key and merged with the related design database 104b to generate an HDL syntax.
Return to the DL input / output unit 100b.

The related description correction unit 100e performs processing when correcting the HDL text file 104c that has already been created. HDL text file 104c already created
When the terminal name is changed or the terminal is added or deleted from the input / output terminal description, the circuit name and the terminal information are received from the HDL input / output unit 100b. HD whose terminal has changed
The related design database 104b is searched using a circuit name which is not described in any place other than the L text file 104c or whose terminal has been changed as a key. As a result of the search, if the terminal is used in another HDL text file 104c, the description is changed in the same manner as the changed terminal and returned to the HDL input / output unit 100b.

The semantics check section 100f is H
The signal declaration input by the designer from the DL input / output unit 100b
Character string data of input / output terminal information is used as input data. Each of the signal declaration / input / output terminal information and the signal terminal information of the logic description part is stored in the work area 100g of the HDL input program 100a. Then, the respective signal / terminal information is compared to check whether there is an excess / shortage signal / terminal description. If there is an excess / shortage, a message is output.

<Description of FIG. 3> FIG. 3 shows the data structure of the HDL syntax database 104a.

The HDL syntax database 104a has an HD
L syntax generation unit 100c and related description generation unit 100d
Used to generate L syntax. The HDL syntax database 104a searches the HDL syntax database 104a for the reserved word 302 using the HDL character string (reserved word) input by the designer as a key. If there is a reserved word 302 that matches the character string input by the designer, an HDL syntax is generated from syntax information (model) 303 corresponding to the reserved word.

The HDL syntax database 104a has a VHD
A language type 301 for identifying a reserved word of L or Verilog HDL, and VHDL or Verilo.
It is composed of a reserved word 302 of gHDL and syntax information (model) 303 of the reserved word 302.

For example, assume that the designer inputs 'entity'. The HDL syntax generation unit 100c receives the input character string 'ent
A search is made for the language type 301VHDL / reserved word 302'entity 'in the HDL syntax database 104a using the' ity 'as a key.
When “entity” is detected as a result of the search, an HDL syntax is generated from the “entity” syntax information (model) 303.

The HDL syntax database 104a is prepared in advance as a database.

<Description of FIG. 4> FIG. 4 shows the data structure of the related design database 104b.

The related design database 104a is used by the related description generating unit 100d and the related description correcting unit 100e. The related design database 104a includes a circuit name 401 of the input HDL description, a terminal name 402 of the circuit, a terminal direction 403, a terminal attribute 404, and related circuit information 405. The circuit name 401 is a name given to the circuit. In the case of VHDL, it is a circuit name declared by the reserved word 'entity'. In the case of verilog HDL, it is a circuit name declared by the reserved word 'module'.

The terminal name 402 is the name of the input / output terminal attached to the circuit. Terminal direction 403 is a terminal is an input terminal
(In case of VHDL, in case of verilog HDL i
output terminal (out, ve for VHDL)
This is information on the terminal direction for determining whether or not the output is rilog HDL. The terminal attribute 404 indicates the attribute of the terminal. For example, std_logic type or std_logic_v
Indicates the type of signal such as the ector type. The terminal names 402, the terminal directions 403, and the terminal attributes 404 are generated for the number of terminals of the circuit.

Registration of the related design database 104b is as follows.
When the circuit description is completed and the HDL text file 104c is output, the circuit name 401, the terminal name 402, and the terminal direction 4
03 ・ Terminal attribute 404 to HDL text file 104
c and performs registration processing. In the case of VHDL, a circuit name is created from an “entity” statement, and terminal information is created from a “port” statement.
In the case of verilog HDL, a circuit name is created from a 'modul' statement and 'input', 'output', and 'inout' statements. The related circuit information 405 stores the HDL text file 10 that is referred to when the circuit terminal of the already created HDL texter file 104c is used by another related description generation unit 100d.
4c is registered.

In the case of FIG. 4, the circuit name "ADD" is the terminal name 40.
2'IN1 ', terminal direction 403'in', terminal attribute 404
It has a terminal of 'std_logic', and the circuit name 401 'ADD' indicates that the circuit name top is referring.

When there is a change in the terminal information in the related description correcting unit 100e, the terminal name 402, the terminal direction 403, and the terminal attribute 404 of the related design database 104b are also updated according to the change.

<Description of FIG. 5> FIG.
00c will be described.

When designing a circuit using HDL, the designer must learn the HDL grammar, and if the designer has little experience in HDL design, there is a problem that syntax mistakes are likely to be made.

Then, the HDL syntax generation unit 100c generates an HDL syntax from the syntax information (model) 303 of the HDL syntax database 104a using the HDL reserved word input by the designer as a key. For this reason, designers can use HDL reserved words only
Can be described, the burden of learning the HDL grammar can be reduced, and syntax mistakes can be prevented.

The input screen 501 is a reserved word 'en' that allows the designer to specify the interface (input / output terminal) of the circuit in VHDL.
You have just typed 'tity'. Then, the designer issues a syntax generation instruction (for example, pressing an escape key on a keyboard). The HDL syntax generator 100c receives the character string 'entity'. Using the received character string 'entity' as a key, the language type 301 'VHDL' in the HDL syntax database 104a,
The reserved word 302 'entity' is searched. Search results for 'en
tity 'is detected from the syntax information (model) 303
Generate a template for 'entity'. Input screen 502 is' enti
This shows where the template of ty 'is displayed.

The designer inputs information necessary for circuit design (“?” In FIG. 5) into the generated “entity” template syntax to complete the syntax. H from the HDL syntax generation unit 100c
A DL template is generated, and the designer does not need to pay attention to the syntax, and even a designer with little experience can prevent a syntax error.

<Description of FIG. 6> The processing of the HDL syntax generation unit 100c will be described in detail using the processing flow of the HDL syntax generation unit 100c.

In Step 600, the character string input from the input screen is searched for the language type 301 and the reserved word 302 in the HDL syntax database 104a using the character string which is a reserved word of HDL as a key. In the case of the input screen 501, the language type 301 'VHDL'
Search the HDL syntax database 104a using the reserved word 302'entity 'as a key.

Step 601 is an HDL syntax database 1
The search result of 04a is determined. If the corresponding reserved word 302 is found from the HDL syntax database 104a as a result of the search, the HDL syntax database 104 is searched in Step 602.
A model of a character string (reserved word) is displayed on the input screen from the syntax information (model) 303 of a. Input screen 502 is' entit
This indicates that a template of 'entity' is displayed from the syntax information (model) 303 of 'y'.

If the corresponding reserved word 302 is not detected as a result of the search of the HDL syntax database 104a in Step 601, a warning message indicating that there is no corresponding reserved word (input character) is output in Step 603.

Step 604 returns to the input mode of the input screen, and then the designer inputs circuit information (“?” In FIG. 5) to the generated HDL syntax model to complete the description.

<Description of FIG. 7> FIG.
00d represents the principle.

In the case of hierarchical description in HDL, it is necessary to describe terminal information in a circuit description of an upper layer based on circuit terminal information of a lower layer. Even designers who have experience with HDL may omit the description of terminal information or make a description error. The related description generation unit 100d determines that the lower-level HDL text file 104c has been created and the related design database 1
If the terminal information has already been registered in 04b, an HDL syntax is generated from the terminal information (terminal name 402, terminal direction 403, terminal attribute 404) of the related design database 104b and the HDL syntax database 104a. This can prevent omission of description of terminals and description errors.

In step 701, a designer inputs a reserved word 'component' for expressing hierarchy in VHDL from an input screen, then describes a circuit name (ADD in this example) of a lower hierarchy, and instructs syntax generation (hereinafter referred to as ADD). The syntax generation instruction means pressing the escape key on the keyboard). Next, a search is made for a circuit name 401 as to whether a circuit 'ADD' has been created in the related design database 104b. As a result of the search, if the lower-level description “ADD” is registered, if the terminal name 402 of the related design database 104 b
The terminal information necessary for the 'component' statement is created from the terminal direction 403 and the terminal attribute 404.

Further, the syntax information (model) 303 of the reserved word 'component' sentence is detected from the HDL syntax database 104a to form a model. The terminal information generated from the related design database 104b and the syntax information (model) 303 detected from the HDL syntax database 104a are merged to generate a 'component' statement shown on an input screen 702.

'AD' is stored in the related design database 104b.
If there is no D 'circuit information, the' co
mponent 'Generate only the template of the sentence'? In the 'part, the designer describes the terminal information by himself.

When circuit information of a lower hierarchy is already registered in the related design database 104b.
00d creates an HDL syntax, which can prevent omission of description and description error.

<Description of FIG. 8> The processing of the related description generation unit 100d will be described in detail with reference to the processing flow chart of the related description generation unit 100d.

Step 800 is related design database 1
Search for the circuit name 401 of 04b. In the case of the input screen 701, the character string 'ADD' is used as a key and the related design database 10
It is searched whether 'ADD' is registered in the circuit name 401 of 4b.

If data is registered in the circuit name 401 as a result of the search in Step 801, Step 802 determines the terminal information (terminal name 4) in the related design database 104 b.
02, terminal direction 403, terminal attribute 404)
Create the data required for the port statement of the 'ent' syntax. In the case of the input screen 702, “IN1”, “IN1”, “IN1”,
The terminal information of IN2 'and' S 'is extracted. (In the terminal information of FIG. 4, only “IN1” is described, but the terminal information of “IN2” and “S” is repeated after “IN1”.) Step 803 reads the reserved word “component” statement from the HDL syntax database 104a. The syntax information (model) 303 is extracted and merged with the terminal information created in Step 802 to complete the 'component' statement and display it on the input screen. The input screen 702 is a “comp” generated by merging the template of the “component” syntax and the terminal information (IN1, IN2, S).
onent 'statement.

In step 801, the related design database 1
If there is no related description in 04b, a warning message to the effect that there is no relevant information in Step 804 is output.

In step 805, the process shifts to the HDL syntax generation unit 100c to generate a template of the HDL syntax, and generates a template of the 'component' statement and displays it on the input screen in the same manner as the process described with reference to FIG.

<Description of FIG. 9> FIG.
00e.

The terminal description of the circuit may be changed due to a change in logic or the like. When the terminal information is used in another HDL text file 104c using the circuit whose description has been changed, the terminal description of the other HDL text file 104c describing the changed terminal information must be similarly changed. In this way, the terminal information of the changed part is
When used in the text file 104c, another H
There is a risk that the DL text file 104c may be omitted or changed incorrectly.

The related description correction unit 100e searches the relevant design database 104b for a correction location that is not used in another HDL text file 104c, and changes the terminal description if it is used. The related description correcting unit 100e can prevent omission or incorrect correction of the terminal description of another HDL text file 104c which is affected by the terminal description correction.

Reference numeral 901 denotes an output terminal 'OU' for a circuit name 'ADD'.
It is the figure which showed T 'and added correction. Reference numeral 901a denotes a description before correction. The terminals of the circuit are three terminals'IN1''IN2''S'. 901b is the output terminal 'OU' in the description of 901a.
FIG. 14 is a diagram showing that T ′ is additionally corrected and changed to four terminals. 902 is a diagram showing that “OUT” has been added to the output terminal of the circuit name “TOP” which is another HDL text file 104c referring to the circuit “ADD” due to the description change of 901. Reference numeral 902 denotes a description expressing a circuit hierarchy. Reference numeral 902a is an upper layer description, which is a structural description using a lower layer circuit 'ADD' of the 901a by a 'component' statement, and shares terminal information of 'ADD'. 902b is 9
01b, the output terminal 'OUT' has been added.
Indicates that the output terminal 'OUT' has been added to the 'port' statement of the 'omponent' statement 'ADD'.

Since the description of the terminal has been changed in 901b, the terminal information (terminal name 402) in the related design database 104b has been changed.
The terminal direction 403 and the terminal attribute 404) are updated. 90
In the case of 2, the circuit name 40 of the related design database 104b
1 Add the terminal information 'OUT' to the 'ADD' record.

Next, if there is a circuit name in the related circuit information 405 of the circuit name 401'ADD 'in the related design database 104b, the HDL text file 104c of the circuit name registered in the related circuit information 405 is stored in the HDL input program 100a. Change the terminal description related to reading.

In the case of FIG. 9, when the circuit “TOP” HDL text file 104c is created, “TOP” is added to the related circuit information 405.
Is registered. The HDL text file 104c of the circuit 'TOP' is read and an output terminal 'OUT' is added.

The related description correction unit 100e is the H
By changing the DL text file 104c, other HDL
Whether the text file 104c needs to be modified is searched from the related design database 104b, and if there is an HDL text file 104c that needs modification, the modification is performed. As a result, it is possible to prevent a change leak or a change mistake.

<Description of FIG. 10> Related description correction unit 100e
The processing of the related description correcting unit 100e will be described in detail with reference to the processing flowchart of FIG.

Since the input / output terminal description of the circuit is changed in Step 1000 due to a design change or the like, the circuit name 401 in the related design database 104b is searched using the circuit name being changed as a key. In the case of FIG. 9, the circuit name 401 of the related design database 104b is searched using the circuit name 401'ADD 'as a key.

The step 1010 updates the data by adding the terminal information 'OUT' to the circuit name 401 'ADD' record of the related design database 104b. In the case of FIG. 9, the terminal name 402'OUT 'and the terminal direction 403'out'
A terminal attribute 404 'std_logic' is added.

Step 1020 searches the related circuit information 405 of the related design database 104b, and retrieves the related path information 40.
5 is searched for a registered circuit name. In the case of FIG. 9, the circuit name 'TOP' is registered in the related circuit information 405. (Registration of the related circuit information 405 is performed by setting the circuit name 'TOP' to H
'Component' when creating DL text file 104c
When the circuit name is registered in the related circuit information 405 (registered in the related description generation unit 100d when describing the 'ADD' of the sentence), the HDL text file 104 of the circuit name is registered.
c into the HDL input program 100a,
Change data is created from the terminal information (terminal name 402, terminal direction 403, terminal attribute 404) updated in p1010, and the terminal description is changed. In the case of 902b in FIG.
Terminal information 'OUT' is added.

In Step 1040, if the circuit name is not registered in the related circuit information 405 as a result of searching the related design database 104 b in Step 1020, the process returns to the normal input mode and the designer returns to the HDL input program 10.
Input is performed from the input screen 0a.

<Description of FIG. 11> FIG. 11 illustrates the principle of the semantics check unit 100f.

In the circuit design, a simulation is performed using a simulator to determine whether the designed circuit operates correctly. In simulation, VHDL 'process' statement, Verio
The change of the signal of the sensitivity list included in the 'always' statement of the lgHDL is verified. Therefore, the signal on the right side of the signal assignment statement or the signal in the conditional expression needs to be described in the sensitivity list. (However, in the case of VHDL, 'wai
(If the description of the 't' statement is in the 'process' statement, it cannot be described.)
Even if it is not a beginner of the HDL description, there is a possibility that the description of the sensitivity list may be lost, which is a problem in the circuit verification process. The semantics check unit 100f detects a signal necessary for the sensitivity list and creates a sensitivity list. As a result, it is possible to prevent the creation of an incomplete sensitivity list and prevent problems in the circuit verification process.

If there is a leak in the description of the sensitivity list as in 1101, the signal on the right side of the signal assignment statement or in the conditional expression is added to the sensitivity list as in 1102. (The sensitivity list is 'process'
In the case of FIG. 11, “B” SEL ”is not described in the sensitivity list in the case 1101 of FIG. Add B''SEL 'to the sensitivity list.

Reference numeral 1103 in FIG. 11 checks unused signals and terminals. In 1103, 'A_
Although described as SIG ', it is not used in the function description part (in the process statement). If such a description is left, unnecessary terminals may be generated and the area of the circuit may be increased, and the quality of the circuit may be degraded. If such unused signals / terminals exist, a warning message is output. The designer can check for unnecessary terminals and signals in the description by the warning message, and can prevent the quality of the circuit from deteriorating.

<Description of FIG. 12> The processing of the semantics checking unit 100f will be described in detail using the processing flow of the semantics checking unit 100f.

Step 1200 is an HDL syntax generation unit 100
A 'process' statement and an 'always' statement are generated by the processing of c.

Step 1210 is the generated 'proces
The designer describes the function of the circuit from the input screen of the HDL input program 100a in the 's' and 'always' statements. At this time, the signal information in the sensitivity list is
And the signal information on the right side of the conditional expression and the signal assignment statement are stored as a table B in the work area 100g.

At Step 1220, when the function description is completed, the signal information (table
A) is compared with the signal information (table B) on the right side of the conditional expression or signal assignment statement, and if there is a description omission in the sensitivity list, data is created from table B and added to the sensitivity list.

Work area 10 in the case of 1101 in FIG.
'A' in table A of 0g, work area 100g
'A''B''SEL' is stored in the table B. As a result of the comparison between table A and table B, 'B''SEL' not stored in table A is added to the sensitivity list.

Step 1230 uses the signal declaration or input / output terminal information as signal / terminal information data in work area 1.
Store it in table C of 00g. Step 1240 stores the signal information of the function description section as signal information data in table D of work area 100g.

Step 1250 compares the signal / terminal information data (table C) with the signal information data (table D). In Step 1250, if there is an excess or deficiency in the registered data as a result of comparing the table C and the table D, a warning message is output for the information of the excess or deficient signal / terminal.

In the case of 1103 in FIG. 11, the signal / terminal information data (table C) contains' port 'information'I1''I2''SE
L "O1" and signal information "A_SIG" are stored. 'I1 "I2" SEL "O1" of the function description part (in the process statement) is stored in the signal information data (table D). Although the comparison result 'A_SIG' of table C and table D declares a signal, it is determined to be an unused signal and a warning message is output for 'A_SIG'.

[0078]

According to the present invention, as described above, HDL
In designing a logic using HDL, it is possible to solve the problems of the above-mentioned conventional method and to design using HDL description.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of an HDL input system.

FIG. 2 is a program configuration diagram of an HDL input system.

FIG. 3 shows a data structure of an HDL syntax database.

FIG. 4 shows a data structure of a related design database.

FIG. 5 illustrates the principle of an HDL syntax generation unit.

FIG. 6 is a processing flowchart of an HDL syntax generation unit.

FIG. 7 illustrates the principle of a related description generation unit.

FIG. 8 is a processing flowchart of a related description generation unit.

FIG. 9 illustrates the principle of a related description correction unit.

FIG. 10 is a processing flowchart of a related description correction unit.

FIG. 11 illustrates the principle of a semantic check unit.

FIG. 12 is a processing flowchart of a semantic check unit.

[Explanation of symbols]

 100: main storage device, 100a: HDL input system, 100b: HDL input / output unit, 100c: HDL syntax generation unit, 100d: related description generation unit, 100e: related description correction unit, 100f: semantics check unit, 101: CPU, Reference numeral 102: display, 103: keyboard, 104: hard disk, 104a: HDL syntax database, 104b: related design database, 104c: HDL text file, 105: bus, 301: language type, 302: reserved word, 303: syntax information (model) ), 401: circuit name, 402: terminal name, 403: terminal direction, 404: terminal attribute, 405: related circuit information, 501: initial input screen, 502: HDL syntax generation screen, 701: initial input screen, 702: automatic Generation screen (with related information), 703 ... 901: Description change input screen, 901a: Description change input screen, 901b: Description change input screen, 902: Related description side input screen, 902a: Automatic change before input screen, 902b ... Input screen after automatic change, 1101 ... input screen before automatic generation, 1102 ... input screen after automatic generation, 1103 ... description example of semantic checks.

Claims (5)

[Claims] 1. A hardware description language (hereinafter referred to as HDL)
An HDL input device for designing a circuit using the HDL includes a database having a template of the syntax of each HDL and a means for referring to a database having connection information between the circuits, and a HDL input device which is input by a designer. A program that generates HDL syntax from reserved words, a program that generates HDL syntax by generating circuit information from a database containing information related between circuits, and a program that changes existing HDL text files to other HDL
An HDL input device including a program for correcting a relevant part when a text file is related, and a program for checking a semantics of a circuit. 2. The program according to claim 1, wherein a database having a template of an HDL syntax is searched using a reserved word of the HDL inputted by a designer as a key, and an HDL syntax of the reserved word is generated from the template. . 3. An HDL input device according to claim 1, wherein when circuit information necessary for input is registered in a database having connection information between circuits, an HDL syntax is generated from a model of the HDL syntax and the circuit information. Program to do. 4. The HDL input device according to claim 1, wherein a change is made to an already created HDL text file due to a function change, a logic defect, or the like so that another HDL text file does not need to be changed or not. A program that searches a database with information and changes other HDL text files if needed. 5. The HDL description input device according to claim 1, wherein an unused signal is described, and a process statement or an alternative which influences a simulation result at a function level / gate level.
A program that performs semantics-checking of sensitive sentimentists in s statements.