JP2000091307A - Etching method for semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make etching treatment where semiconductor such as silicon is dipped in etching liquid a process superior in controllability. SOLUTION: In etching equipment 1, TMAH aqueous solution 3 of 22 wt.% is kept at 80 deg.C in an etching bath 2, and a silicon wafer 6 is dipped and treated by etching. At this time, in smoothing etching treatment, a specified potential Va to a reference electrode 7c is applied to a silicon where 6 via a potential applying electrode 7a by using a potentiostat 7. When Miller indices of the silicon wafer 6 are (110), by setting the applying potential Va at a negative side from a rest potential Vr, etching restraining generation of micropyramids is enabled, and an etching surface is smoothed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor etching method for performing an etching process by immersing a semiconductor in an etchant.

[0002]

Among the conventional methods for etching silicon as a semiconductor, a method for performing anisotropic etching is disclosed, for example, in Japanese Patent Laid-Open No. 3-201.
No. 533 is disclosed. This uses a material that does not contain alkali metal ions as an anisotropic etchant so as to be compatible with the semiconductor manufacturing process. Specifically, an anisotropic etchant using an aqueous solution of tetramethylammonium hydroxide (TMAH) is used. It is.

The TMAH aqueous solution is used in a state where the temperature and the concentration are adjusted, and particularly, the concentration is 20 to 50%.
It has been found that the range of wt% is appropriate. In this case, the etching rate tends to increase on the low concentration side. For example, an aqueous solution of 22 wt% as a concentration that can achieve stable conditions within this range may be used as the silicon anisotropic etching solution.

[0004] However, in the anisotropic etching of silicon using the TMAH aqueous solution on the low concentration side, even if the etching surface is not roughened under the set conditions, Temperature as the etching condition and TMA with progress of etching
Due to fluctuations in the concentration of the H aqueous solution, micro-pyramids may be formed on the etched surface of the silicon substrate after etching, or a pattern having streaky irregularities may be formed after etching.

Therefore, even when a slight change in etching conditions occurs with the progress of the etching process as in a production line, if the smoothness of the etched surface needs to be stably obtained with good reproducibility, the requirement is satisfied. There is a problem that it is difficult to satisfy the above, and there is a surface that process controllability is poor as a whole.

Such a problem becomes an important problem when performing anisotropic etching for forming a diaphragm such as a semiconductor pressure sensor. That is, the diaphragm is formed so as to have a desired thickness by removing most of the thickness of the silicon substrate by etching, but in order to obtain sensitivity characteristics with respect to pressure accurately, etching of the diaphragm is performed. The surface must be formed smoothly. This is because if irregularities such as micro pyramids are formed on the etched surface, a problem such as a variation in accuracy of pressure detection occurs even if the thickness of the diaphragm is formed as specified.

On the other hand, as a method of eliminating the occurrence of roughness on the etching surface and finishing the surface with a smooth etching surface, there is a method disclosed in Japanese Patent Application Laid-Open No. Hei 8-13165, for example. In this method, a silicon substrate is immersed in an ammonium fluoride (NH ₄ F) solution, and an etching process is performed while applying a potential to the silicon substrate. The applied potential is controlled to, for example, a rest potential or less. This is a microfabrication technology that achieves atomic level flatness.

However, an aqueous solution of ammonium fluoride as an etching solution used in the above method is
Originally, the etching rate is low, and furthermore, because it contains fluorine ions, it becomes difficult to perform heat treatment in terms of safety in the semiconductor manufacturing process,
There are aspects such as poor workability.

Also, unlike the above-described etching process for forming a diaphragm of a pressure sensor, it is conceivable to actively use a micropyramid generated on the surface of a silicon substrate by an etching process using a TMAH aqueous solution. In other words, on the surface of the silicon substrate, for example, microscopic irregularities such as micropyramids are formed in a region where an ohmic contact is formed to increase a contact area, or fine irregularities are formed in an adhesive surface portion and an adhesive is used. Roughening treatment, such as increasing the contact area to increase the adhesive strength, may be considered.

However, even in such a case, for the same reason as described above, an etching process for stably generating a micropyramid cannot be performed as a manufacturing process, and in some cases, a micropyramid does not occur. There are problems that a relatively smooth surface is formed and that it is difficult to control the formation state of the micropyramid.

The present invention has been made in view of the above circumstances, and an object of the present invention is to smooth or roughen a finished state of an etched surface when etching a semiconductor such as a silicon wafer. It is an object of the present invention to provide a method of etching a semiconductor, which can perform the process with good controllability and improve the process controllability.

[0012]

According to the first aspect of the present invention, since the etching process is performed while a predetermined potential is applied to the semiconductor by using a quaternary ammonium hydroxide aqueous solution as an etching solution, the etching rate is secured to some extent. The etching process can be performed while controlling the finish of the etching surface while the etching solution does not contain alkali metal ions. Therefore, it is suitable for the semiconductor manufacturing process. It can be performed under conditions that do not hinder temperature setting and the like.

According to the second aspect of the present invention, when the smoothing etching process is performed, the plane orientation index of the main surface is (1).
When the silicon substrate of 10) is used as a semiconductor, the potential is given to the silicon substrate during the etching process by setting the potential to a negative side with respect to the rest potential. The etching proceeds so as to solve the problem, and the occurrence of micro-pyramids during the etching can be suppressed as much as possible, whereby process control can be performed so that the etched surface is formed to be a smooth surface. become able to.

According to the third aspect of the present invention, when the smoothing etching process is performed, the plane orientation index of the main surface is (1).
When the silicon substrate of (00) is used as a semiconductor, it is performed by setting the potential applied to the silicon substrate during the etching process to a potential between the passivation potential and the rest potential. While satisfying the condition that is not formed,
As the etching progresses to eliminate the unevenness of the etched surface, the generation of micro-pyramids during the etching can be suppressed as much as possible, thereby controlling the process so that the etched surface is formed as a smooth surface Can be performed.

According to the fourth aspect of the present invention, prior to performing each of the above-described smoothing etching processing steps, the silicon substrate is etched without applying a potential, so that the silicon substrate is etched in the smoothing etching processing step. Etching can be performed at an increased etching rate compared to the etching process. In this case, a relatively small amount of micropyramids and streaks that are expected to occur on the etched surface of the silicon substrate are smoothed as described above. Since the problem can be solved by the etching process, the time required for the etching process can be shortened and the finished etched surface can be formed as a smooth and good one.

According to the present invention, tetramethyl ammonium hydroxide (TM) is used as an etching solution.
AH) Since an aqueous solution is used and adjusted to a concentration in the range of 20 to 50% by weight, and further adjusted to a concentration of 22% by weight, damage to the etched surface during etching of the silicon substrate is relatively reduced. While
The etching rate can be relatively increased, and a process that does not include an alkali metal ion or the like can be performed, handling can be simplified in a semiconductor manufacturing process, and conditions can be set without being restricted by heating or the like. become.

According to the invention of claim 8, when the roughening etching process is performed, the plane orientation index of the main surface is (1).
When the silicon substrate of 10) is used as a semiconductor, it is performed by setting the potential applied to the silicon substrate during the etching process to a potential between the passivation potential and the rest potential, so that a micro pyramid is formed on the main surface of the silicon substrate. It is possible to form positively, and thereby, it is possible to perform process control so as to roughen the etched surface.

According to the ninth aspect of the present invention, when the roughening etching step is performed, the plane orientation index of the main surface is (1).
When the silicon substrate of (00) is used as a semiconductor, the potential is given to the silicon substrate during the etching process by setting the potential to a negative side of the rest potential, so that the micro-pyramid is actively formed on the main surface of the silicon substrate. , Whereby process control can be performed to roughen the etched surface.

According to the tenth and eleventh aspects of the present invention, the etching is performed in a state where a potential for setting the etching rate ratio with respect to the planes having different plane orientation indices is applied to the silicon substrate which is a semiconductor. The etching progress rate ratio between the plane orientation index of the substrate and the plane orientation index of the etched surface to be formed can be selected, thereby increasing the degree of freedom for etching into a desired shape, and controlling the etching process. The performance can be improved.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. In this embodiment, a silicon substrate as a semiconductor is used to obtain a smooth etched surface in both cases where the main surface has a plane orientation index of (110) and (100). The etching process will be described.

First, tetramethylammonium hydroxide (hereinafter referred to as TMAH) is used as the quaternary ammonium hydroxide as an etching solution used in the present embodiment, and this is used in place of the methyl group (-CH ₃ ). An alkyl group (C _n ) such as an ethyl group (—C ₂ H ₅ ), a propyl group (—C ₃ H ₇ ), or a butyl group (—C ₄ H ₉ ).
H _{2n + 1} ) may be used.

FIG. 1 shows a principle configuration of an etching apparatus 1 according to the present embodiment. An etching tank 2 contains a TMAH aqueous solution 3 as an etching solution. This TMAH aqueous solution 3 has a concentration of 20 to 50 wt%.
, And the concentration is adjusted to, for example, 22 wt%. The temperature of the TMAH aqueous solution 3 is controlled by heating and cooling by the temperature controller 4 so as to maintain the liquid temperature at a predetermined temperature, for example, 80 ° C., and the temperature distribution in the etching bath 2 becomes uniform. As described above, the stirrer 5 is arranged at the bottom in the tank, and the TMAH aqueous solution 3 is stirred by being rotated by the application of the rotating magnetic field.

As a silicon substrate as a semiconductor to be etched, an n-type silicon wafer 6 having a main surface with a plane orientation index of (110) or (100) is used, and a TMAH aqueous solution 3 in an etching bath 2 is used. Etching is performed in a state of being immersed in the substrate. Although only a single silicon wafer 6 is shown in the drawing, it is needless to say that a configuration in which a plurality of wafers are simultaneously processed can be employed when used in a manufacturing process.

In the smoothing etching process, the potential application electrode 7a of the potentiostat 7 is
And a predetermined potential Va (V v
s. Pt). In potentiostat 7,
In addition, a counter electrode 7b and a reference electrode 7c made of platinum (Pt) are provided. These are also immersed in the TMAH aqueous solution 3 and have a predetermined potential V set with respect to the potential of the reference electrode 7c.
a is applied to the potential application electrode 7a, and a current flows through the counter electrode 7b.

Next, a case where an etching process is performed using the present etching apparatus 1 will be described with reference to the following three embodiments. That is, (1) the etching process of the n-type silicon wafer 6 with the plane orientation index (110) performed in one step, and (2) the plane orientation index (11) performed in two steps.
There are three modes, ie, 0) the etching process for the n-type silicon wafer 6 and (3) the etching process for the n-type silicon wafer 6 with the plane orientation index of (100).

(1) Plane orientation index (1)
10) Smoothing etching of n-type silicon wafer 6 This is a TMAH aqueous solution 3 (22
wt.% and used at 80 ° C.), and anisotropically etching the n-type silicon wafer 6 having a plane orientation index of (110). At this time, the etching is performed on the silicon wafer 6 with the etching surface being smoothed, with the predetermined potential Va (V vs. Pt) being applied via the potential application electrode 7 a of the potentiostat 7.

First, in the silicon wafer 6 (of the plane orientation index (110)) in this case, the rest potential Vr measured in advance as described later is −
With respect to 1.38 (V vs. Pt), for example, -1.8 (V vs. Pt), which is a potential on the negative side, is applied as the predetermined potential Va. In this state, even if the etching process is continued for, for example, 60 minutes, it is possible to obtain a smooth surface without a micro pyramid on the etched surface. The etching rate at this time is as shown in FIG.
As shown in (c), 0.15 to 0.18 μm / mi
about n.

The above-described conditions of the applied potential Va are obtained from experimental results by the inventors described later. In this case, in the above-described case in which the etching is performed with the setting being made on the negative side of the rest potential Vr, the etching rate is slightly reduced, but the etching surface can be obtained in a smooth state without micro-pyramids. Further, the potential Va applied to the silicon wafer 6 is changed to the rest potential Vr.
For example, as a potential on the more positive side, for example, -1.2 (V vs.
When Pt) is applied, the etching rate increases, but micro-pyramids are generated on the etched surface after the etching process for 60 minutes.

When a potential Va near the rest potential Vr is applied, FIG. 2B shows a state in which the distinction between the occurrence of the micropyramid and the occurrence of the streak pattern is clearly shown. However, the occurrence of micropyramids is extremely small even though these are mixed in a small amount, and the micropyramids may not be generated due to a slight change in etching conditions, and only streaks may be generated.

As described above, by setting the potential Va applied to the silicon wafer 6 on the negative side of the rest potential Vr, the potential Va is set to the potential of the area where the stripe pattern shown in FIG. 2B is formed. 4) on the etched surface, some streak patterns as schematically shown in FIG. 4 (the island-like streaks have a width in the range of several tens to one hundred and several tens μm, and the irregularities are in units of each streak pattern). However, unlike a convex part such as a micro-pyramid, it can be obtained as a substantially smooth surface without any hindrance, and process control is performed as an etching process up to a desired etching depth. This makes it possible to perform highly efficient etching.

(2) Plane orientation index (1)
10) Etching process of n-type silicon wafer 6 Next, prior to the above-described smoothing etching process, TMA was performed without applying a potential to the silicon wafer 6.
The etching process is performed in an H aqueous solution 3, and subsequently, the silicon wafer 6 is immersed in the TMAH aqueous solution 3 as it is, and the potential Va is applied under the above conditions to perform the smoothing etching process.

First, the state in which no potential is applied does not mean that the potential of the silicon wafer 6 is zero, but is equivalent to a state in which no current flows, that is, a state in which the rest potential Vr is applied. Therefore, as the etching conditions, as shown in FIG. 2B, the potential region where the micro pyramid occurs and the streak pattern (FIG.
) Is a boundary portion with the potential region where the potential is formed.

Under these etching conditions, as described above, the occurrence of micro-pyramids is extremely small in some cases, and streaks are generated as a whole. In this case, for example, when the etched surface is observed after an etching time of 60 minutes, the surface roughness is 0.8 μm Rz (Rz is 1
0 point average roughness). Further, under these etching conditions, the etching rate can be increased as compared with the above-mentioned etching conditions in which the potential Va is applied (see FIG. 3C). Therefore, when the etching depth (etching amount) dimension of silicon is large, the etching time can be shortened.

When performing the above-described etching without applying the potential, the potential applying electrode 7a is connected to the silicon wafer 6 in advance, and the above-described etching is performed by applying no potential. Then, the silicon wafer 6 is left as it is,
In the state of being immersed in the AH aqueous solution 3, the applied potential Va
Is set to −1.8 (V vs. Pt) to perform a smoothing etching process.

As a result, irregularities such as stripes generated on the etched surface of the silicon wafer 6 can be eliminated, and after the lapse of the etching time of 60 minutes,
The surface roughness was improved to about 0.1 to 0.2 μm Rz.
In this case, the etching rate is reduced as described above, but the degree of smoothness of the etched surface is increased, and irregularities that have occurred in the middle can be improved to a level that does not cause a problem at a practical level. become.

In the smoothing etching process, the etching rate is reduced instead of increasing the smoothness of the etched surface. In this case, however, the etching rate is reduced by stopping the etching. This leads to control in the direction in which the etching is performed, and when the etching depth approaches a desired etching depth, switching to the smoothing etching process can further enhance the process controllability.

(3) Etching process of n-type silicon wafer 6 having plane orientation index (100) This is because, similar to (1), silicon wafer 6 having plane orientation index of (100) is subjected to smoothing etching processing. In this case, it was found that the relationship was opposite to that of the silicon wafer 6 having the plane orientation index of (110).

That is, in order to prevent the micro pyramid from being generated, the potential Va applied to the silicon wafer 6 is changed to the rest potential Vr (= −1.25 V v
s. Pt) is set to a positive potential. Further, the set potential Va is set to a passivation potential Vp (= −−) so that an oxide film is not formed by the etching process.
1.0V vs. For example, the potential is set to about -1.1 (V vs. Pt) so that the potential is on the negative side of Pt). Thus, even after the etching process is performed for an etching time of about 60 minutes, the etched surface can be obtained as a smooth surface in which micro pyramids do not occur.

Next, the results of experiments conducted by the inventors to find out the above etching conditions will be described. First, the potential Va set for the silicon wafer 6
The value of (V vs. Pt) will be schematically described. First, generally, the silicon wafer 6 is placed in the TMAH aqueous solution 3.
When the scanning potential V (V vs. Pt) is applied by changing the scanning potential from a negative potential side to a positive potential side at a predetermined scanning speed (for example, 50 mV / sec) in a state of being immersed in the inside, the potential reaches a certain potential Vr. The current flows in the direction flowing from the TMAH aqueous solution 3 side, that is, the cathode current, and when the potential becomes more positive than the potential Vr, the anode current flows so that the current flows toward the counter electrode 7b. At this time, the potential V at which neither the cathode current nor the anode current flows
r is defined as a rest potential.

Although the negative value of the rest potential is obtained here as the value of the potential, this is the value of the potential Va (V vs. Pt) obtained with respect to the reference electrode 7c. As described above, the state when the silicon wafer 6 is immersed in the etching solution without applying a potential is equivalent to the state when the potential is not applied, that is, the state when the potential is not applied is the same as that when the rest potential Vr is given. Will be set to.

The state in which the anode current flows is caused by the dissolution or oxidation of the silicon wafer 6, and until the current reaches a certain peak, the current mainly due to the dissolution of silicon is dominant. Yes,
The oxidation phenomenon becomes dominant when the potential becomes higher than the potential Vp at which the peak value is obtained, and the anode current tends to decrease. Then, as the oxidation phenomenon progresses, the resistance is increased by the oxide film generated, and the current is stopped, so that the current value approaches zero. Note that the potential Vp when the anode current reaches a peak value is defined as a passivation potential.

By setting the potential of the potential application electrode 7a by providing the reference electrode 7c as described above, the potential Va (V vs. Pt) of the silicon wafer 6 is set.
Is the size of the silicon wafer 6 as a sample and the TMAH
The setting can be performed without being affected by the temperature variation of the aqueous solution 3 or the like. The same applies to the rest potential Vr and the passivation potential Vp.

FIGS. 2 (a) and 3 (a) show the results (voltammograms) of plotting the relationship between the potential and the current actually using the silicon wafer 6, which is shown in FIG. 2 (a). Fig. 3 (a) shows the results obtained for the silicon wafer 6 having the plane orientation index (110), and Fig. 3 (a) shows the results obtained for the silicon wafer 6 having the plane orientation index (100). In other words, even with the same silicon wafer 6, different results can be obtained depending on the plane orientation index of the main surface exposed to the TMAH aqueous solution 3 as an etchant.

That is, in the silicon wafer 6 having the plane orientation index (110), the rest potential Vr is -1.38.
(V vs. Pt), and the passivation potential Vp is −0.95 (V vs. Pt). In the silicon wafer 6 having the plane orientation index (100), the rest potential Vr is -1.25 (V vs. Pt).
And the passivation potential Vp is -1.0
(V vs. Pt).

Next, with respect to the silicon wafer 6 having the respective plane orientation indices, the results obtained with respect to the state of the etched surface and the etching rate when the etching process is performed with the applied potential Va set to various values are shown. 2
(B), (c) and FIGS. 3 (b), (c). Thus, it was found that the conditions when the micro-pyramid was generated had almost the opposite characteristics with respect to those having the plane orientation index of (110) and (100) with respect to the rest potential Vr.

That is, when a potential on the negative side of the rest potential Vr is applied to the silicon wafer 6 having a plane orientation index (110), the occurrence of micro-pyramids is suppressed and the surface becomes a substantially smooth etched surface, and a positive potential is applied. This results in the occurrence of a micropyramid. On the other hand, in the silicon wafer 6 having the (100) plane orientation, a micro-pyramid is generated when a negative potential is applied from a potential near the rest potential Vr, and when a positive potential is applied. The generation of micro pyramids is suppressed, and a substantially smooth etched surface can be obtained.

Further, with respect to the etching rate, the silicon wafer 6 having the (110) plane orientation is a factor that largely fluctuates around the potential of the rest potential Vr. Also indicates that control can be performed by setting the potential.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. This is a case where etching for roughening the surface of the silicon wafer 6 to be etched, that is, a roughening etching process is performed. That is, by forming a rough surface on the surface of the silicon wafer 6 to increase the surface area, it is intended to form an etched surface that is effective in forming an ohmic contact or bonding formed elements. It is.

Thus, for example, in the case of forming an ohmic contact, by increasing the contact area, it is possible to reduce the contact resistance at that portion and to improve the electrical characteristics, and to improve the electrical characteristics of the element. In the case of forming the bonding surface, by increasing the contact area, the bonding strength at that portion can be improved.

As described in the first embodiment, the etching conditions for the silicon wafer 6 having a plane orientation index of (110) among the potential regions shown in FIGS. 2 and 3 are as described in the first embodiment. As shown in FIG. 2B, the potential Va to be applied is changed to a region (-1.5
~ -0.95V vs. Pt), for example, −
The etching process is performed at 1.2 (V vs. Pt). Then, a large number of micro pyramids as shown in FIG. 5 are formed on the etched surface of the silicon wafer 6. At this time, the degree of the formed micropyramid can be controlled by appropriately selecting the value of the applied potential.

In the case of the silicon wafer 6 having a plane orientation index of (100), the potential Va to be applied is set to the potential of the region where the micropyramid is generated (the potential region on the negative side of -1.45 V vs. Pt). For example, -1.55 (V
vs. (Pt) and perform the etching process. Then, a large number of micro pyramids as shown in FIG. 5 are formed on the etched surface of the silicon wafer 6. At this time, the degree of occurrence frequency of the formed micro-pyramid can be controlled by appropriately selecting the value of the potential Va to be applied.

The size of the micropyramid is about several μm to 10 μm on one side, and the plane orientation index (1
It is known that the bottom surface is formed in a square pyramid shape on the (00) plane, whereas the bottom surface is formed in a rhombic pyramid shape on the plane with the plane orientation index (110).

Third Embodiment FIGS. 6 and 7 show a third embodiment of the present invention. For example, when a diaphragm or the like of a pressure sensor is formed, the plane orientation index is (110). By adjusting the potential Va applied to the silicon wafer 6 having the above, an etching process for controlling the size is performed.

FIG. 6 shows a silicon substrate 8 for forming a pressure sensor of a silicon wafer 6 to be subjected to an etching process.
This shows a cross section of a portion, and a rear surface (upward in the figure) is formed to form a portion of the diaphragm 9 having a desired thickness t.
A concave portion 1 having a depth D by performing anisotropic etching from the side
0 is formed (see FIG. 3A). At this time, in order to form the dimension L (the width dimension of the portion having the thickness t) L of the diaphragm 9 to a desired size, as shown in FIG.
The etching mask 11 is taken into consideration so that the slope portion forming the peripheral wall portion of the concave portion 10 is exposed with the plane orientation index (100) with respect to the plane orientation index (110) of the main surface.
To form

In this embodiment, the silicon wafer 6
The ratio of the etching rate of the plane with the plane orientation index (110) to the etching rate of the plane with the plane orientation index (100) exposed in the concave portion 10 as the etching process proceeds is defined as the potential applied to the silicon wafer 6. It is intended to control by adjusting Va.

FIG. 7 shows that the etching solution is a 22 wt% TM
The potential Va applied to the n-type silicon wafer 6 is changed while maintaining the temperature at 80 ° C. using the AH aqueous solution 3 (110).
In the figure, the etching rates of the plane and the (100) plane were measured, and the ratio values were shown. As a result, the etching rate ratio is highly dependent on the applied voltage Va, and by controlling this, the etching processing can be performed at a desired etching rate ratio.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. In the above embodiments, the case where the n-type silicon wafer 6 is used has been described.
The same etching process is performed for a p-type silicon wafer. The applied voltage V that determines the etching conditions
The value of a and the polarity can be treated as having the same characteristics regardless of the n-type or p-type, but the values of the rest potential Vr and the value of the passivation potential Vp are generally different. It is a target.

The TMAH aqueous solution 3 used as the etching solution is not limited to 22 wt% but may be 20 to 50 wt%.
Can be used as long as it is within the range. Regarding the concentration, the etching rate is higher on the lower concentration side,
The etched surface tends to be rough. In addition, if the concentration fluctuation can be controlled, it is possible to use a concentration of 20 wt%. Similarly, the temperature of the etching solution is set to 80 ° C. to perform the etching process, but this can be set to an appropriate condition.

Not only the TMAH aqueous solution 3 but also various alkyl groups such as tetraethylammonium hydroxide (TEAH), tetrapropylammonium hydroxide (TPAH) or tetrabutylammonium hydroxide (TBAH) as the quaternary ammonium hydroxide. Can be adopted.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an etching tank showing a first embodiment of the present invention.

FIG. 2 is a view for explaining etching conditions for a silicon wafer having a plane orientation index (110).

FIG. 3 is a view corresponding to FIG. 2 for a silicon wafer having a plane orientation index (100).

FIG. 4 is a schematic view of a streak pattern formed on an etched surface.

FIG. 5 is a schematic diagram of a micro pyramid formed on an etched surface according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a shape of a diaphragm and a plane orientation index on a silicon substrate according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between an etching rate ratio between different plane orientation indices with respect to an applied potential.

[Explanation of symbols]

1 is an etching device, 2 is an etching tank, 3 is TMAH
Aqueous solution (quaternary ammonium hydroxide aqueous solution), 4 is a temperature controller, 5 is a stirrer, 6 is a silicon wafer, 7 is a potentiostat, 7a is a potential application electrode, 7c is a reference electrode, 8 is a silicon substrate, 9 is a diaphragm, Reference numeral 10 denotes a concave portion, and 11 denotes an etching mask.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F043 AA02 BB02 DD12 DD14 EE10 EE14 FF04 FF07 FF10 GG04

Claims (11)

[Claims] 1. A semiconductor etching method for performing an etching process by immersing a semiconductor in an etching solution, wherein the etching solution is quaternary ammonium hydroxide (TAA).
H (Tetra Arkyl Ammonium Hydroxide); [R ₁ R ₂ R
₃ R ₄ N] ⁺ OH ⁻ , wherein R _{1 to} R _{4 each} represent an alkyl group) An aqueous solution adjusted to a predetermined concentration is used, and the etching process is performed while a predetermined potential is applied to the semiconductor. Semiconductor etching method. 2. The method of etching a semiconductor according to claim 1, wherein, when the semiconductor is a silicon substrate having a main surface having a plane orientation index of (110), the potential given to the semiconductor during the etching process is set to the potential. A smoothing etching process step is provided in which the potential of the reference electrode immersed in the etchant is set to a potential on the negative side of a rest potential defined as a state in which no current flows through the silicon substrate. Characteristic semiconductor etching method. 3. The semiconductor etching method according to claim 1, wherein, when the semiconductor is a silicon substrate having a main surface having a plane orientation index of (100), the potential applied to the semiconductor during the etching process is set to the potential. A smoothing etching process performed by setting a potential between a passivation potential and a rest potential defined as a potential at which an anode current flowing through a silicon substrate becomes maximum with respect to a potential of a reference electrode immersed in an etching solution. A method for etching a semiconductor, comprising a step. 4. The method for etching a semiconductor according to claim 2, wherein the smoothing etching process is performed as a process after the etching process performed without applying a potential to the semiconductor. Semiconductor etching method. 5. The method for etching a semiconductor according to claim 1, wherein the etching solution is tetramethylammonium hydroxide (TMAH).
thyl Ammonium Hydoroxide); [(CH ₃ ) ₄ N] ⁺ O
H ⁻ ; hereinafter referred to as TMAH) an etching method for a semiconductor, characterized by using an aqueous solution. 6. The method for etching a semiconductor according to claim 5, wherein the TMAH aqueous solution is adjusted to a concentration in a range of 20 to 50 wt%. 7. The method of etching a semiconductor according to claim 6, wherein the TMAH aqueous solution is adjusted to a concentration of 22 wt%. 8. The method for etching a semiconductor according to claim 1, wherein when the semiconductor is a silicon substrate having a main surface having a plane orientation index of (110), the potential applied to the semiconductor during the etching process is set to the potential. A method of etching a semiconductor, comprising a roughening etching step performed by setting a potential between a passivation potential and the rest potential. 9. The method for etching a semiconductor according to claim 1, wherein, when the semiconductor is a silicon substrate having a main surface having a plane orientation index of (100), the potential applied to the semiconductor during the etching process is set to the potential. A method for etching a semiconductor, comprising a roughening etching step performed by setting the potential to a negative side of a rest potential. 10. The method for etching a semiconductor according to claim 1, wherein, for different plane orientations appearing on the etched surface of the semiconductor due to the etching process, the etching progress rate ratio with respect to those plane orientations is determined. A method for adjusting the level of a predetermined potential applied to a semiconductor device. 11. The method for etching a semiconductor according to claim 10, wherein the silicon substrate as the semiconductor has an etching progress rate ratio of (100) and (110) with respect to a plane orientation index of (100). Applying a potential to the semiconductor.