JP2000058826A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an inter-band current consuming excessive power by making an insulating film excepting the lower section of a gate electrode thicker than an insulating film in the lower section of the gate electrode. SOLUTION: A gate oxide film 12 is formed onto a silicon substrate 11, and a polycrystalline silicon layer and a nitride film are formed successively onto the gate oxide film 12. The nitride film is patterned and a nitride film pattern is formed, and the polycrystalline silicon layer is removed selectively by etching while using the nitride film pattern as a mask, and a gate electrode 14 is shaped. An oxide film 23 is formed by a heat treatment while employing the nitride film pattern and the nitride film as masks, and a polycrystalline silicon film 17 is deposited on the whole surface. Consequently, the oxide film 23 excepting the lower section of the gate electrode 14 is made thicker than the oxide film 12 in the lower section of the gate electrode 14. Accordingly, an inner-band current consuming excessive power can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS transistor having an LDD structure.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional MOS transistor having an LDD structure. Reference numeral 1 in the figure denotes an n-type silicon substrate, on which a gate electrode (S) 3 is formed via a gate oxide film 2. A spacer 4 made of an insulating material is formed on a side wall of the gate electrode 3. On the surface of the substrate 1, a low-concentration (p-type) diffusion layer 5a is formed in a self-aligned manner with the gate electrode 3.
6a are formed. Also, on the surface of the substrate 1,
High concentration (p) in a self-aligned manner with the gate electrode 3 and the spacer 4
(Type) diffusion layers 5b and 6b are formed. Here, the source region (S) 7 is composed of the diffusion layers 5a and 5b, and the drain region (D) 8 is composed of the diffusion layers 6a and 6b.

In a transistor having such a configuration, a current path in the substrate 1, the gate electrode 3, the source region 7, and the drain region 8 is as shown in FIG. In other words, when operating as a transistor, the current path is between the drain and the source. Even when this current is turned off, a current (inter-band current) flows through the path in FIG.

FIG. 9 shows an example of the voltage dependence of the interband tunnel current (the dependence of the drain current on the drain voltage). However, FIG. 9 shows the case of the p channel. In FIG. 9, the vertical axis shows the drain current in logarithm, and the horizontal axis shows the drain voltage. From FIG. 9, the current has an exponential dependence on the source-drain voltage.
Further, the current depends on the voltage between the gate electrode and the drain region. For example, point A has Vd = -3V / Vg = 0V, point B has Vd = -2V / Vg = 1V, and the DG voltage is 3V.
V. The currents are almost equal.

FIG. 10 shows an example of the dependence of the interband tunnel current on the gate oxide film. However, FIG.
This is for the p channel. In FIG. 10, the vertical axis shows the drain current in logarithm, and the horizontal axis shows the gate oxide film thickness. The current greatly depends on the gate oxide film thickness. For example, when the gate oxide film thickness increases from 8 nm to 9 nm, the current decreases less than half from 0.37 pA / μm to 0.16 pA / μm.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. Therefore, the inter-band current which consumes extra power is reduced by increasing the gate oxide film thickness at the drain end near the gate electrode. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0007]

Means for Solving the Problems The first invention of the present application is the first invention.
A conductive semiconductor substrate, an insulating film provided on the semiconductor substrate, a gate electrode formed on the semiconductor substrate via the insulating film, and a gate electrode provided on the semiconductor substrate and on a side wall of the gate electrode. A conductive member, an insulator provided on the semiconductor substrate and on a side wall of the conductive member, and a second conductive type low formed on the surface of the semiconductor substrate in self-alignment with the gate electrode. A second conductivity type high-concentration region formed in a self-alignment manner with the gate electrode, the conductive member and the insulator on the surface of the semiconductor substrate, and the insulating film other than the lower portion of the gate electrode. Is thicker than the insulating film below the gate electrode.

According to a second aspect of the present invention, there is provided a process for forming a gate electrode and a nitride film pattern on a semiconductor substrate of a first conductivity type via an insulating film, and a process for forming a nitride film spacer on a side wall of the gate electrode. Performing a heat treatment using the gate electrode and the nitride film spacer as a mask to increase the thickness of the insulating film except for the portion below the gate electrode; and removing the nitride film pattern and the nitride film spacer, and then forming a conductive member on the entire surface. Depositing the conductive member, reactive ion etching the conductive member to leave the conductive member on the side wall of the gate electrode, and forming a second conductive type on the semiconductor substrate using the gate electrode and the conductive member as a mask. Introducing an impurity to form a low concentration region of the second conductivity type; forming an insulating film spacer on a side wall of the conductive member; A second conductivity type impurity is introduced into the semiconductor substrate to Makusupesa as a mask, a method of manufacturing a semiconductor device characterized by comprising the step of forming a high-concentration region of the second conductivity type.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an LD according to an embodiment of the present invention will be described.
1 to 8 show a method of manufacturing a MOS transistor having a D structure.
This will be described with reference to FIG. The following embodiments are merely examples of the present invention, and numerical values such as film thickness, material, temperature, and time are not limited to those described.

(1) First, an 8 nm-thick gate oxide film 12 is formed on a p-type silicon substrate 11 by a dry oxidation method (9).
(00 ° C., 50 minutes). Subsequently, a thickness 200 as a gate electrode material layer is formed on the gate oxide film 12.
A polycrystalline silicon layer having a thickness of 150 nm and a nitride film having a thickness of 150 nm were sequentially formed. Here, the nitride film is for preventing the gate electrode from being oxidized by the gate oxidation after the formation of the nitride film spacer. Further, after patterning the nitride film to form a nitride film pattern 13, the polycrystalline silicon layer was selectively etched away using the nitride film pattern 13 as a mask to form a gate electrode 14 (see FIG. 1). .

(2) Next, a 30-nm-thick nitride film 15 was deposited on the entire surface (see FIG. 2). Subsequently, the nitride film 1
5 is nitrided film 1 by reactive ion etching (RIE).
5 was removed until it remained on the side wall of the gate electrode 14 (see FIG. 3). Further, the nitride film pattern 13 and the nitride film 1
5 was used as a mask, and an oxide film 23 having a thickness of about 12 nm was formed. Thereafter, a polycrystalline silicon layer 17 was deposited on the entire surface (see FIG. 4).

(3) Next, the polycrystalline silicon layer 17 is etched by RIE to leave a polycrystalline silicon layer (polyspacer) 17a having a width of 100 nm as a conductive member only on the side wall of the gate electrode 14. . The gate length becomes longer than the minimum photo length by using the policer. In this example, the photo length is 0.35 μm and 6
% Increase. However, a transistor intended for low power consumption often has a large poly length, which is not a serious problem in practice. Subsequently, n is added to the element region using the gate electrode 14 and the polysilicon 17a as a mask.
Type impurity (phosphorus) at an acceleration voltage of 40 keV and a dose of 1
Introduced under the condition of × 10 ⁻¹⁴ , the n ⁻ type diffusion layers 15a, 15
6a was formed. Further, an insulating film 18 having a thickness of 100 nm was deposited on the entire surface (see FIG. 5).

(4) Next, the insulating film 18 was removed by etching by RIE, and an insulating spacer 19 having a width of 100 nm as an insulator was formed on the sidewall of the polysilicon spacer 17a (see FIG. 6). During this etching, the oxide film 2
Part of 3 was also etched away. Subsequently, the surfaces of the diffusion layers 15a and 16a were oxidized to form an oxide film 20 having a thickness of 100 nm (see FIG. 7).

(5) An n-type impurity (arsenic) is accelerated to the element region of the substrate 11 at an acceleration voltage of 60 keV by using the gate electrode 14, the polysilicon spacer 17a and the insulating spacer 19 as a mask.
Introduced under the condition of a dose of 3 × 10 ⁻¹⁵ , n ⁺ type diffusion layers 15b and 16b were formed. As a result, the diffusion layers 15a,
15b constitutes the source region 21, and the diffusion layer 16a1
The drain region 22 was composed of 6b, and a MOS transistor having an LDD structure was manufactured (see FIG. 8).

In the MOS transistor having the LDD structure according to the above embodiment, the polysilicon 17 is provided on the side wall of the gate electrode 14.
Since the insulating spacer 19 is provided through the gate electrode a and the thick oxide film 23 is provided at the drain end near the gate electrode 14, the interband tunnel current is reduced and the electric field between the gate and the drain is reduced. can do.

In the above embodiment, the case where polycrystalline silicon is used as the conductive member has been described. However, the present invention is not limited to this.

[0017]

As described above in detail, according to the present invention, by increasing the gate oxide film thickness at the drain end near the gate electrode, it is possible to reduce the interband current that consumes extra power and reduce the source-drain current. Semiconductor device capable of alleviating the electric field and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a view showing one step of a MOS transistor having an LDD structure according to an embodiment of the present invention, up to formation of a gate electrode.

FIG. 2 is a view showing one step of a MOS type transistor having an LDD structure according to one embodiment of the present invention, up to formation of a nitride film on the entire surface;

FIG. 3 is a view showing one step of the MOS transistor having the LDD structure according to one embodiment of the present invention, up to the step of covering the side wall of the gate electrode with a nitride film.

FIG. 4 is a view showing one step of an MOS transistor having an LDD structure according to one embodiment of the present invention, up to formation of a polysilicon layer serving as a polysilicon over the entire surface;

FIG. 5 is a view showing one step of a MOS transistor having an LDD structure according to one embodiment of the present invention, up to formation of an insulating film serving as an insulating spacer over the entire surface;

FIG. 6 is a view showing one step of a MOS transistor having an LDD structure according to an embodiment of the present invention, up to formation of an insulating spacer on a side wall of the polysilicon spacer.

FIG. 7 is a view showing one step of a MOS transistor having an LDD structure according to an embodiment of the present invention, up to formation of an oxide film on an exposed diffusion layer surface;

FIG. 8 is a view showing one step of a MOS transistor having an LDD structure according to one embodiment of the present invention, up to formation of source and drain regions.

FIG. 9 is a characteristic diagram showing a relationship between a source / drain current and a drain voltage.

FIG. 10 is a characteristic diagram showing a relationship between a drain current and a gate oxide film thickness.

FIG. 11 is a sectional view of a conventional MOS transistor having an LDD structure.

FIG. 12 is an explanatory diagram of a current path between a substrate and a gate, a source, and a drain.

[Explanation of symbols]

 11: p-type silicon substrate, 12: gate oxide film, 13: nitride film pattern, 14: gate electrode, 15: nitride film, 17a: policer (conductive member), 19: insulating spacer (insulator) ), 20, 23: oxide film, 21: source region, 22: drain region.

Claims (2)

[Claims] A first conductive type semiconductor substrate; an insulating film provided on the semiconductor substrate; a gate electrode formed on the semiconductor substrate via the insulating film; A conductive member provided on a side wall of the gate electrode, an insulator provided on the semiconductor substrate and on a side wall of the conductive member, and formed on the surface of the semiconductor substrate in a self-aligned manner with the gate electrode; A low-concentration region of the second conductivity type, and a high-concentration region of the second conductivity type formed on the surface of the semiconductor substrate in a self-aligned manner with the gate electrode, a conductive member, and an insulator. The semiconductor device, wherein the insulating film other than the lower part of the electrode is thicker than the insulating film below the gate electrode. A step of forming a gate electrode and a nitride film pattern on a semiconductor substrate of a first conductivity type via an insulating film; a step of forming a nitride film spacer on a side wall of the gate electrode; Performing a heat treatment using the nitride film spacer as a mask to increase the thickness of the insulating film other than the lower portion of the gate electrode; and, after removing the nitride film pattern and the nitride film spacer, depositing a conductive member on the entire surface; Reactive ion etching this conductive member, leaving a conductive member on the side wall of the gate electrode, and introducing a second conductivity type impurity into the semiconductor substrate using the gate electrode and the conductive member as a mask; Forming a low concentration region of the second conductivity type, forming an insulating film spacer on a side wall of the conductive member, and masking the gate electrode, the conductive member and the insulating film spacer. Forming a high-concentration region of the second conductivity type by introducing a second conductivity type impurity into the semiconductor substrate.