JP2000056847A - Constant current driving circuit - Google Patents

Constant current driving circuit

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JP2000056847A
JP2000056847A JP10229650A JP22965098A JP2000056847A JP 2000056847 A JP2000056847 A JP 2000056847A JP 10229650 A JP10229650 A JP 10229650A JP 22965098 A JP22965098 A JP 22965098A JP 2000056847 A JP2000056847 A JP 2000056847A
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transistor
connected
gate
constant current
drain
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JP2953465B1 (en
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Shigeo Nishitoba
茂夫 西鳥羽
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Nec Corp
日本電気株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a constant current driving circuit which can supply a constant current corresponding to an inputted signal without increasing cost.
SOLUTION: A resistance 3 is connected to an input terminal 1. Further, a transistor(TR) 4 has its drain and gate connected to the resistance 3. A switching TR 6 has one end connected to the drain and gate of the TR 4. A control terminal 2 inputting an address signal for ON/OFF control over the switching TR 6 is connected to the gate of the switching TR 6. One electrode of a charge holding capacity element 7 is connected to the other end of the switching TR 6. The other electrode of the charge holding capacity element 7 is connected to a ground terminal 11. Further, a TR 5 has its gate connected to the other end of the switching TR 6. A load 8 is connected to the drain of the TR 5.
COPYRIGHT: (C)2000,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明はアクティブマトリクス方式の有機エレクトロルミネセント素子等に好適な定電流駆動回路に関し、特に、内蔵されるカレントミラー回路の整合性の向上を図った定電流駆動回路に関する。 The present invention relates to relates to suitable constant current driving circuit to the organic electroluminescent element or the like of an active matrix type, in particular, relates to a constant current driving circuit with improved consistency of the current mirror circuit incorporated .

【0002】 [0002]

【従来の技術】従来、アクティブマトリックス方式の有機エレクトロルミネセント(EL)素子等に定電流駆動回路が使用されている。 Conventionally, a constant current drive circuit is used in an organic electroluminescent (EL) element or the like of an active matrix system. 図7は従来の定電流駆動回路を示す回路図である。 Figure 7 is a circuit diagram showing a conventional constant current driving circuit.

【0003】従来の定電流駆動回路においては、入力端子101に抵抗103が接続されている。 In a conventional constant current drive circuit, the resistor 103 is connected to the input terminal 101. また、抵抗1 In addition, resistance 1
03にドレイン及びゲートが接続されたトランジスタ1 03 transistor 1 drain and gate connected to
04が設けられている。 04 is provided. トランジスタ104のソースには、スイッチ用トランジスタ106のドレインが接続されている。 The source of the transistor 104, the drain of the switching transistor 106 are connected. そして、スイッチ用トランジスタ106のゲートには、スイッチ用トランジスタ106の導通/遮断の制御を行うためのアドレス信号が入力される制御端子102が接続され、スイッチ用トランジスタ106のソースには、接地端子111が接続されている。 Then, to the gate of the switching transistor 106, a control terminal 102 to the address signal for controlling the conduction / interruption of the switching transistor 106 is input is connected to the source of the switching transistor 106, a ground terminal 111 There has been connected.

【0004】また、トランジスタ104のドレイン及びゲートには、電荷保持容量素子107の一方の電極が接続されている。 Further, to the drain and gate of the transistor 104, one electrode of the charge storage capacitor 107 is connected. 電荷保持容量素子107の他方の電極は、接地端子111に接続されている。 The other electrode of the charge storage capacitor 107 is connected to the ground terminal 111. 更に、トランジスタ104のドレイン及びゲートにゲートが接続されたトランジスタ105が設けられている。 Further, the transistor 105 having the gate connected to the drain of transistor 104 and the gate is provided. トランジスタ1 Transistor 1
05のソースは接地端子111に接続されている。 05 source is connected to the ground terminal 111. また、トランジスタ105のドレインには、負荷108が接続されている。 Further, the drain of the transistor 105, the load 108 is connected. 負荷108は、例えば定電流駆動を要する有機EL素子である。 Load 108 is, for example, an organic EL device requiring a constant current driving. そして、負荷108には、電源端子110が接続されている。 Then, the load 108, the power terminal 110 is connected. このようにして構成された従来の定電流駆動回路には、トランジスタ104及び105からなるカレントミラー回路が含まれている。 Thus the conventional constant current driving circuit configured is contained by the current mirror circuit consisting of transistors 104 and 105.

【0005】そして、入力端子101に入力された信号の電圧に応じて抵抗103に電流が流れる。 [0005] Then, current flows through the resistor 103 in accordance with the voltage of the signal input to the input terminal 101. このとき、 At this time,
スイッチ用トランジスタ106が導通状態であれば、トランジスタ105に抵抗103に流れる電流に比例した電流がドレイン電流として流れ、負荷108にも電流が流れる。 If the transistor 106 is in the conductive state switches, flow as a current drain current proportional to the current flowing through the transistor 105 to the resistor 103, current also flows to the load 108. 一方、スイッチ用トランジスタ106が遮断状態であれば、トランジスタ105にはドレイン電流が流れないので、負荷108にも電流は流れない。 On the other hand, if the transistor 106 is cut-off state for the switch, since no drain current flows through the transistor 105, a current does not flow in the load 108. このようにして、負荷108に流れる定電流の導通/遮断が制御される。 In this way, the connection / disconnection of the constant current flowing through the load 108 is controlled.

【0006】 [0006]

【発明が解決しようとする課題】しかしながら、上述の従来の定電流駆動回路においては、スイッチ用トランジスタ106のオン抵抗及びソース電流による電圧降下のためにカレントミラー回路の整合性が悪化し、負荷10 [SUMMARY OF THE INVENTION However, in the conventional constant-current drive circuit described above, the consistency of the current mirror circuit for the voltage drop due to the on resistance and the source current of the switching transistor 106 is deteriorated, the load 10
8に入力端子101の信号レベルに応じた定電流が供給されないという問題点がある。 There is a problem that a constant current corresponding to the signal level of the input terminal 101 to 8 is not supplied.

【0007】また、これを防止するためにスイッチ用トランジスタ106のサイズを大きくしてそのオン抵抗を小さくすることが考えられるが、これを半導体集積回路で構成しようとする場合、チップサイズが増大するため、コストの上昇につながる。 Further, it is conceivable to reduce the on-resistance by increasing the size of the switching transistor 106 in order to prevent this, when trying to configure this in the semiconductor integrated circuit, chip size increases Therefore, it is leading to an increase in cost. また、例えば有機EL素子の駆動回路として薄膜トランジスタ(TFT)を使用する場合、スイッチ用トランジスタに大きなサイズが必要となるため、画素の占有率が減って開口率が低下して輝度が低下してしまう。 Also, for example, when using a thin film transistor (TFT) as the driving circuit of the organic EL device, since a large size is required for switching transistor, decreases luminance by the aperture ratio is decreased decreases occupancy of pixels . この場合には、輝度を通常使用レベルまで上昇させるために定電流値を上げる等の対策が必要となり、近時の省電力化に逆行するものとなる。 In this case, measures such as increasing the constant current value in order to increase the brightness to the normal use level is required, and that runs counter to recent power saving.

【0008】本発明はかかる問題点に鑑みてなされたものであって、コストを上昇させることなく入力された信号に応じた定電流を供給することができる定電流駆動回路を提供することを目的とする。 The present invention was made in view of the above problems, it aims to provide a constant current drive circuit capable of supplying a constant current corresponding to the input signal without increasing the cost to.

【0009】 [0009]

【課題を解決するための手段】本発明に係る定電流駆動回路は、入力端子と、この入力端子にドレインが接続され接地にソースが接続された第1のトランジスタと、この第1のトランジスタのゲート及びドレインに接続されたスイッチ用トランジスタと、このスイッチ用トランジスタのゲートに接続されこのスイッチ用トランジスタの導通と非導通とを切替える信号が入力される制御端子と、前記スイッチ用トランジスタにゲートが接続され接地にソースが接続され前記第1のトランジスタと共にカレントミラー回路を構成する第2のトランジスタと、この第2のトランジスタのゲートに一方の電極が接続され接地に他方の電極が接続された容量素子と、を有することを特徴とする。 Constant current driving circuit according to the present invention, in order to solve the problem] has an input terminal, a first transistor having a drain source to ground is connected is connected to the input terminal of the first transistor a switch connected transistor to the gate and drain, a control terminal connected to the gate of the switching transistor signal switching between conduction and non-conduction and the switching transistor is inputted, the gate is connected to the switching transistor by the second transistor and, the second one electrode to the gate of the transistor is connected the other electrode is a capacitor which is connected to a ground which constitutes a current mirror circuit together with the source thereof connected to the first transistor to ground and having a, the.

【0010】なお、前記第1及び第2のトランジスタのチャネルの導電型は、前記スイッチ用トランジスタのチャネルの導電型と相違し、前記第1のトランジスタのソースと接地との間に接続された第1のレベルシフト用ダイオードと、前記第2のトランジスタのソースと接地との間に接続された第2のレベルシフト用ダイオードと、 [0010] Incidentally, the first and the channel conductivity type of the second transistor, different from the conductivity type of the channel of the switching transistor, the first connected between the source and the ground of the first transistor and 1 of the level shift diode, a second level shift diode connected between the source and the ground of the second transistor,
を有してもよい。 It may have.

【0011】また、前記第1及び第2のトランジスタのチャネルの導電型は、前記スイッチ用トランジスタのチャネルの導電型と同じであってもよい。 Further, the first and the channel conductivity type of the second transistor may be the same as the conductivity type of the channel of the switching transistor.

【0012】本発明に係る他の定電流駆動回路は、入力端子と、この入力端子にドレインが接続され接地にソースが接続された第1のトランジスタと、この第1のトランジスタのゲートとドレインとの間に接続されたスイッチ用トランジスタと、このスイッチ用トランジスタのゲートに接続されこのスイッチ用トランジスタの導通と非導通とを切替える信号が入力される制御端子と、前記第1のトランジスタのゲートにゲートが接続され接地にソースが接続され前記第1のトランジスタと共にカレントミラー回路を構成する第2のトランジスタと、この第2 [0012] Another constant current driving circuit according to the present invention includes an input terminal, a first transistor having a drain source to ground is connected is connected to the input terminal, a gate and a drain of the first transistor a switching transistor connected between a control terminal connected to the gate of the switching transistor signal switching between conduction and non-conduction and the switching transistor is inputted, the gate to the gate of said first transistor a second transistor constituting a current mirror circuit but with the connected source is connected to the ground the first transistor, the second
のトランジスタのゲートに一方の電極が接続され接地に他方の電極が接続された容量素子と、を有することを特徴とする。 Is of one of the electrodes is connected to the gate of the transistor and having a, a capacitor element and the other electrode is connected to ground.

【0013】なお、前記入力端子と前記第1のトランジスタのドレインとの間に接続された抵抗を有することができる。 [0013] Incidentally, it is possible to have a resistor connected between the drain of the said input terminals first transistor.

【0014】また、前記入力端子と前記抵抗との間に接続されたソースフォロワ用トランジスタを有することができる。 Further, it is possible to have a connected source follower transistor between said resistor and said input terminal.

【0015】更に、前記第2のトランジスタのドレインは有機エレクトロルミネセント素子に接続されることができる。 Furthermore, the drain of the second transistor may be connected to the organic electroluminescent element.

【0016】本発明においては、スイッチ用トランジスタが非導通にされても、第2のトランジスタのゲートと接地との間に設けられた容量素子に蓄積された電荷によって、定電流を供給し続けることができる。 In the present invention, that the switch transistor is also rendered non-conductive, which by the charge stored in the capacitor provided between the ground and the gate of the second transistor continues to supply a constant current can. また、スイッチ用トランジスタのオン抵抗による電圧降下は無視できるほど小さい。 Also, small enough voltage drop due to the on resistance of the switching transistor can be neglected. このため、カレントミラー回路の整合性が著しく改善される。 Therefore, consistency of the current mirror circuit is remarkably improved.

【0017】 [0017]

【発明の実施の形態】以下、本発明の実施例に係る定電流駆動回路について、添付の図面を参照して具体的に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the constant current driving circuit according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. 図1は本発明の第1の実施例に係る定電流駆動回路を示す回路図である。 Figure 1 is a circuit diagram showing a constant current driving circuit according to a first embodiment of the present invention.

【0018】本実施例の定電流駆動回路においては、入力端子1に抵抗3が接続されている。 [0018] In the constant current drive circuit of the present embodiment, the resistance 3 to the input terminal 1 is connected. また、抵抗3にドレイン及びゲートが接続されたNチャネルMOSトランジスタ4が設けられている。 Also, N-channel MOS transistor 4 having a drain and a gate connected is provided to the resistor 3. トランジスタ4のソースには、接地端子11が接続されている。 The source of the transistor 4, the ground terminal 11 is connected. また、トランジスタ4のドレイン及びゲートに一端が接続されPチャネルMOSトランジスタであるスイッチ用トランジスタ6が設けられている。 Further, the switching transistor 6 is provided at one end to the drain of the transistor 4 and the gate is connected to P-channel MOS transistor. そして、スイッチ用トランジスタ6のゲートには、スイッチ用トランジスタ6の導通/遮断(非導通)の制御を行うためのアドレス信号が入力される制御端子2が接続されている。 Then, to the gate of the switching transistor 6, the control terminal 2 is connected to the address signal for controlling the conduction / interruption of the switching transistor 6 (nonconductive) is input.

【0019】また、スイッチ用トランジスタ6の他端には、電荷保持手段として電荷保持容量素子7の一方の電極が接続されている。 Further, the other end of the switching transistor 6, one electrode of the charge storage capacitor 7 is connected as the charge holding unit. 電荷保持容量素子7の他方の電極は、接地端子11に接続されている。 The other electrode of the charge storage capacitor 7 is connected to the ground terminal 11. 更に、スイッチ用トランジスタ6の前記他端にゲートが接続されたNチャネルMOSトランジスタ5が設けられている。 Furthermore, the N-channel MOS transistor 5, the gate of which is connected is provided on the other end of the switching transistor 6. トランジスタ5のソースは接地端子11に接続されている。 The source of the transistor 5 is connected to the ground terminal 11. また、トランジスタ5のドレインには、負荷8が接続されている。 Further, the drain of the transistor 5, a load 8 is connected. 負荷8は、例えば定電流駆動を要するアクティブマトリクス方式の有機エレクトロルミネセント(E Load 8, for example, organic electroluminescent (E active matrix requiring constant current drive
L:Electro-Luminescent)素子である。 L: is the Electro-Luminescent) element. そして、負荷8には、電源端子10が接続されている。 Then, the load 8, the power supply terminal 10 is connected. このようにして構成された本実施例の定電流駆動回路には、トランジスタ4及び5からなるカレントミラー回路が含まれている。 The constant current drive circuit of the present embodiment was thus constructed, it contains a current mirror circuit consisting of transistors 4 and 5.

【0020】次に、上述のように構成された本実施例の定電流駆動回路の動作について説明する。 [0020] Next, the operation of the constant current driving circuit of the present embodiment constructed as described above.

【0021】入力端子1に画像信号等の入力信号が入力されると、この信号の電圧に応じて抵抗3に電流が流れる。 [0021] When the input signal of the image signal or the like to the input terminal 1 is input, a current flows to the resistor 3 in accordance with the voltage of the signal. そして、抵抗3に流れる電流は、ドレイン及びソースが相互に接続されたトランジスタ4に流れ、トランジスタ4にゲート−ソース間電圧が発生する。 Then, the current flowing through the resistor 3, flows through the transistor 4 whose drain and source are connected to each other, the gate transistor 4 - source voltage is generated.

【0022】そして、制御端子2に入力されたアドレス信号がロウレベルでスイッチ用トランジスタ6が導通状態の場合には、トランジスタ4に発生したゲート−ソース間電圧は、スイッチ用トランジスタ6を介して電荷保持容量素子7及びトランジスタ5のゲートに印加される。 [0022] Then, when the address signal input to the control terminal 2 is in a conducting state switching transistor 6 at low level, the gate occurred transistor 4 - source voltage, charge retention through the switching transistor 6 It is applied to the gate of the capacitor 7 and the transistor 5. このとき、トランジスタ4及び5はカレントミラー回路を構成しているため、抵抗3に流れる電流に比例した電流がトランジスタ5のドレイン電流として流れる。 At this time, the transistors 4 and 5 for constituting a current mirror circuit, current proportional to the current flowing through the resistor 3 flows as the drain current of the transistor 5.
即ち、トランジスタ4とトランジスタ5とのパターンサイズの比によって決定される電流、例えばトランジスタ4及び5が同一パターンサイズで構成されている場合には、抵抗3に流れる電流と等しい電流がトランジスタ5 That is, the current that is determined by the ratio of the pattern size of the transistors 4 and 5, for example, when the transistors 4 and 5 are formed by the same pattern size, the current equal to the current flowing through the resistor 3 the transistor 5
のドレインとソースとの間を流れる。 Flowing between the drain and the source of. これにより、負荷8が駆動される。 Thus, the load 8 is driven.

【0023】次に、制御端子2に入力されたアドレス信号がハイレベルでスイッチ用トランジスタ6が遮断状態となると、トランジスタ4及び5からなるカレントミラー回路も遮断される。 Next, when the address signal inputted to the control terminal 2 is the switching transistor 6 are cut off at the high level, a current mirror circuit consisting of transistors 4 and 5 are also cut off. しかし、スイッチ用トランジスタ6が導通状態の時に、入力端子1の信号電圧に応じた電流がトランジスタ4に流れ、その電流に応じたトランジスタ4のゲート−ソース間電圧が電荷保持容量素子7に印加されている。 However, when the transistor 6 conductive state switch, current corresponding to the signal voltage at the input terminal 1 flows through the transistor 4, a gate of the transistor 4 in accordance with the current - source voltage is applied to the charge storage capacitor 7 ing. このため、スイッチ用トランジスタ6 For this reason, the switching transistor 6
が遮断された後にも、この電圧がトランジスタ5のゲートに印加されるので、このゲート電圧に応じた電流が負荷8に供給される。 There after being blocked also because this voltage is applied to the gate of the transistor 5, a current corresponding to the gate voltage is supplied to the load 8. 即ち、スイッチ用トランジスタ6が遮断状態でも、負荷8には入力端子1の信号電圧に応じた電流が供給され続ける。 That is, even in the transistor 6 is blocked state switch, the load 8 is a current corresponding to the signal voltage at the input terminal 1 is continuously supplied.

【0024】従って、本実施例をアクティブマトリクス方式の有機EL素子の駆動回路に適用した場合、入力端子1には入力画像信号が入力され、その階調データによって発光輝度が変化する。 [0024] Therefore, when the present embodiment is applied to a driving circuit of the organic EL device of active matrix type, the input terminal 1 input image signal is input, the emission luminance varies depending on the gradation data. また、制御端子2にはアドレス信号が入力され、入力端子1からの画像信号に対応する画素が電荷保持容量素子7に選択的に読み込まれ、次の新しい画像信号が入力されるまで電荷が保持され、画素は発光し続ける。 Also, the control to the terminal 2 address signal is input, the pixel charge storage capacitor element 7 corresponding to the image signal from the input terminal 1 is read selectively, charges held until next new image signal is input is, the pixel continues to emit light.

【0025】このように、本実施例によれば、スイッチ用トランジスタ6のオン抵抗による電圧降下を無視できるため、カレントミラー回路の整合性が改善される。 [0025] Thus, according to this embodiment, since a negligible voltage drop due to the on resistance of the switching transistor 6, the consistency of the current mirror circuit is improved.

【0026】また、従来技術のように大電流経路にスイッチ素子を設ける場合には、オン抵抗を低減するために素子サイズを大きくする必要があったが、本実施例においてスイッチ用トランジスタ6を流れる電流は無視できるほど小さいので、最小寸法のトランジスタにて構成することができる。 Further, in the case where the switching element for large current path as in the prior art, it has been necessary to increase the element size in order to reduce the on-resistance, through the switching transistor 6 in this embodiment since the current is negligibly small, it can be configured by transistors of minimum size. 従って、半導体集積回路に適用する場合にも、安価なものとなる。 Therefore, even when applied to a semiconductor integrated circuit, an inexpensive.

【0027】更に、有機ELの駆動回路として薄膜トランジスタ(TFT)を使用する場合にも、大きなスイッチ用トランジスタは不要であるため、画素の開口率の向上をさせ有機ELの輝度を向上させることが可能である。 Furthermore, when using a thin film transistor (TFT) as the driving circuit of the organic EL also, since a large switching transistor is unnecessary, it is possible to improve the luminance of the organic EL is an improvement in the aperture ratio of the pixel it is. また、薄膜トランジスタによりカレントミラー回路を構成するトランジスタ4及び5を作製する場合、トランジスタ4及び5を相互に隣接して配置することができるため、製造に起因するトランジスタのパラメータのバラツキを低く抑制することができる。 In the case of manufacturing a transistor 4 and 5 constituting a current mirror circuit by a thin film transistor, it is possible to arrange adjacent transistors 4 and 5 to each other, to suppress low variation of parameters of the transistor due to manufacturing can. 従って、トランジスタ4及び5からなるカレントミラー回路の整合性が向上する。 Accordingly, the consistency of the current mirror circuit consisting of transistors 4 and 5 are improved.

【0028】次に、本発明の第2の実施例について説明する。 Next, a description will be given of a second embodiment of the present invention. 本実施例には、レベルシフト用のダイオード構造を有するトランジスタが配設されている。 In this embodiment, the transistor is provided with a diode structure for a level shift. 図2は本発明の第2の実施例に係る定電流駆動回路を示す回路図である。 Figure 2 is a circuit diagram showing a constant current driving circuit according to a second embodiment of the present invention. なお、図2に示す第2の実施例において図1に示す第1の実施例と同一の構成要素には、同一の符号を付してその詳細な説明は省略する。 Note that the first embodiment and the same components shown in FIG. 1 in the second embodiment shown in FIG. 2, a detailed description thereof will be omitted given the same reference numerals.

【0029】本実施例に係る定電流駆動回路には、トランジスタ4のソースにドレインが接続され接地端子11 The constant current driving circuit according to the present embodiment is connected drain to source of the transistor 4 grounding terminal 11
にソースが接続されダイオード構造を有するNチャネルMOSトランジスタ12が設けられている。 N-channel MOS transistor 12 having a source having a connected diode structure is provided. また、トランジスタ5のソースにドレインが接続され接地端子11 Further, a drain connected to the source of the transistor 5 the ground terminal 11
にソースが接続されダイオード構造を有するNチャネルMOSトランジスタ13が設けられている。 N-channel MOS transistor 13 having a source having a connected diode structure is provided.

【0030】第1の実施例においては、カレントミラー回路が2個のNチャネルMOSトランジスタから構成され、スイッチ用トランジスタにPチャネルMOSトランジスタが使用されているが、このような構成のもとでP [0030] In the first embodiment, is composed of a current mirror circuit are two N-channel MOS transistors, but P-channel MOS transistor in the switching transistor is used, under P of this structure
チャネルMOSトランジスタのオン電圧がNチャネルM ON voltage of the channel MOS transistor is an N-channel M
OSトランジスタのオン電圧より大きい場合には、スイッチ用トランジスタ6を導通させるためには、制御端子2の電圧を接地端子11の電圧以下にする必要がある。 OS when the transistor is greater than the ON voltage, in order to conduct the switching transistor 6, it is necessary to set the voltage of the control terminal 2 below the voltage of the ground terminal 11.

【0031】第2の実施例においても、制御端子2の電圧を接地端子11の電圧以下にする必要があるが、レベルシフト用にトランジスタ12及び13が設けられているので、容易に適応することが可能である。 [0031] In the second embodiment, the voltage of the control terminal 2 should be less than or equal to the voltage of the ground terminal 11, the transistors 12 and 13 are provided for the level shift, be readily adapted it is possible.

【0032】なお、この場合、カレントミラー回路の整合性を確保するため、トランジスタ12及び13は相互に同一導伝形式、つまりチャネルの導電型が同じである必要がある。 [0032] In this case, in order to ensure the integrity of the current mirror circuit, the transistors 12 and 13 each other in the same-conduction type, i.e. it is necessary conductivity type channel are the same. 本実施例においては、NチャネルMOSトランジスタが使用されているが、PチャネルMOSトランジスタを使用されても同様の効果が得られる。 In this embodiment, the N-channel MOS transistor is used, the same effect can be obtained be using a P-channel MOS transistor.

【0033】また、第1の実施例においても、NチャネルMOSトランジスタとPチャネルMOSトランジスタとのオン電圧が等しければ何ら問題はない。 [0033] Also in the first embodiment, there is no problem being equal on voltage of the N-channel MOS transistor and P-channel MOS transistor.

【0034】次に、本発明の第3の実施例について説明する。 Next, a description will be given of a third embodiment of the present invention. 本実施例においては、スイッチ用トランジスタの導伝形式がカレントミラー回路を構成するトランジスタのそれと同一のものとなっている。 In the present embodiment,-conduction type of the switching transistor is in the ones same as those of the transistors constituting the current mirror circuit. 図3は本発明の第3 Figure 3 is a third of the present invention
の実施例に係る定電流駆動回路を示す模式図である。 It is a schematic diagram showing a constant current driving circuit according to the embodiment. なお、図3に示す第3の実施例において図1に示す第1の実施例と同一の構成要素には、同一の符号を付してその詳細な説明は省略する。 Note that the first embodiment and the same components shown in FIG. 1 in a third embodiment shown in FIG. 3, and the detailed description is omitted denoted by the same reference numerals.

【0035】本実施例に係る定電流駆動回路においては、トランジスタ4のゲートとトランジスタ5のゲートとの間にNチャネルMOSトランジスタであるスイッチ用トランジスタ16が接続されている。 [0035] In the constant current driving circuit according to the present embodiment, the switching transistor 16 is an N-channel MOS transistor between the gate of the gate of the transistor 5 of the transistor 4 is connected.

【0036】このように構成された本実施例においては、スイッチ用トランジスタ16とカレントミラー回路を構成するトランジスタ4及び5とのオン電圧が相違していても、制御端子2の電圧を接地端子11の電圧以下にする必要が無くなる。 [0036] In such embodiment, which is configured, be different on-voltage of the transistor 4 and 5 constituting the transistor 16 and the current mirror circuit switch, grounding the voltage of the control terminal 2 terminal 11 must be below the voltage is eliminated.

【0037】なお、第1の実施例においては、アドレス信号がロウレベルのときにカレントミラー回路が動作状態となるが、第3の実施例においては、アドレス信号がハイレベルのときにカレントミラー回路が動作状態となる。 [0037] In the first embodiment, although the address signal is a current mirror circuit is in an operating state when a low level, in the third embodiment, the current mirror circuit when the address signal is high-level in the operating state.

【0038】次に、本発明の第4の実施例について説明する。 Next, a description will be given of a fourth embodiment of the present invention. 本実施例においては、スイッチ用トランジスタは、カレントミラー回路を構成するトランジスタのゲート間ではなく、入力端子側に接続されたトランジスタのゲートとドレインとの間に接続される。 In the present embodiment, the switching transistor, rather than between the gates of the transistors constituting the current mirror circuit is connected between the gate and the drain of the transistor connected to the input terminal side. 図4は本発明の第4の実施例に係る定電流駆動回路を示す回路図である。 Figure 4 is a circuit diagram showing a constant current driving circuit according to a fourth embodiment of the present invention. なお、図4に示す第4の実施例において図1に示す第1の実施例と同一の構成要素には、同一の符号を付してその詳細な説明は省略する。 Note that the first embodiment and the same components shown in FIG. 1 in the fourth embodiment shown in FIG. 4, a detailed description thereof will be omitted given the same reference numerals.

【0039】本実施例においては、トランジスタ4のゲートとトランジスタ5のゲートとが直接接続されている。 [0039] In this embodiment, the gates of the transistor 5 of the transistor 4 is connected directly. また、NチャネルMOSトランジスタであるスイッチ用トランジスタ26がトランジスタ4のゲートとドレインとの間に接続されている。 Further, the switching transistor 26 is an N-channel MOS transistor is connected between the gate and the drain of the transistor 4.

【0040】このように構成された本実施例においては、スイッチ用トランジスタ26は、カレントミラー回路を構成するトランジスタ4及び5のゲート間ではなく、トランジスタ4のゲートとドレインとの間に接続されているので、スイッチ用トランジスタ26のオン抵抗による電圧降下のためにカレントミラー回路の整合性が悪化するということは完全に防止される。 [0040] In the present embodiment having such a configuration, the switching transistor 26, rather than between the gate of the transistor 4 and 5 constituting a current mirror circuit, is connected between the gate and the drain of the transistor 4 because there, is totally prevented that integrity of the current mirror circuit for the voltage drop due to the on resistance of the switch transistor 26 is deteriorated.

【0041】また、第4の実施例においては、制御端子2がロウレベルでカレントミラー回路が遮断状態になったとき、スイッチ用トランジスタ26は遮断される。 Further, in the fourth embodiment, when the control terminal 2 by the current mirror circuit becomes blocked state low level, the switching transistor 26 is cut off. 従って、入力端子1がハイレベルの状態でもトランジスタ4は遮断されるため、抵抗3及びトランジスタ4の経路には電流が流れなくなり、消費電力が低下する。 Therefore, the input terminal 1 is the transistor 4 is blocked in the high level state, the path of the resistor 3 and the transistor 4 current does not flow, the power consumption is reduced. 従って、本実施例を例えば有機EL素子等を使用した画像表示装置の駆動回路に適用した場合、画像表示装置には複数個の有機EL素子が縦横に配列されているので、著しい省電力化が期待できる。 Therefore, when applied to a drive circuit of an image display apparatus using the present embodiment, for example, an organic EL element or the like, since a plurality of organic EL elements are arranged in a matrix in an image display device, a significant power saving is It can be expected.

【0042】次に、本発明の第5の実施例について説明する。 Next, a description will be given of a fifth embodiment of the present invention. 本実施例においては、入力端子と抵抗との間にソースフォロワ用トランジスタが接続される。 In the present embodiment, the source follower transistor is connected between the input terminal and the resistor. 図5は本発明の第5の実施例に係る定電流駆動回路を示す回路図である。 Figure 5 is a circuit diagram showing a constant current driving circuit according to a fifth embodiment of the present invention. なお、図5に示す第5の実施例において図1に示す第1の実施例と同一の構成要素には、同一の符号を付してその詳細な説明は省略する。 Note that the first embodiment and the same components shown in FIG. 1 in the fifth embodiment shown in FIG. 5, and the detailed description is omitted denoted by the same reference numerals.

【0043】本実施例には、入力端子1にゲートが接続されNチャネルMOSトランジスタであるソースフォロワ用トランジスタ9が設けられており、その一端は抵抗3に、その他端は電源端子10に接続されている。 [0043] This example demonstrates that the source follower transistor 9 is an N-channel MOS transistor whose gate is connected to the input terminal 1 is provided, one end of the resistor 3 and the other end connected to the power supply terminal 10 ing. また、トランジスタ4及び5のゲート間には、スイッチ用トランジスタ36が接続されている。 Further, between the gate of the transistor 4 and 5, switching transistor 36 is connected. このスイッチ用トランジスタ36はNチャネルMOSトランジスタであってもPチャネルMOSトランジスタであってもよい。 The switching transistor 36 can be a P-channel MOS transistor may be an N-channel MOS transistor.

【0044】このように構成された本実施例においては、ソースフォロワ用トランジスタ9により、入力端子1側のインピーダンスが高くてもカレントミラー回路を構成するトランジスタ4を十分に駆動させることが可能である。 [0044] In the present embodiment having such a configuration, the source follower transistor 9, it is possible to sufficiently drive the transistor 4 constituting the current mirror circuit even with a high impedance at the input terminal 1 side .

【0045】また、第1の実施例では、入力端子1がロウレベルでありインピーダンスが低い場合には、電荷保持容量素子7に蓄積されていた電荷がスイッチ用トランジスタ6が遮断状態のときにスイッチ用トランジスタ6 [0045] In the first embodiment, when the input terminal 1 is low impedance at a low level, the switch when the charge accumulated in the charge storage capacitor element 7 of the transistor 6 is blocked state switch transistor 6
のオフ抵抗と抵抗3との経路で放電することにより、電荷保持の機能が十分ではなくなることがあるが、第5の実施例にはトランジスタ9が設けられているので、電荷の放電が防止される。 By discharging the path between the off-resistance resistor 3, but the function of charge retention may become insufficient, to the fifth embodiment, since the transistor 9 is provided, the discharge of the charges are prevented that.

【0046】次に、本発明の第6の実施例について説明する。 Next, a description will be given of a sixth embodiment of the present invention. 本実施例は、第4の実施例と第5の実施例とを組み合わせたものである。 This embodiment is a combination of the fourth embodiment and the fifth embodiment. 図6は本発明の第6の実施例に係る定電流駆動回路を示す回路図である。 6 is a circuit diagram showing a constant current driving circuit according to a sixth embodiment of the present invention. なお、図6に示す第6の実施例において図4に示す第4の実施例又は図5に示す第5の実施例と同一の構成要素には、同一の符号を付してその詳細な説明は省略する。 Incidentally, in the fourth embodiment or the fifth embodiment and the same components of FIG. 5 shown in FIG. 4 in the sixth embodiment shown in FIG. 6, its detailed denoted by the same reference numerals explained It omitted.

【0047】本実施例においては、トランジスタ4のゲートとトランジスタ5のゲートとが直接接続されている。 [0047] In this embodiment, the gates of the transistor 5 of the transistor 4 is connected directly. また、NチャネルMOSトランジスタであるスイッチ用トランジスタ26がトランジスタ4のゲートとドレインとの間に接続されている。 Further, the switching transistor 26 is an N-channel MOS transistor is connected between the gate and the drain of the transistor 4. 更に、本実施例には、入力端子1にゲートが接続されNチャネルMOSトランジスタであるソースフォロワ用トランジスタ9が設けられており、その一端は抵抗3に、その他端は電源端子10 Further, the present embodiment, the source follower transistor 9 gates are connected to N-channel MOS transistor is provided to the input terminal 1, the one end of the resistor 3 and the other end the power supply terminal 10
に接続されている。 It is connected to the.

【0048】このように構成された本実施例においては、第4及び第5の実施例による双方の効果が得られる。 [0048] In the present embodiment having such a configuration, the effects of both of the fourth and fifth embodiment can be obtained. 即ち、レントミラー回路の整合性が改善される。 That is, the consistency of the rent mirror circuit is improved. また、カレントミラー回路を構成するトランジスタ4の駆動性及び電荷保持容量素子7の放電特性が改善される。 The discharge characteristics of the driven and the charge storage capacitor 7 of transistor 4 constituting the current mirror circuit is improved.
更に、入力端子1がハイレベル、制御端子2がロウレベル、カレントミラー回路が遮断状態のときには、抵抗3 Furthermore, the input terminal 1 is high level, when the control terminal 2 is at a low level, the current mirror circuit cut-off state, the resistance 3
及びトランジスタ4の電流経路が遮断状態となるため、 And a current path of the transistor 4 are cut off,
省電力化の効果もある。 The effect of power saving also.

【0049】なお、前述の種々の実施例の組み合わせは第6の実施例に示すものに限定されるものではない。 [0049] Combinations of the various embodiments described above are not limited to those shown in the sixth embodiment. 例えば、第5の実施例と第2又は第3の実施例とを組み合わせてもよい。 For example, it may be combined with the fifth embodiment and the second or third embodiment.

【0050】 [0050]

【発明の効果】以上詳述したように、本発明によれば、 As described above in detail, according to the present invention,
スイッチ用トランジスタのオン抵抗による電圧降下を無視できるため、カレントミラー回路の整合性を改善することができる。 Since negligible voltage drop due to the on resistance of the switching transistor, it is possible to improve the consistency of the current mirror circuit. また、スイッチ用トランジスタを流れる電流は無視できるほど小さいくなるで、スイッチ用トランジスタを小型化することができ、半導体集積回路で構成する場合にも、コストの上昇を抑制することができる。 Further, the current flowing through the switching transistor is smaller Naru Ku negligibly, the switching transistor can be miniaturized, even in the case of a semiconductor integrated circuit, it is possible to suppress an increase in cost. 更に、種々のトランジスタを薄膜トランジスタとし、有機エレクトロルミネセント素子の駆動回路に適用する場合、大きなスイッチ用トランジスタは必要ないので、画素の開口率を向上させ輝度を向上させることができる。 Furthermore, the various transistors and a thin film transistor, when applied to a driving circuit of an organic electroluminescent device, a large switching transistor is not required, thereby improving the brightness to improve the aperture ratio of the pixel.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施例に係る定電流駆動回路を示す回路図である。 Is a circuit diagram showing a constant current driving circuit according to a first embodiment of the present invention; FIG.

【図2】本発明の第2の実施例に係る定電流駆動回路を示す回路図である。 Is a circuit diagram showing a constant current driving circuit according to a second embodiment of the present invention; FIG.

【図3】本発明の第3の実施例に係る定電流駆動回路を示す模式図である。 3 is a schematic diagram showing a constant current driving circuit according to a third embodiment of the present invention.

【図4】本発明の第4の実施例に係る定電流駆動回路を示す回路図である。 Is a circuit diagram showing a constant current driving circuit according to a fourth embodiment of the present invention; FIG.

【図5】本発明の第5の実施例に係る定電流駆動回路を示す回路図である。 5 is a circuit diagram showing a constant current driving circuit according to a fifth embodiment of the present invention.

【図6】本発明の第6の実施例に係る定電流駆動回路を示す回路図である。 6 is a circuit diagram showing a constant current driving circuit according to a sixth embodiment of the present invention.

【図7】従来の定電流駆動回路を示す回路図である。 7 is a circuit diagram showing a conventional constant current driving circuit.

【符号の説明】 DESCRIPTION OF SYMBOLS

1、101;入力端子 2、102;制御端子 3、103;抵抗 4、5、6、9、12、13、16、26、36、10 1,101; input 2,102; control terminal 3,103; resistance 4,5,6,9,12,13,16,26,36,10
4、105、106;トランジスタ 7、107;容量素子 8、108;負荷 10、110;電源端子 11、111;接地端子 4,105,106; transistor 7,107; capacitive element 8,108; load 10,110; power supply terminal 11, 111; ground terminal

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Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 入力端子と、この入力端子にドレインが接続され接地にソースが接続された第1のトランジスタと、この第1のトランジスタのゲート及びドレインに接続されたスイッチ用トランジスタと、このスイッチ用トランジスタのゲートに接続されこのスイッチ用トランジスタの導通と非導通とを切替える信号が入力される制御端子と、前記スイッチ用トランジスタにゲートが接続され接地にソースが接続され前記第1のトランジスタと共にカレントミラー回路を構成する第2のトランジスタと、この第2のトランジスタのゲートに一方の電極が接続され接地に他方の電極が接続された容量素子と、を有することを特徴とする定電流駆動回路。 And 1. A input terminal, a first transistor source to ground the drain is connected to the input terminal is connected, and the first of the connected switching transistor to the gate and drain of the transistor, the switch a control terminal conducting a signal for switching the non-conduction of the connected transistor switch to the gate of use transistor is input, the current together with the first transistor source connected to ground is connected a gate to said switching transistor second transistor and a constant current drive circuit, wherein the one electrode to the gate of the second transistor; and a capacitor and the other electrode connected to ground is connected to constitute a mirror circuit.
  2. 【請求項2】 前記第1及び第2のトランジスタのチャネルの導電型は、前記スイッチ用トランジスタのチャネルの導電型と相違し、前記第1のトランジスタのソースと接地との間に接続された第1のレベルシフト用ダイオードと、前記第2のトランジスタのソースと接地との間に接続された第2のレベルシフト用ダイオードと、を有することを特徴とする請求項1に記載の定電流駆動回路。 Wherein the conductivity type of the channel of the first and second transistors, different from the conductivity type of the channel of the switching transistor, the first connected between the source and the ground of the first transistor and 1 of the level shift diode, the constant current driving circuit according to claim 1, characterized in that it comprises a second level shift diode connected between the source and the ground of the second transistor .
  3. 【請求項3】 前記第1及び第2のトランジスタのチャネルの導電型は、前記スイッチ用トランジスタのチャネルの導電型と同じであることを特徴とする請求項1に記載の定電流駆動回路。 Wherein the first and the channel conductivity type of the second transistor, a constant current drive circuit according to claim 1, characterized in that the same as the conductivity type of the channel of the switching transistor.
  4. 【請求項4】 入力端子と、この入力端子にドレインが接続され接地にソースが接続された第1のトランジスタと、この第1のトランジスタのゲートとドレインとの間に接続されたスイッチ用トランジスタと、このスイッチ用トランジスタのゲートに接続されこのスイッチ用トランジスタの導通と非導通とを切替える信号が入力される制御端子と、前記第1のトランジスタのゲートにゲートが接続され接地にソースが接続され前記第1のトランジスタと共にカレントミラー回路を構成する第2のトランジスタと、この第2のトランジスタのゲートに一方の電極が接続され接地に他方の電極が接続された容量素子と、を有することを特徴とする定電流駆動回路。 4. A input terminal, a first transistor having a drain source to ground is connected is connected to the input terminal, and a switch connected transistor between the gate and the drain of the first transistor , it is connected to the gate of the switching transistor and a control terminal to which a signal for switching conduction and non-conduction and the switching transistor is inputted, the gate to the gate of the first transistor source connected to the coupled ground the a second transistor constituting a current mirror circuit together with the first transistor, a capacitor element and the other electrode connected to ground one electrode connected to the gate of the second transistor, and wherein a constant current driving circuit for.
  5. 【請求項5】 前記入力端子と前記第1のトランジスタのドレインとの間に接続された抵抗を有することを特徴とする請求項1乃至4のいずれか1項に記載の定電流駆動回路。 5. The constant current driving circuit according to any one of claims 1 to 4, characterized in that it has a resistor connected between the drain of the input terminal and the first transistor.
  6. 【請求項6】 前記入力端子と前記抵抗との間に接続されたソースフォロワ用トランジスタを有することを特徴とする請求項5に記載の定電流駆動回路。 6. The constant current driving circuit according to claim 5, characterized in that a source connected follower transistor between said resistor and said input terminal.
  7. 【請求項7】 前記第2のトランジスタのドレインは有機エレクトロルミネセント素子に接続されることを特徴とする請求項1乃至6のいずれか1項に記載の定電流駆動回路。 Wherein said constant current drive circuit according to any one of claims 1 to 6 the drain of the second transistor is characterized in that it is connected to the organic electroluminescent element.
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