JP2000031952A - Clock changeover device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock changeover device that can suppress a phase fluctuation amount with respect to a time interval without sacrificing a phase response characteristic. SOLUTION: In the case of switching a clock, a hold-over circuit 16 first holds a clock output signal 24 just before the switching and switches a reference clock 6 into a new reference clock after that. The hold-over state is released and a re-synchronization process is entered after by short-circuiting an operational amplifier feedback resistor 14 in this state to decrease a loop gain of a loop filter 100. In the re-synchronization process, a delay section 200 is used to restore the loop gain of the loop filter 100 in a timing when a phase of the clock output signal is just close to a phase of the new reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching device, for example, according to ITU-T Recommendation G. 813 relates to a clock switching device that can satisfy the required characteristics.

[0002]

2. Description of the Related Art In a highly information-oriented society in recent years, synchronization of transmission systems is a worldwide trend, and unification of hierarchies is being promoted. In such a situation, SD
The H (Synchronous Digital Hierarchy) system is becoming the standard for trunk optical transmission systems.
16, that is, up to a system of 2.488 Gbit / s has been put to practical use.

In a synchronous network such as the SDH, the transmission device operates in synchronization with an externally supplied reference clock. The clock transmission system that distributes this reference clock is duplicated in case of failure, so if one of the systems fails, switching to the other system eliminates the risk of system down. I have.

By the way, clock phases of respective systems which are generally duplicated have a shift. For this reason, phase fluctuations that occur when the clock is switched become a problem. That is, since the output signal of the SDH transmission device is generated based on the reference clock, the phase fluctuation generated at the time of switching becomes the phase fluctuation of the output signal as it is. As a result, in the receiving station receiving apparatus that receives this output signal, jitter and wander are added to the input signal.

[0005] If left unchecked, the transmission quality deteriorates, which is not preferable. In recent years, attempts have been made to define the phase variation of the output of the SDH transmission apparatus in association with the input jitter tolerance of the reception apparatus.
TU-T Recommendation G. 813 (August 1996).

[0006] FIG. 12 and FIG. 13 shown in this recommendation define phase fluctuation characteristics at the time of reference clock switching. Among them, FIGURE 12 is shown in FIG.
FIG. 20B shows the FIGURE 13. FIG.
According to (a), it is required that the maximum value of the phase change amount occurring before and after the clock switching process is 1 μsec or less, and that the time required for the switching be within 15 seconds.

Also, in order to prevent the instantaneous frequency fluctuation from exceeding an upper limit value over the entire switching process, the phase fluctuation in a region where the observation time is short is set to be small, and FIG. The value is 7.5 ppm. According to FIG. 20 (a), in order to satisfy the phase fluctuation characteristics shown in this recommendation, it is necessary to synchronize with a new reference phase with a slow time of 1 second or more.

FIG. 20B shows MTIE (Maximum Time Interval Error) characteristics required by the above recommendation. Here, the MTIE indicates an allowable phase difference with respect to the elapsed time (observation time window), and the horizontal axis is plotted as the observation time window and the vertical axis is plotted as the phase difference. FIG. 20B also shows that the phase fluctuation in the region where the observation time is short is set to be small.

In this recommendation, almost all other characteristics related to the clock system of the SDH transmission apparatus, such as other frequency pull-in ranges, phase fluctuation characteristics in a synchronous state, etc., are defined, and the interface specifications are nearing completion. .

In the future SDH transmission system, the above G. It is necessary to design phase fluctuation characteristics at the time of clock switching based on the 813 recommendation. However, realizing a clock switching device that satisfies the characteristics required in this recommendation involves the following difficulties.

That is, G. In order to satisfy the phase fluctuation characteristics required by the 813 recommendation, it is necessary to make the time constant for the frequency response extremely slow. However,
If the time constant is simply reduced, the response to minute phase fluctuations (that is, the response to the reference clock itself without switching) will also be delayed, causing the following problem.

First, since the reference clock is hierarchically distributed from the higher-order transmission device to the lower-order transmission device, the response characteristic of the lower-order transmission device to the higher-order transmission device is considerably increased. Otherwise, the clock cannot be distributed. However, the response characteristics of DCS (Digital Clock Supply Device) as the highest clock supply device in the SDH transmission system are described in G. It is close to the characteristics required by 813 Recommendation.

That is, G. S to meet the 813 Recommendation
If the time constant of the clock switching device provided in the DH transmission device is reduced, the response of the lower SDH transmission device cannot catch up with the fluctuation of the DCS clock.
Therefore, the clock cannot be transmitted to the lower-order SDH transmission device (in other words, the clock chain becomes unstable).

However, if the time constant is made faster, the width of the frequency pull-in range (capture range) and the following operation characteristics with respect to instantaneous frequency fluctuations (for example, when the operation mode is changed from the free-running mode to the external synchronization mode) are obtained. Not only is it difficult to secure the clock switching device, but also a clock switching device that meets the requirements of the recommendation cannot be created in the first place.

[0015]

As described above,
G. FIG. When actually making a clock switching device based on the 813 recommendation, the response characteristic to the phase is sacrificed,
For example, there has been a dilemma that it is difficult to ensure stability during a clock chain.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a clock switching device capable of suppressing the amount of phase fluctuation with respect to a time interval without sacrificing phase response characteristics.

[0017]

According to a first aspect of the present invention, a clock signal is selected from a plurality of clock signals supplied via a communication network and is used as a reference clock signal. Clock selecting means for switching and outputting as; an oscillating means for outputting an oscillating signal having a frequency corresponding to the level of a given control signal; a phase comparing means for detecting a phase difference between the reference clock signal and the oscillating signal; Generating a control signal to the oscillating means for causing the phase of the oscillation signal to converge to the phase of the reference clock signal based on the phase difference detected by the means; Generating means, holding means for selectively holding the oscillation means by holding a control signal generated by the means, and clock selecting means. When it becomes necessary to switch the quasi-clock signal, the oscillating means is set to the hold state through the oscillating hold means to keep the state of the oscillating signal at that time, and in this state, the clock selection means switches the reference clock signal Switching control means for releasing the hold state of the oscillating means through the hold means, and changing the time constant of the control signal generating means from the state before holding to a larger value while the hold state of the oscillating means continues. And a time constant control means for changing the time constant of the control signal generation means to a value before the hold when a predetermined period after the release of the hold state has elapsed.

With this configuration, for example, one of the main system and sub system clock signals supplied from the upper network or the like is output from the clock selection means as a reference clock signal. In a steady operation state, an oscillation signal synchronized with the phase of a clock signal of any system is output (as a clock output). At this time, the time constant of the control signal generation means is set to a small state, so that the clock output quickly follows the phase fluctuation of the reference clock signal.

For example, it is assumed that the clock signal of the main system is selected in the normal operation state, and it is necessary to switch to the clock signal of the sub system due to the occurrence of a failure or the like. Then, the oscillation means is first held by the switching control means,
The phase of the oscillation signal at that time is maintained for a certain time. While the hold state continues, the clock selection means switches from the main system to the sub system clock signal, and a new sub system clock signal is output as a reference clock signal. Further, the time constant of the control signal generation means is set to a state larger than the steady state.

When the above control is completed and the hold state is released, a re-synchronization process is started, and the phase of the oscillation signal slowly converges (with a large time constant) to the phase of the clock signal of the sub-system. Go. From the start of this resynchronization process, for example, After the elapse of a predetermined period based on the 813 recommendation, the time constant is returned to the original value by the time constant control means, and thereafter, the phase of the oscillation signal rapidly converges to the phase of the clock signal of the sub-system. Will do.

In the resynchronization process, there must be a timing at which the phase of the converging oscillation signal matches (or approaches) the phase of the new reference clock signal. This timing should be determined by design according to the set value of the time constant and the frequency and phase of the supplied clock signal. Therefore, by setting the period from the start of the resynchronization process to the return of the time constant to the above timing, it is possible to minimize the amount of phase change in the rapid convergence process. .

With this configuration, it is possible to minimize the amount of phase fluctuation with respect to time in the entire process related to the switching of the clock output. Such phase fluctuation characteristics are described in G. This is a very good match for the characteristics required in the 813 Recommendation.

Further, in the normal operation state after the switching, the time constant for phase tracking is kept small. As a result, a slight phase change (phase fluctuation) of the reference clock signal
You will be able to follow immediately.

According to the second aspect of the present invention, the time constant control means may control the phase difference between the new reference clock signal and the oscillation signal after switching of the clock selection means after releasing the hold state of the oscillation means. The time constant of the control signal generating means is returned to the value before the hold when the value becomes smaller than a predetermined value.

As described above, the time constant may be restored more directly based on the phase difference between the reference clock signal and the oscillation signal.

In the third aspect of the present invention, the switching control means may be arranged such that a phase difference between the new reference clock signal after the clock switching by the clock selecting means and the oscillation signal is smaller than a predetermined value. At this time, the hold state of the oscillation means is released through the hold means. That is, the time constant for the convergence of the phase in the control signal generation means is fixed, and the hold state is changed to a predetermined value based on the criterion, based on the criterion. It continued until the point where it became smaller.

In this case, the time until phase convergence is extended, The phase change can be realized in accordance with the 813 recommendation.

According to a fourth aspect of the present invention, one clock signal is selected from a plurality of clock signals supplied via a communication network and is used as a reference instead of the configuration of the first and second aspects of the present invention. Clock selection means for switching and outputting as a clock signal, and a reference clock signal sent from the clock selection means are provided. Reference clock signal holding means for outputting while holding, oscillation means for outputting an oscillation signal having a frequency corresponding to the level of a given control signal, and phase comparison means for detecting a phase difference between the reference clock signal and the oscillation signal And generating a control signal to the oscillating means for converging the phase of the oscillating signal to the phase of the reference clock signal based on the phase difference detected by the means. And a control signal generating means capable of changing a time constant for the convergence, and when the clock selecting means needs to switch the reference clock signal, the clock selecting means switches the reference clock signal. Switching control means for changing the time constant of the control signal generation means to a value larger than the state before the switching at the same time as the switching of the reference clock signal of the clock selection means by this means, and the clock signal is transmitted from the clock signal holding means. Time constant control means for returning the time constant of the control signal generation means to the value before the switching when the phase difference between the reference clock signal and the oscillation signal becomes smaller than a predetermined value. Features.

Even with such a configuration, the phase of the reference clock after switching does not fluctuate rapidly due to the operation of the holding means, and the hold state is quasi-maintained. When the phase difference between the switched reference clock and the oscillation signal becomes smaller than a predetermined value, the time constant of the phase control unit returns to the original value. Therefore, G. The phase variation characteristics required by the 813 recommendation can be realized.

[0030]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a circuit block diagram showing a configuration of a clock switching device according to a first embodiment of the present invention. The clock switching device of FIG. 1 selects one of the main system reference clock 1 and the sub system reference clock 2 supplied from the outside by the selection circuit 3 under the control of the control unit 4 and selects this. Let it be the reference clock 6. The clock output signal 2 synchronized with the reference clock 6
The clock is switched by causing a high-precision voltage controlled oscillator (VCXO) 17 to oscillate and output the clock.

Here, a part of the clock output signal 24 is branched, and the branched signal is supplied through the frequency dividing circuit 18 to the reference clock 6.
And a phase comparator 7 constituting a PLL (Phase Lock Loop) circuit, and a phase difference signal obtained by the phase comparison is supplied to a loop filter (control signal generation unit) 100, and the output of the loop filter 100 is subjected to voltage control. By using the control signal of the oscillator 17, a clock output signal 24 synchronized with the reference clock 6 is obtained.

The reference clock 6 and the output of the frequency dividing circuit 18 (phase comparison signal 8) are led to the phase comparator 7. The output of the phase comparator 7 is spurious-removed by an integration circuit including a resistor 9 and a capacitor 11 in a loop filter 100, and a reference clock 6 and a phase comparison signal 8
A DC voltage corresponding to the phase shift is supplied to an operational amplifier (op-amp) 12 via a resistor 10.

The output of the operational amplifier 12 is partially branched and negatively fed back through operational amplifier feedback resistors 14 and 13, and the resistor 10 and the operational amplifier feedback resistor 1
Based on the loop gain determined by the resistance values of 4, 13
The phase of the phase comparison signal 8 (that is, the phase of the clock output signal 24) is made to respond to the phase of the reference clock 6.

Here, the control unit 4 includes known signal interruption detection units 4a and 4b having, for example, a smoothing circuit, and when a failure occurs in the reference clock 1 of the main system or the reference clock 2 of the sub system. Upon detection of this, a clock selection control signal 5 and a holdover control signal 20 are provided.

In this embodiment, the output of the loop filter 100 is provided to the voltage controlled oscillator 17 via the holdover circuit 16. Although not shown, the holdover circuit 16 converts an input signal into a digital signal by an A / D converter, stores the digital signal in a storage element, takes out information stored in the storage element by external control, and outputs the information. An example is a device in which a D / A converter performs analog conversion and outputs the result.

That is, the holdover circuit 16
Holdover control signal 20 provided from control unit 4
At the moment when the holdover state is set, the immediately preceding input (that is, the output of the operational amplifier 12) is held, and this is given as a control voltage to the voltage controlled oscillator 17 until the holdover state is released. Have.

In this embodiment, an on / off switch 15 for short-circuiting an operational amplifier feedback resistor 14 which is one of the feedback resistors of the operational amplifier 12 is provided. The on / off switch 15 is turned on / off in accordance with L / H of a control signal (gain switching signal 19) provided from the outside, and is realized by, for example, a relay, a photocoupler, an analog switch, or the like. The feedback resistance to the operational amplifier 12 changes according to the on / off operation of the on / off switch 15, and the loop gain is switched between low and high.

Further, in this embodiment, a delay unit 200 is provided, and the holdover control signal 20 is transmitted to the delay unit 200.
, And is supplied to the on / off switch 15 as a gain switching signal 19 as a control signal. The delay unit 200 delays the branch signal of the holdover control signal 20 by the signal delay circuit 21 and further
2 is supplied to an AND circuit 23, and an AND operation with the holdover control signal 20 is performed to obtain a gain switching signal 19. It is not always necessary to provide the AND circuit 23, and the output of the signal delay circuit 21 is directly used as the gain switching signal 1
9 may be used.

Now, the operation of the clock switching device having the above configuration will be described with reference to the time chart of FIG. Here, in the steady state before the switching, the main system reference clock 1
It is assumed that has been selected. From this state, when a failure occurs in the reference clock 1 of the main system at time t1, the clock detection signal 41 (not shown, the clock detection signals 41 and 42 detect the clock supply) in the signal interruption detection unit 4a. (Which is a signal that sometimes becomes H) becomes L, and the control unit 4 sets the holdover control signal 20 to active L in response to this. This holdover control signal 2
The holdover circuit 16 (FIG. 1) that has received 0 immediately enters the holdover state, and the immediately preceding control voltage is continuously supplied to the voltage controlled oscillator 17.

At time t1, the control unit 4 sets the gain switching signal 19 to L, whereby the on / off switch 1
5 is turned on, and the loop gain of the loop filter 100 switches from high to low. This state reaches time t2, and the control unit 4 changes the holdover control signal 20 to H level again.
Continue until returning to.

During the continuation of the holdover state, the control section 4 supplies a clock selection control signal 5 to the selection circuit 3,
The reference clock 6 is switched from the reference clock 1 of the main system to the reference clock 2 of the sub system. The timing of this switching is I
TU-T Recommendation G. Based on 813, the amount of phase variation with respect to time is set in advance so as to fall within the range of FIG.

Now, the time t when τ1 has elapsed from the time t1
2, the control unit 4 causes the holdover control signal 20
Is returned to H again. Further, at time t3 when the delay amount τ2 in the signal delay circuit 21 has elapsed from this point, the gain switching signal 19 becomes H again, and the loop gain returns to the high state again.

FIG. 3 shows how the phase of the clock output signal 24 changes in such a control process. 3, the horizontal axis represents the elapsed time, and the vertical axis represents the phase of the clock output signal 24 with reference to the absolute phase system. Also, φ1 on the vertical axis,
φ2 indicates each phase when the clock output signal 24 is synchronized with the reference clocks 1 and 2 of the main system or the sub system.

At the same time when a failure occurs in the reference clock 1 of the main system, a holdover state occurs at time t1, and the phase of the clock output signal 24 gradually shifts from φ1. Of course, the amount of the deviation increases or decreases according to the characteristics of the holdover, but is not limited to recommendation G. The shift amount is kept in a range satisfying 813.

When τ1 elapses from this, the holdover state is released. At this time t2, the loop gain of the loop filter 100 has already been switched to a low state, and the sub system enters the resynchronization process with the reference clock 2 with this low loop gain. In this resynchronization process, the phase of the clock output signal 24 slowly converges while oscillating toward the phase φ2 of the reference clock 2 of the sub-system.

The manner of this change is as follows.
Varies depending on the characteristics of each element constituting the above, but the setting of the resistance values of the operational amplifier feedback resistors 13 and 14 is particularly large. That is, compared to the operational amplifier feedback resistor 13,
If the resistance value of the operational amplifier feedback resistor 14 is too large, the gain after switching becomes too small, damping is not effective, and the phase does not converge. On the other hand, if the resistance value of the operational amplifier feedback resistor 14 is too small, the gain after switching remains large, and the way of phase tracking becomes too fast. Therefore, the resistance values of the operational amplifier feedback resistors 13 and 14 are appropriately set so that the speed of the phase change is G. The characteristics required by the 813 recommendation are satisfied.

When τ2 elapses from time t2 (time t3), the loop gain of the loop filter 100 returns to the original high state, and the phase of the clock output signal 24 becomes high with a fast transient response characteristic. 2 phase φ
Converges to 2. Thus, the switching of the reference clock is completed, and the clock output signal 24 of the new phase φ2 is output to the outside.

At this time, if the loop gain is restored at the moment when the phase of the clock output signal 24 that fluctuates slowly approaches the new phase φ2, G. The phase switch should be able to be completed without protruding the characteristics required by the 813 recommendation. In the present embodiment, by setting τ2 in advance, the gain can be returned to the original at just the right timing.

That is, the timing at which the phase of the clock output signal 24 approaches the new phase after switching in the resynchronization process should be uniquely determined by design. Therefore, such a timing is obtained in advance and the signal delay circuit 21
Is set to the delay amount τ2.

From this, it can be seen that the setting of τ2 is not unique. That is, in the present embodiment, the gain is restored at the cross point C in FIG.
The gain may be restored at the cross points D and E by shortening τ2 and increasing the cross points A and C or τ2. As described above, τ2 can be freely selected, but it is preferable that the switching be completed at the earliest possible point when designing the system.

In the above description, switching from the main system reference clock 1 to the sub system reference clock 2 has been described. Conversely, switching from the sub system reference clock 2 to the main system reference clock 1 is performed. Is performed, the same procedure as above is performed.

Thus, in this embodiment, the reference clock 6
The clock output signal 24 synchronized with the
In the clock switching device of the type that generates and outputs at
The holdover circuit 16 and the delay unit 200 are provided.

At the time of switching due to the failure of a reference clock provided from the outside, the clock output signal 24 immediately before switching is first held by the holdover circuit 16, and then the reference clock 6 is switched to a new reference clock.
From this state, the loop gain of the loop filter 100 is lowered by short-circuiting the operational amplifier feedback resistor 14, the holdover state is released, and the resynchronization process is started.

Then, at the timing when the phase of the clock output signal 24 in the resynchronization process becomes close to the phase of the new reference clock by the delay unit 200, the loop filter 1
The loop gain of 00 is restored.

By doing so, even if the reference clock 6 is switched to a new phase, the phase of the clock output signal 24 is held and does not change immediately. In the resynchronization process after the release of the holdover, since the loop gain is already low, the phase of the clock output signal 24 gradually converges on the phase after the switching. When the phase of the clock output signal 24 becomes close to the phase after the switching, the loop gain returns to the original high state. Therefore, although the final phase converges rapidly, the amount of phase change is extremely small. It can be kept small.

That is, according to ITU-T Recommendation G. 813 requires that “the amount of phase change in a short time range is small,
Clock switching can be performed after satisfying the condition that "a large phase change takes time slowly".

In addition, when switching the reference clock, the time response characteristic in which a large phase change occurs is slowed down, and only the small phase change at the time of pull-in is speeded up.
When used for a transmission device, it is possible to realize a phase variation characteristic that does not exceed the jitter tolerance of an opposing receiving device.

Further, in the steady state, the loop filter 10
Since the loop gain of 0 can be kept high, the function of following the phase fluctuation of the reference clock can be enhanced, and the phase fluctuation in the synchronous clock chain state can be effectively suppressed.

FIGS. 4 and 5 show the results of measuring the operation characteristics of the clock switching device according to the present embodiment. FIG. 4 shows a time interval analyzer.
13 is a graph showing a result of measuring a relative phase after time t2, that is, based on an output phase at the time of holdover release. The manner of convergence to the phase after switching can be understood.

FIG. 5 shows the graph shown in FIG. 4 as MRTIE characteristics. The MRTI mentioned here
E means (Maximum Relative Time Interval Error), and MTIE described on the page of (Prior Art)
Has the same meaning as (MTIE is a more academic expression, and the word Relative does not seem to be appended if the reference clock used to measure the phase error is compensated for absolute accuracy.) As can be seen from FIG. High-speed fluctuations, that is, phase fluctuations in a short time are suppressed to several tens of nsec, and large phase fluctuations occur in a region of several seconds. As a whole, it falls within the range shown in FIG. 20B, and it can be seen that the standard is satisfied.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 6, the same portions as those in FIG. 1 are denoted by the same reference numerals, and only different portions will be described here. In the clock switching device of the present embodiment, the delay unit 200 in FIG. 1 is replaced with a phase detection unit 300.

In the first embodiment, the gain switching signal 1
The timing at which 9 returns to H was fixedly determined by the signal delay circuit 21. Instead, in the present embodiment, the timing at which the changing phase in the resynchronization process becomes close to (or equal to) the new phase after switching is detected, and the gain switching signal 19 is determined based on this timing. To return to.

In phase detecting section 300, reference clock 6 is inverted by inverter 67 and then delayed by delay element 62.
a and delay it with the phase comparison signal 8
It leads to the circuit 66. The output of the AND circuit 66 is an edge trigger type D flip-flop (hereinafter, referred to as D-FF).
68 and 69, respectively.

The reference clock 6 is applied to the CK terminal of the D-FF 68. A signal obtained by further delaying the output of the delay element 62 by τb at the CK terminal of the D-FF 69 (τa + τb
Signal 65).

The Q / outputs (Q inverted outputs) 70 and 71 of the D-FFs 68 and 69 are supplied to the NAND circuit 72 together with the holdover control signal 20. This NAND circuit 7
2 is an RS flip-flop (hereinafter, RS-F).
F) 74 is provided to the R terminal. Also, RS-F
The S terminal of F74 is provided with a holdover control signal 20, and the output of the RS-FF 74 is connected to the gain switching signal 1
9 is provided to the on / off switch 15.

In the above configuration, as shown in the time chart of FIG. 7, the control unit 4 immediately sets the holdover state upon detecting the clock signal interruption, switches the clock with the loop gain lowered, and then executes the holdover. To release. Then, after the elapse of τ3, the gain switching signal 1
9 returns to H and converges to the phase after switching.

FIG. 8 also shows the timing relationship of each signal in FIG. In FIG. 8, reference numeral 6 denotes a reference clock;
Is the inversion of the reference clock 6, 63 is the τa delay of the signal 61,
Reference numeral 65 denotes a (τa + τb) delay of the signal 61, and reference numeral 8 denotes a phase comparison signal (frequency-divided output of the clock output signal 24). FIG.
Shows a case where the PLL circuit becomes stable when the phase relationship between the phase comparison signal 8 and the signal 63 is shifted by exactly π.

This will be described in more detail with reference to the time chart of FIG. In FIG. 9, 67 is the output of the AND circuit 66, 70 is the Q-inverted output of the D-FF 68, and 71 is the D-FF
69 is the inverted Q output, and the other symbols correspond to FIG. 6 (FIG. 8).

In FIG. 9, the phase of the phase comparison signal 8 moves in the “←” direction (in the direction in which the phase difference decreases) in the figure. The D-FFs 68 and 69 are constantly supplied with a reference clock 6 and a signal 65 (a (τa + τb) inversion of the reference clock 6) as clock signals.

When the state of the output 67 of the AND circuit 66 is detected at the rising edge of each of these clocks, when the falling transition point of the phase comparison signal 8 passes the edge detection point in FIG. Q inverted output 71 of FF69
Changes from L to H.

On the other hand, signals 70 and 71 and holdover control signal 20 are given to NAND circuit 72 in FIG. That is, when the falling transition point of the phase comparison signal 8 passes through the edge detection point, if the holdover control signal 20 is H, that is, only when the holdover state is released, the output of the NAND circuit 72 is 73 becomes L.

At this time, the RS-FF 74 is set, the gain switching signal 19 becomes H, and the on / off switch 15
Is turned off, and the loop gain returns to the high state again. As a result, the phase of the clock output signal 24 converges on the phase φ2 of the reference clock 2 of the sub-system with high-speed transient response characteristics. Thus, the switching of the reference clock is completed, and the clock output signal 24 of the new phase φ2 is output to the outside.

That is, in the above configuration, the falling transition point of the phase comparison signal 8 is set to (τ
a + τb) The gain switching signal 19 is reset only when it is identified by the delayed edge detection point and the holdover is released at that time.

By doing so, it is possible to more appropriately control the timing at which the loop gain is restored. That is, even if the time constant of the resynchronization process changes for some reason, the timing at which the loop gain is restored is controlled accordingly, so that the reliability can be further improved.

Further, since the gain switching signal 19 is reset only when the holdover is released, the switching operation is performed in the holdover state (in this case, the phase suddenly changes). Fluctuating) can be prevented.

FIG. 10 shows the operation principle of the clock switching device of the present embodiment. It can be seen that the phase converges at the first cross point after the holdover is released at time t2.

(Modification) A modification of FIG. 11 can be given as an example of the configuration of the phase detector 300 in this embodiment. FIG. 11 illustrates an example in which an inverter is used as a delay element and the phase detection unit 300 is configured only with a digital IC.

According to the circuit shown in FIG. 11, the reference clock 6 is delayed by the inverters I1 and I2 and becomes the phase comparison reference clock 63. This phase comparison reference clock 6
3 is supplied to the AND circuit A1 together with the phase comparison signal 8, and is latched by the D-FF80. This D-FF 80 is supplied with a phase comparison reference clock 63 by inverters I3 to I6.
The signal D63 delayed by the above is supplied as a clock.

The signal NOT63 obtained by inverting the signal 63 with the inverter I3 is output together with the phase comparison signal 8 to the AND circuit A2.
, And latched by the D-FF 81. This DF
The reference clock 6 is supplied to F81 as a clock.

The Q-inverted output of the D-FF 80, the D-FF 81
Q output together with the holdover control signal 20
ND circuit NA1 and its output is applied to NAND circuit N1.
After being inverted at A2, it is latched at D-FF. D
The holdover control signal 20 is supplied to the CLR inverting terminal of the -FF 82, and the Q output thereof becomes the gain switching signal 19.

In this configuration, as shown in FIG. 12, it can be seen that phase detection is performed before and after only the rising edge of the PLL reference clock 63. That is, it does not depend on the duty of the reference clock 6.

Since the reference clock 6 is supplied from the outside, there is no compensation for the duty.
By adopting the configuration described above, the influence of the duty can be eliminated, and the operation can be further stabilized.
Note that the duty of the phase comparison signal 8 can be easily specified using a counter or the like.

Thus, in the present embodiment, the reference clock 6
The clock output signal 24 synchronized with the
The holdover circuit 16 and the phase detection unit 300 are provided in a clock switching device of the type that generates and outputs a signal.

Then, the phase of the clock output signal 24 converges to a new phase from the holdover state through a resynchronization process. At this time, the phase of the phase comparison signal 8 is changed by the phase detection unit 300 after the switching. The timing at which the phase first approaches the proper phase is detected, and the loop gain of the loop filter 100 is restored at that time.

By doing so, the same effect as that of the first embodiment can be obtained, and the phase can always converge at the first cross point, so that the time until synchronization can be shortened. Again, it is possible to follow the change in the characteristics of the PLL circuit well.

FIGS. 13 and 14 show the results of measuring the operation characteristics of the clock switching device of the present embodiment.
FIG. 13 is a graph showing a result obtained by measuring a relative phase after that based on the output phase at time t2 using the time interval analyzer. The shaking waveform as shown in the graph of FIG. 4 is no longer seen, and it can be seen that the waveform converges faster to the new phase.

FIG. 14 shows the above measurement results as MRTIE characteristics. This also indicates that the phase fluctuation in a short time is suppressed to several tens of nsec, and that a large phase fluctuation occurs in a region of several seconds. As a whole, it falls within the range shown in FIG. 20B, and it can be seen that the standard is satisfied.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 15, the same parts as those in FIG.
Here, only different portions will be described. The clock switching device of the present embodiment is different from the configuration of FIG. 6 in the configuration of the loop filter 100 and the phase detection unit 300. For the sake of distinction, the loop filter of the present embodiment is denoted by 100 ', and the phase detector is denoted by 300'.

First, the loop filter 100 'is of a fixed gain type in which the on / off switch 15 is omitted. That is, the loop gain of the loop filter 100 'is always set to a high state. On the other hand, the phase detector 300 '
Is provided with an AND circuit 91 without the NAND circuit 72 and the RS flip-flop 74. Holdover control signal 20, Q / output 70 of D-FF68, D-FF6
The Q / output 71 of 9 is supplied to the AND circuit 91, and its logical product output is supplied to the holdover circuit 16 as a control signal.

FIG. 16 shows a configuration example of the holdover circuit 16. The configuration shown in FIG. 16 can be applied to the clock switching device shown in FIGS. The holdover circuit 16 includes an analog / digital (A / D) converter 161, a latch circuit 162, and a digital / analog (D / A) converter 163, and a voltage controlled oscillator 17 provided from a loop filter 100 '. Is latched (held) by a signal from the AND circuit 91.

Next, the operation of the clock switching device in this configuration will be described. Upon detecting the clock signal interruption, the control unit 4 immediately sets the holdover control signal 20 to L and causes the holdover circuit 16 to hold the immediately preceding voltage value. Thus, the output clock 24 of the voltage controlled oscillator 17
Hold. However, at this time, the loop filter 10
The loop gain of 0 'does not change.

After a predetermined time has elapsed, the control section 4 returns the holdover control signal 20 to H. The first,
In the second embodiment, this is directly supplied to the holdover control circuit 16, where the holdover is released. On the other hand, in the configuration shown in FIG. 15, since the holdover control signal 20 is passed through the AND circuit 91, the signal applied to the holdover control circuit 16 is still L at this point, so that the holdover is not released. .

That is, as shown in the description of the second embodiment, the signal 71 does not become H unless the phase of the phase comparison signal 8 matches the phase of the clock signal after switching.
That is, in this embodiment, the holdover is released when the phase of the clock output signal 24 matches the phase of the clock signal after the switching.

FIG. 17 shows the principle of the phase change in the above operation. FIG. 17A shows the phase change diagram of FIG. 3 for comparison.
As shown in FIG. The scale of the horizontal axis (time) in FIGS. 17A and 17B is the same. That is, FIG.
In (a), the holdover is released at time t2 and approaches the new phase φ2 with a low loop gain, whereas in FIG. 17 (b), the holdover is continued as it is,
Despite the high loop gain, it approaches phase φ2 more slowly. Then, the holdover is released when the phase of the clock after switching matches φ2, and the clock after switching converges to phase φ2 with a high loop gain.

As described above, in the present embodiment, the loop gain of the loop filter 100 'is fixed,
With 0, the holdover is canceled when the phase of the phase comparison signal 8 approaches the new phase after switching.

In this manner, although the time until the completion of synchronization is longer than that of the second embodiment, G.
In addition to satisfying the recommendation 813, it is possible to follow changes in the characteristics of the PLL circuit well, so that substantially the same effects as in the second embodiment can be obtained.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. In FIG. 18, the same parts as those in FIG.
Here, only different portions will be described. In the clock switching device of the present embodiment, the holdover circuit 16 is omitted from the configuration of FIG. 6, and the output of the operational amplifier 12 in the loop filter 100 is directly supplied to the voltage controlled oscillator 17. Further, the reference clock 6 sent from the selection circuit 3 is supplied to the phase detection unit 300 via the tank circuit 92.

In the first and second embodiments, the voltage controlled oscillator 17
, The switching can be performed while avoiding the loss of the clock. In the present embodiment, the same effect is obtained by the output holding operation of the tank circuit 92.

For example, if it becomes necessary to switch clocks due to the disappearance of the propagation clock, the reference clock 6 from the selection circuit 3 will be interrupted before the switching is completed,
In this state, a sudden change in phase cannot be avoided. Therefore, in the present embodiment, the reference clock 6 from the selection circuit 3 is passed through the tank circuit 92, thereby preventing the reference clock from disappearing.

Here, it is assumed that the tank circuit 92 can maintain its output (reference clock 6 ') over a period longer than the time until the clock loss is detected by the signal loss detection units 4a and 4b. . Conversely, this can be easily realized by shortening the time required for detecting the clock input disconnection.

For example, by defining a clock loss based on the disappearance of four clocks (four pulses) of the propagation clock, it is possible to detect the clock loss by the disappearance of three to five clocks even if the uncertainty width is considered. . Q of tank circuit 92
You only need 100 at most.

The operation of the above configuration will be described. When the amplitude of the reference clock 1 is lost due to a failure in the signal cable or the like, the signal loss detection unit 4a detects the clock loss, switches the selection circuit 3, and switches to the reference clock 2.
Further, the on / off switch 15 is turned on, and the loop gain of the loop filter 100 is reduced.

When the failure occurs, the reference clock 6 from the selection circuit 3 disappears. However, since the oscillation component of the waveform of the original reference clock 6 is held by the tank circuit 92, the reference clock 6 is supplied to the phase detector 300. The reference clock 6 'is not lost. Then, before the reference clock 6 ′ from the tank circuit 92 disappears, the switched reference clock 6 is input via the selection circuit 3.

Here, there is no guarantee that the reference clocks 6 before and after the switching are synchronized with each other. Even if they are synchronized, it is more likely that their absolute phase relations are out of alignment. Therefore, after selecting a new reference clock 6, the PLL circuit starts a phase following operation toward the phase. When the reference clocks 6 before and after the switching are in an asynchronous relationship, the frequency / phase pull-in is started.

Next, when the phase of the switched reference clock 6 and the phase comparison signal 8 approach each other through the same processing as in the second embodiment, the loop gain of the loop filter 100 is returned to its original state ( The on / off switch 15 is turned off), and the clock output signal 24 converges on a new second phase.

FIG. 19 shows the above process on a time axis.
When a clock failure occurs at time t1 from the steady state,
At time t2, the controller 4 detects the failure. Here, the output of the tank circuit 92 does not disappear. Next, at time t3, the loop gain of the loop filter 100 is reduced, and at time t4, switching to a new reference clock is performed.

Eventually, at time t5, the reference clock 6 'from the tank circuit 92 disappears. At this point, since the reference clock switching has already been completed, the phase detector 300
There is no loss of the reference clock. In other words,
The output holding time of the tank circuit 92 is set longer than Δt.

The frequency / phase pull-in to the new reference clock has already started at time t4. Then, when the phase of the phase comparison signal 8 has a stationary phase relationship with the phase of the switched reference clock 6 (time t6), the gain of the loop filter 100 is restored.

When the above operation is considered in terms of the time change of the phase fluctuation, the PLL circuit is re-synchronized with the phase difference between the original reference clock and the new reference clock between times t4 and t6. . However, in this state, since the loop gain is low, although the absolute phase fluctuation is large, the temporal change is small. Because the gain of the loop filter 100 is reduced. When the loop gain is returned to the original value at t6, the amount of phase change with time increases, but the absolute phase change can be suppressed to a small amount because the phase difference itself is small.

As described above, in the present embodiment, the tank circuit 92 is provided instead of omitting the holdover circuit 16, and the clock is switched while avoiding the disappearance of the reference clock by the output holding operation of the tank circuit 92. By doing so, the same effects as those of the second embodiment can be obtained, and the configuration can be further simplified.

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the holdover circuit 16 may be configured by an analog element. In each of the above embodiments, the loop filter 100
As a method of controlling the loop gain of the above, a part of the feedback resistor connected in series is short-circuited by the on / off switch 15, but for those who are knowledgeable about the operational amplifier circuit, the same effect can be obtained by the following method. You can easily imagine what you can get.

A plurality of feedback resistors are combined in parallel, and some of the resistors are connected in series with the on / off switch, and when reducing the loop gain, the on / off switch is short-circuited.・ Change the value of the input resistance instead of the feedback resistance. -Change the resistance value not at one place but at multiple places.

Further, since it is sufficient to lower the loop gain, the following method can be considered. The operation resistance value is controlled by using a non-linear element such as a transistor or a diode on the feedback circuit side or the input side of the operational amplifier 12. -Insert an attenuation circuit in the middle of the circuit and change the attenuation rate. -Insert an amplifier circuit in the middle of the circuit to change the amplification factor. There are various ways to do this.

In the second embodiment, the PLL circuit becomes stable when the phase of the reference signal (signal 63) in the phase comparator 7 and the phase of the phase comparison signal 8 are shifted by exactly π. It was explained on the premise of this. However, the present invention is not limited to this, and the final synchronization phase relationship may be shifted due to the characteristics of the phase comparator 7 or when an offset of the operating point of the PLL circuit is artificially added. Such a shift is a matter determined by design, and a similar effect can be obtained by manipulating the position for detecting the edge to set the final synchronization position.

The effects obtained in the above embodiments are described in ITU Recommendation G. It can be said that this is not only a characteristic that satisfies 813 but also a desirable characteristic as a phase fluctuation characteristic of a general transmission device or a switching device.

In the fourth embodiment, the tank circuit 92 is provided to prevent the reference clock from disappearing. However, the tank circuit 92 may not be provided depending on the required specification level. In particular, the phase detector 300 or the loop filter 100 is
In the case of using an R (exclusive OR) circuit, by appropriately adjusting the characteristics of the loop filter 100,
Even if the reference clock disappears, it is possible to avoid detuning of the output.

In addition, various modifications can be made without departing from the gist of the present invention, such as the number of input reference clocks, the difference between positive logic and negative logic, and setting of timing for phase convergence.

[0118]

As described above in detail, according to the present invention, the switching control means is provided, the phase of the output clock is temporarily held, and the time constant required to follow the phase of the output clock to the reference clock is increased in the meantime. After switching the reference clock, and in the resynchronization process that follows, the above time constant is restored at the timing when the phase of the output clock approaches the phase of the reference clock after switching, so that the phase response characteristics It is possible to provide a clock switching device capable of suppressing the amount of phase fluctuation with respect to a time interval without sacrificing data.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a clock switching device according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the clock switching device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing in principle a state of a phase change of a clock output signal 24 in a clock switching process of the clock switching device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing experimental results of operating characteristics of the clock switching device according to the first embodiment of the present invention in a relationship between time and a relative phase.

FIG. 5 is a view showing experimental results of MRTIE characteristics of the clock switching device according to the first embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a configuration of a clock switching device according to a second embodiment of the present invention.

FIG. 7 is a first time chart illustrating a relationship between signals according to the second embodiment of the present invention.

FIG. 8 is a second time chart illustrating a relationship between signals according to the second embodiment of the present invention.

FIG. 9 is a third time chart illustrating a relationship between signals according to the second embodiment of the present invention.

FIG. 10 is a view principally showing a state of a phase change of a clock output signal 24 in a clock switching process of the clock switching device according to the second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a modification of the phase detection unit 300 of the clock switching device according to the second embodiment of the present invention.

FIG. 12 is a time chart illustrating a relationship between signals according to a modification of the phase detection unit 300 in the clock switching device according to the second embodiment of the present invention.

FIG. 13 is a diagram showing experimental results of operating characteristics of the clock switching device according to the second embodiment of the present invention in a relationship between time and a relative phase.

FIG. 14 is a view showing an experimental result of MRTIE characteristics of the clock switching device according to the second embodiment of the present invention.

FIG. 15 is a circuit block diagram showing a configuration of a clock switching device according to a third embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration example of a holdover circuit 16;

FIG. 17 shows how the phase of the clock output signal 24 changes in the clock switching process of the clock switching device according to the third embodiment of the present invention in comparison with the clock switching device according to the first embodiment of the present invention. FIG.

FIG. 18 is a circuit block diagram showing a configuration of a clock switching device according to a fourth embodiment of the present invention.

FIG. 19 is a view showing a process of an operation in a clock switching device according to a fourth embodiment of the present invention on a time axis.

FIG. 20 shows ITU-T recommendation G. FIG. 813
The figure which introduced URE12 and FIGURE13.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Reference clock of main system 2 ... Reference clock of sub system 3 ... Selection circuit 4 ... Control unit 4a ... Signal disconnection detection unit of reference clock of main system 4b ... Signal disconnection detection unit of reference clock of sub system 5 ... Clock selection Control signal 6 ... Reference clock 7 ... Phase comparator 8 ... Phase comparison signal 9,10 ... Resistor 11 ... Capacitor 12 ... Operational amplifier (op amp) 13,14 ... Op amp feedback resistor 15 ... On / off switch 16 ... Hold Over circuit 161 ... Analog / digital (A / D) converter 162 ... Latch circuit 163 ... Digital / analog (D / A) converter 17 ... Voltage controlled oscillator (VCXO) 18 ... Division circuit 19 ... Gain switching signal 20 ... Holdover control signal 21 Signal delay circuit 22 Delay signal 23 AND circuit 24 Clock output signal 41 42 Lock detection signal 100 ... Loop filter 200 ... Delay unit 60 ... Inverter 61 ... Inverter 61 output 62,64 ... Delay element 63 ... Delay element 62 output 65 ... Delay element 64 output 66 ... AND circuit 67 ... AND circuit 66 Outputs 68, 69 D flip-flop (D-FF) 70 Q / output of D-FF 68 (Q inverted output) 71 Q / output of D-FF 69 (Q inverted output) 72 NAND circuit 73 NAND circuit 72 74 RS flip-flop (RS-FF) I1-I6 inverter A1, A2 AND circuit NA1, NA2 NAND circuit 80-82 D flip-flop (D-FF) D63 signal delayed from signal 63 NOT63 ... Signals 300 and 300 ′ obtained by inverting signal 63,... Phase detector 100 ′... PLL circuit 91. Reference clock via the D circuits 92 ... tank circuit 6 '... tank circuit 92

Claims (11)

[Claims] 1. A clock selecting means for selecting one clock signal from a plurality of clock signals supplied via a communication network and switching and outputting the selected clock signal as a reference clock signal; Oscillating means for outputting an oscillating signal of a frequency; phase comparing means for detecting a phase difference between the reference clock signal and the oscillating signal; based on the phase difference detected by this means, A control signal generating means for generating a control signal to the oscillating means for converging to a phase of a clock signal; a control signal generating means capable of changing a time constant required for the convergence; and Holding means for selectively holding the oscillating means in a hold state; and After holding the oscillation means in the hold state through the hold means and keeping the state of the oscillation signal at that time, and in this state, causing the clock selection means to switch the reference clock signal, the oscillation means is held through the hold means. Switching control means for canceling the state, and changing the time constant of the control signal generation means from a state before holding to a large value during a hold state of the oscillation means to a large value, and a predetermined period after canceling the hold state. And a time constant control means for returning the time constant of the control signal generation means to the value before the hold when the time has elapsed. 2. The time constant control means according to claim 1, wherein after the oscillation means is released from the hold state, the phase difference between the new reference clock signal after switching of the clock selection means and the oscillation signal becomes larger than a predetermined value. 2. The clock switching device according to claim 1, wherein a time constant of said control signal generation means is returned to a value before said hold when said value becomes smaller. 3. A clock selecting means for selecting one clock signal from a plurality of clock signals supplied via a communication network and switching and outputting the selected clock signal as a reference clock signal; Oscillating means for outputting an oscillating signal of a frequency; phase comparing means for detecting a phase difference between the reference clock signal and the oscillating signal; based on the phase difference detected by this means, Control signal generating means for generating a control signal to the oscillating means for converging to a phase of a clock signal; and holding means for selectively holding the oscillating means by holding the control signal generated by the means. Holding the oscillating means through the oscillating holding means when it becomes necessary to switch the reference clock signal by the clock selecting means. State, the state of the oscillating signal at that time is maintained, and in this state, the clock selecting means switches the reference clock signal. Then, a new reference clock signal after the clock switching of the clock selecting means and the oscillation 2. The clock switching device according to claim 1, further comprising: a switching control unit that releases the hold state of the oscillation unit through the hold unit when the phase difference from the signal becomes smaller than a predetermined value. apparatus. 4. A clock selecting means for selecting one clock signal from a plurality of clock signals supplied via a communication network and switching and outputting the selected clock signal as a reference clock signal; and a reference transmitted from the clock selecting means. A clock signal is supplied, and when the supplied reference clock signal is lost, a reference clock signal holding means for outputting the waveform before the loss while holding the waveform before the loss with a predetermined relaxation time, and according to the level of the applied control signal. Oscillating means for outputting an oscillating signal having a frequency which has been adjusted, phase comparing means for detecting a phase difference between the reference clock signal and the oscillating signal, and, based on the phase difference detected by this means, A control signal for generating a control signal to the oscillating means for converging to a phase of a reference clock signal; Generating means; switching control means for causing the clock selecting means to switch the reference clock signal when it becomes necessary to switch the reference clock signal by the clock selecting means; and a reference clock of the clock selecting means by this means. At the same time as the signal switching, the time constant of the control signal generating means is changed to a value larger than the state before the switching, and the phase difference between the reference clock signal sent from the clock signal holding means and the oscillation signal is predetermined. A clock switching device comprising: a time constant control unit that returns the time constant of the control signal generation unit to the value before the switching when the value becomes smaller than the value. 5. The switching control means monitors each of the plurality of reference clock signals, and, when a failure occurs in the reference clock signal selected by the clock selection means, only for a predetermined period. A drive signal is sent to the hold unit to set the oscillation unit in a hold state, and in the meantime, the clock selection unit switches the reference clock signal. The time constant control unit is output from the switch control unit. The drive signal is delayed by a predetermined time and used as a time constant switching signal for switching the time constant of the control signal generating means. The control signal generating means switches the time constant generated by the time constant controlling means. 2. The clock switching device according to claim 1, wherein the number of connected time constant elements is switched according to a signal. 6. The holding means changes a driving signal applied from the control signal generating means to the oscillating means in a driving state when the applied driving signal is in a driving state at a first level and in a stopped state at a second level. Holding, the switching control means usually sets the drive signal to a first level, monitors each of the plurality of reference clock signals,
When a failure occurs in the selected clock signal, the drive signal is set to the second level for a predetermined period, and the clock selection means switches the clock signal during the second level of the drive signal. The time constant control means performs the following based on a drive signal output from the switching control means, a reference clock signal provided from the clock selection means, and an oscillation signal output from the oscillation means. Generating an on / off control signal that can take a value level, and guiding the on / off control signal to the control signal generating means, wherein the control signal generating means includes a plurality of time constants connected in series; An on / off switch that is turned on when the on / off control signal is at a first level and short-circuits at least one of the plurality of time constant elements. A time constant control means for inverting a reference clock signal output from the clock selection means, a first delay circuit for delaying an output of the inversion circuit by a predetermined first delay time, A second delay circuit that further delays the output of the first delay circuit by a predetermined second delay time, and an AND circuit that outputs a logical product of the output of the first delay circuit and the oscillation signal A first holding circuit that holds the output of the AND circuit at the rising or falling timing of the reference clock signal output from the clock selecting means, and an output of the AND circuit that is output from the second delay circuit. A second holding circuit for holding at the rising or falling timing of
And a NAND circuit that outputs a NAND of an inverted output or a non-inverted output of the second holding circuit and the drive signal, an input of the drive signal to a set terminal, and an output of the NAND circuit to the reset terminal. 2. The clock switching device according to claim 1, further comprising a NOR latch circuit that supplies a normal output signal or an inverted output signal to the on / off switch as an on / off control signal. 7. The holding means changes a value of a control signal given from the control signal generating means to the oscillating means when the applied driving signal is in a driving state at a first level and in a stopped state at a second level. Holding, the switching control means usually sets the drive signal to a second level, monitors each of the plurality of reference clock signals,
When a failure occurs in the selected clock signal, the drive signal is set to the first level for a predetermined period, and the clock selection means switches the clock signal during the continuation of the first level of the drive signal. The time constant control means performs the following based on a drive signal output from the switching control means, a reference clock signal provided from the clock selection means, and an oscillation signal output from the oscillation means. Generating an on / off control signal that can take a value level, and guiding the on / off control signal to the control signal generating means, wherein the control signal generating means includes a plurality of time constants connected in series; And an on / off switch that is turned on when the on / off control signal is at a first level and short-circuits at least one of the plurality of time constant elements. The time constant control means includes a delay circuit for delaying the reference clock signal output from the clock selection means, a first inversion circuit for inverting the output of the delay circuit, and an output of the delay circuit and the oscillation signal. A first AND circuit that outputs a logical product, a second AND circuit that outputs a logical product of an output of the delay circuit and an output of the first inverting circuit, and an output of the first inverting circuit. A delay inverting circuit for inverting and delaying, a first holding circuit for latching an output of the first AND circuit at a rising or falling timing of the delay inverting circuit, and a reference clock for outputting an output of the second AND circuit; A second holding circuit for latching at a rising or falling timing of a signal; an inverted output or non-inverted output of the first holding circuit; and a non-inverted output or inverted output of the second holding circuit. A NAND circuit that outputs a NAND of the inverted output and the drive signal, a second inverting circuit that inverts the output of the NAND circuit, and an output of the second inverting circuit that is input to a clock terminal. And a third holding circuit that receives the drive signal at a terminal and supplies a normal output signal or an inverted output signal to the on / off switch as the on / off control signal. Item 2. The clock switching device according to Item 1. 8. The holding means changes a value of a control signal given from the control signal generating means to the oscillating means in a driving state when a given driving signal is in a driving state at a first level and in a stopped state at a second level. Holding, the switching control means usually sets the drive signal to a second level, monitors each of the plurality of reference clock signals,
When a failure occurs in the selected clock signal, the drive signal is set to the first level for a predetermined period, and the clock selection means switches the clock signal during the continuation of the first level of the drive signal. To generate an on / off control signal based on the drive signal, the reference clock signal provided from the clock selection means, and the oscillation signal output from the voltage controlled oscillator. An off circuit for inverting a reference clock signal output from the clock selecting means, and an output of the inverting circuit being a first predetermined signal. A first delay circuit that delays by a delay time, a second delay circuit that further delays the output of the first delay circuit by a predetermined second delay time, A first AND circuit that outputs a logical product of the output of the first delay circuit and the oscillation signal; and the output of the first AND circuit is connected to the rising or falling edge of a reference clock signal output from the clock selection means. A first holding circuit that latches at the falling timing, a second holding circuit that latches the output of the AND circuit at the rising or falling timing of the output of the second delay circuit,
A second AND circuit to which inverted output or non-inverted output of the first and second holding circuits and the drive signal are provided, and a logical product of both signals is provided to the holding means as the on / off control signal; The clock switching device according to claim 3, further comprising: 9. The switching control unit monitors each of the plurality of reference clock signals, and when a failure occurs in the clock signal selected by the clock selection unit,
A drive signal for changing the time constant of the control signal generation means is changed from the first level to the second level for a predetermined period, and the clock signal is supplied to the clock selection means during the continuation of the second level of the drive signal. And an on / off control signal is generated based on the drive signal, a reference clock signal provided via the reference clock signal holding means, and an oscillation signal output from the oscillation means. The on / off control signal is led to the control signal generating means, wherein the control signal generating means includes a plurality of time constant elements connected in series, and when the on / off control signal is at a first level. An on / off switch that is turned on to short-circuit at least one of the plurality of time constant elements, wherein the switching control means is provided via the reference clock signal holding means. An inverting circuit for inverting the reference clock signal, a first delay circuit for delaying the output of the inverting circuit by a predetermined first delay time, and an output of the first delay circuit for a predetermined time. A second delay circuit for further delaying by a delay time of 2; an AND circuit for outputting a logical product of an output of the first delay circuit and the oscillation signal;
A first holding circuit for latching the output of the D circuit at the rising or falling timing of the reference clock signal output from the clock selecting means; and the rising or falling of the output of the second delay circuit for the output of the AND circuit. A second holding circuit that latches at a falling timing, a NAND circuit that outputs a NAND of an inverted output or a non-inverted output of the first and second holding circuits, and the drive signal, and a drive signal connected to a set terminal. And a NOR latch circuit to which an output of the NAND circuit is input to a reset terminal and which supplies a normal output signal or an inverted output signal to the on / off switch as the on / off control signal. The clock switching device according to claim 4. 10. The clock switching device according to claim 1, wherein the oscillating unit includes a frequency dividing circuit that divides an oscillation signal output from a variable frequency oscillator. 11. An analog / digital converter for converting a value of a control signal output from the control signal generating means into digital data, and a latch circuit for latching the digital data according to the drive signal. 9. The clock switching device according to claim 1, further comprising: a digital / analog converter that converts an output of the latch circuit into an analog signal and supplies the analog signal to the oscillation unit.