JP2000029703A - Dsp architecture optimized for memory access - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a super-scalar processor which has maximum efficiency for the execution of a loop, including a memory access instruction. SOLUTION: A processor includes at least one memory access unit (MENU) 10 which provides a readout or write-in address for the address bus of a memory 16 as a readout or write-in instruction is executed, a computing and logic unit(ALU) 12, which operates in parallel to the memory access unit and is arranged at least to provide data for the data bus of the memory while the memory access unit provides a write address, and a stored address quene (STAQ) in which respective write addresses provided by the memory access unit waiting until the availability of the data is written are stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (DSP), and more particularly to a memory latency (laten).
cy).

[0002]

FIG. 1 schematically illustrates a portion of a conventional DSP architecture. The DSP includes four processing units operating in parallel. Two of these units are memory access units (MEMU) 10.
Further, a calculation and logic unit (ALU) 12 and a branch unit (BRU) 14 are provided. Each of the MEMU units engages the memory 16 via an independent bus.

[0003] The branch unit BRU receives from a non-represented instruction memory a compound instruction INST, which may include four element instructions to be provided in each unit in parallel. The unit BRU searches for the instruction that means,
3 surviving instructions I1, I to ALU and MEMU units
2 and I3 are distributed in parallel.

[0004] Each of the ALU and MEMU units typically includes an instruction queue 18 in the form of a FIFO in which instructions are weighted before the instructions are processed by the corresponding unit.

A DSP of the type shown in FIG. 1 is of the type X [i]
Optimized to perform OP Y [j] vector operations. i and j usually change in a loop, and O
P indicates any operation to be performed by the computation unit 12. In fact, the operand X [i]
And Y [j] can be fetched together into memory 16 via the two buses and are processed by ALU 12 in the same cycle in theory.

[0006]

In practice, a conventional SRAM
A problem arises because of the structure of the currently used memory. Although memory access can be performed in each cycle, reading data from a conventional SRAM typically has a latency of two cycles. In effect, in executing the read instruction, the address is provided to the memory.
An additional cycle is required to provide the memory with the read access signal, and the last cycle is required for the memory providing data on its data bus.

To illustrate the resulting problem, the common loop, which is a function of which is incremented by certain successive values stored in memory, is discussed below as an example. This loop can be described directly as follows:

LD: R1 = [i] (1) OP: R1 = R1 + R2 ST: [i] = R1 BR: test i, i ++, loop

This loop is clearly one MEMU
Use a unit. It loads the value stored in memory at address i into register R1 (LD), increments the contents of register R1 by the value contained in register R2 (OP), and stores the new contents of register R1 at address 1. Store (ST) and finally increment and test (BR) the address i to start the loop again.
When the branch unit BRU detects that the address i has reached a predetermined value, the process exits the loop. DSP
Is usually a non-BR type instruction. The loop is a unit BRU that independently executes tests, increments and branches
, By first setting a register provided for this purpose.

The register R1 is a working register of the ALU, and the address i is stored in the register of the branch unit BRU. Operations LD and ST are operations to be performed by one of the units MEMU, operation OP is to be performed by the unit ALU, and operation BR is a unit BRU
Should be done by Operations LD and O
P is the unit MEMU and AL in the same compound instruction
Provided in parallel to U, while operations ST and B
R is the unit MEMU and B in the second compound instruction
Provided parallel to the RU.

In practice, some compound instructions contain fields that are provided to several units at a time. For example,
The load instruction LD, meaning unit MEMU, also includes a field, meaning unit ALU, to prepare one of its registers (R1) to receive the data provided by the memory. At the same time, store instruction ST
Contains a field which means unit ALU for selecting a register, the contents of which are provided on the memory bus. Therefore, as shown in FIG.
F of each of the instructions I2 and I3 provided to
Are provided in parallel with the normal instruction I1 to the instruction queue 18 of the unit ALU, and the unit ALU can execute the normal instruction and the operation indicated by the field f in one cycle.

The following table describes the operations performed by one memory access unit MEMU and by the calculation unit ALU for some iterations of the loop. The branch instructions BR do not cause any problems and the table does not explicitly explain them.

Each column of the table corresponds to an instruction cycle,
Each operation marked in the table is assigned a number corresponding to the loop iteration.

[0014]

[Table 1]

In the first cycle, the unit MEM
U and ALU are the first instructions LD and OP (LD1, O
P1) is received. The unit MEMU immediately executes the instruction L
Execute D1 to start a read cycle of the value stored in the memory at address i. The instruction LD1 is deleted from the instruction queue of the unit MEMU. The instruction OP1 requiring the value fetched by the instruction LD1 cannot be executed yet. This instruction OP1 waits in the instruction queue of the unit ALU.

In the second cycle, the unit MEM
U receives the first command ST (ST1). The instruction ST1 requiring the result of the operation OP1 cannot be executed yet, and waits in the instruction queue of the unit MEMU. Instruction OP1 waits in the queue of unit ALU so that the memory does not return the operands it requires.

In the third cycle, the unit MEM
U and ALU receive commands LD2 and OP2. These instructions are placed in the queue after the instructions ST1 and OP1 that have not yet been executed. The memory finally returns the operands required by instruction OP1. Therefore, the instruction OP1 is executed and is deleted from the instruction queue.

In cycle 4, the unit MEMU
Receives the command ST2. The instruction ST2 is an instruction LD2
After to wait in the queue of the unit MEMU. The result is available because instruction OP1 was executed in the previous cycle. Therefore, the instruction ST1 is executed and deleted from the queue. Although there is only one instruction OP2 in the queue of the unit ALU, the instruction LD2
This instruction cannot yet be executed because it requires an operand to be fetched by the execution of.

In cycle 5, units MEMU and ALU receive instructions LD3 and OP3. Instruction L
D2 is executed and removed from the queue.

Instruction OP2 must still wait in the queue to require an operand to return two cycles delayed by the memory in response to instruction LD2.

From the fifth cycle, execution of the instructions of the second iteration of the loop proceeds as long as the first iteration starting in cycle 1 is performed.

As represented by the table, the processor can perform one memory access each cycle, but it only performs memory accesses in two out of four cycles. That is, the loop execution efficiency is only 50%.

Further, at each new iteration of the loop, the instruction queue of unit MEMU is filled with additional instructions and overflows and ends. To avoid overflow, instruction provision must be stopped regularly to allow the queue to be emptied. This consideration reduces efficiency.

In fact, its straight form of loop programming is not at all optimal due to memory latencies.

In order to improve the efficiency, what is called a loop unrolling technique is often used in consideration of memory latency. This technique consists of programming a macro loop, each iteration of which usually corresponds to several iterations of the loop. Therefore, the previous loop (1) is written as follows.

Lda: R1 = [i] (2) Opa: R1 = R1 + R2 Ldb: R3 = [i + 1] Opb: R3 = R3 + R2 Sta: [i] = R1 Stb: [i + 1] = R3 BR: test i, i = + 2, loop

In this loop, the value contained in the address i is loaded into the register R1 (LDa), and the contents of the register R2 are incremented by the contents of the register R1 (O
Pa), the value contained in the address i + 1 is loaded into the register R3 (LDb), the content of the register R3 is incremented by the value contained in the register R2 (OPb), and the register R
1 is stored at address i (STa), and the content of register R3 is stored at address i + 1 (STa).
b) The variable i is incremented by 2 to restart the loop.

This loop is programmed with four compound instructions. The first instruction is formed from operations LDa and OPa and the second instruction is LDb and OPb
And the third instruction is formed from STa and the fourth
Are formed from STb and BR. The following table shows
A sequence of operations for several loop iterations will be described.

[0029]

[Table 2]

In the first cycle, the unit MEM
U and ALU are the first instructions LDa and OPa (LDa
1, OPa1) is received. The instruction LDa1 is executed immediately and is deleted from the queue.

In the second cycle, the unit MEM
U and ALU receive commands LDb1 and OPb1. The instruction LDb1 is executed immediately and is deleted from the queue. The instructions OPa1 and OPb1 are stored in the memory as the instruction LD.
must be returned according to a1 and LDb1,
It remains in the queue of the unit ALU waiting for the corresponding operand.

In the third cycle, the unit MEM
U receives the command STa1. The memory is queried by instruction LDa1 and returns the operands required by instruction OPa1. Therefore, the instruction OPa1 is executed and deleted from the queue.

In the fourth cycle, the unit MEM
U receives the command STb1. The memory stores the instruction LDb1
And returns the operands required by instruction OPb1. Therefore, the instruction OPb1 can be executed.

In the fifth cycle, the unit MEM
U and ALU receive commands LDa2 and OPa2. The value it needs is the instruction OPa in the previous two cycles.
The instruction STa1 can be executed because it has been calculated by 1.

In the sixth cycle, the unit MEM
U and ALU receive commands LDb2 and OPb2. The value required by the instruction OPb in the previous two cycles
The instruction STb1 can be executed because it is calculated by 1.

In the seventh cycle, the unit MEM
U receives the command STa2. A new iteration of the loop is started by execution of instruction LDa2.

The table reveals that the processor performs four memory accesses every six cycles, for a total of 66% efficiency and 33% gain over the above solution.

However, it is clear that the queue of the unit MEMU is willingly full, requiring the provision of instructions to be stopped regularly. Instead of filling all four cycles with two instructions, as in the previous solution, it fills all six cycles with two instructions.

While the loop unrolling technique substantially improves efficiency, it is not an optimal solution for superscalar processors. In fact, it works even better in superscalar.

An object of the present invention is to provide a superscalar processor having the highest efficiency for executing a loop including a memory access instruction.

[0041]

SUMMARY OF THE INVENTION This and other objects are at least one memory access unit for providing a read or write address to an address bus of a memory in response to execution of a read or write instruction, and the memory access unit. This is accomplished using a processor that operates in parallel with the unit and includes a computation and logic unit that is at least arranged to provide data to the data bus of the memory while the memory access unit provides the write address. The processor includes a write address queue in which each write address provided by a memory access unit that waits until data availability is written is stored therein.

According to one embodiment of the present invention, the computation and logic unit includes two independent instruction queues for receiving instructions awaiting execution, the first instruction queue comprising a logic and a computational queue. For receiving instructions, wherein the second instruction queue is for receiving instruction fields provided to the memory access unit to identify registers of computation and logical units involved in a read or write operation. belongs to.

According to one embodiment of the present invention, the computation and logic unit comprises:
A write data queue includes a store data queue that waits for the presence of a write address therein.

According to one embodiment of the invention, the computation and logic unit includes a load data queue into which each data from the memory is written, the computation and logic unit comprising: Wait until available.

According to one embodiment of the invention, the processor includes a branch unit for receiving the instructions and distributing the instructions in parallel between its own memory access unit and the computation and logic units.

According to one embodiment of the present invention, each of the units includes a store data queue in which each data to be written to memory waits until a write address in the write address queue exists.

According to one embodiment of the present invention, each of the units includes a load data queue into which each data is to be written from memory for the unit and waits until the unit is available.

[0048]

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing objects, features and advantages of the present invention will be described in detail in the following non-limiting description of specific embodiments with reference to the accompanying drawings.

In FIG. 2, the processor according to the invention comprises, as in FIG. 1, two memory access units 10 (MEMU) all coupled to a branch unit 14 and one logic and computation unit (ALU). Units 10 and 12 include an instruction queue in which instructions waiting for execution by branch unit BRU are stacked.

In accordance with the present invention, each memory access unit MEMU includes a store address queue STAQ from which the addresses used for write access to memory 16 are provided. The read address is provided to conventional memory 16, as represented by the dashed line across queue STAQ.

The unit ALU further includes a store data queue STDQ and a load data queue LDDQ through which data exchanged with the memory passes. As a practical matter, all units of the processor exchange data with memory as before, and thus include the queues STDQ and LDDQ as shown. Queue STA
Q, STDQ and LDDQ are all of FIFO type.

Each time the unit MEMU executes a store instruction, the write address is stacked in the corresponding queue STAQ. The data written by this instruction is normally stacked in the corresponding store data queue STDQ of the unit ALU. For example, unit AL
If the contents of U's register R1 are to be written to address i, a unit MEMU executing the write instruction
Stacks the address i of the queue STAQ, and at the same time, the unit ALU stacks the contents of the register R1 of the queue STDQ. It should be noted that the data to be written does not need to be stacked on the queue STDQ, while the addresses are stacked on the queue STAQ. This is an essential aspect of the present invention.

In each cycle, the contents of queues STDQ and STAQ are polled. If the queue STAQ contains one address and one of the queues STDQ contains data, the data is written to the address contained in the queue STAQ, so that the queues STDQ and STAQ are updated. If these conditions are not met, ie if the queue STAQ is empty or if the queues STDQ are all empty, no writing is performed. Two queues ST
The situation where the DQ contains data at the same time never occurs.

In the case of a DSP containing two memory access units MEMU, each location of the queue STDQ contains two data words, one for each of the units MEMU. Thus, for a write to take place, the data word contained at the position of the queue STDQ will also have a unit M with a nonempty queue STAQ.
EMU must be supported.

This mechanism makes it possible to execute a write command immediately without taking into account the utilization of the memory bus or the data to be written. Data to be written is written continuously, and all data and memory buses are immediately available. This mechanism will now be described in detail using an example.

Considering again the example of loop (1), it is programmed into a straight form as follows.

LD: R1 = [i] (1) OP: R1 = R1 + R2 ST: [i] = R1 BR: test i, i ++, loop

As described above, the load instruction LD or the store instruction ST is formed of two fields, one field for the unit MEMU is for indicating a read or write address, and the other field for the unit ALU. Is for indicating the register to receive the read data or its contents to be written. Therefore, the instruction LD is, as described above, within the ALU instruction, the first of the load queue LDDQ.
LDA: R1 = LDDQ, which is a MEMU instruction for loading the elements of
LD for providing address i in read mode
M: Decomposed into R (i).

The above-mentioned store instruction ST is for stacking the contents of the register R1 in the store queue STDQ in the ALU instruction, and is a MEMU instruction, STA: S
TDQ = R1 and STM: STAQ = i for stacking the write address in the address queue STAQ
And decompose into

According to the present invention, the field f of the read / write command for the unit ALU is (command OP)
The normal instruction I1 for the unit ALU (as in) is stacked in a separate instruction queue 19 of the queue 18 by which it is received.

The following table shows, for some iterations of loop (1), the units MEMU and ALU
And the contents of the instruction queues of units MEMU and ALU, unit ME
The contents of the MU queue STAQ, and finally the unit AL
The contents of the queues STDQ and LDDQ of U will be described.
In that table, operations are assigned numbers corresponding to the iterations.

[0062]

[Table 3]

In the first cycle, the unit MEM
U and ALU receive commands LD1 and OP1. The instruction LD1 is the instruction LDM provided to the unit MEMU.
1 and the instruction LDA1 provided to the unit ALU. Instruction LDM for instructing transmission of read address
1 is executed immediately. Read queue LD that is empty
To require the value from DQ, instruction LDA1 is set to wait. Instruction OP requiring this same value
1 is also set to the weight.

In the second cycle, the unit MEM
U receives the instruction ST1 that has been decomposed into the instruction STM1 provided to the unit MEMU and the instruction STA1 provided to the unit ALU. The instruction STM1 is executed and is stacked on the queue STAQ at the address i where the result of the operation OP1 is written. Instruction STA1 is set to wait after instruction LDA1.

In the third cycle, the unit MEM
U and ALU receive commands LD2 (LDM2, LDA2) and OP2. The memory provides a queue LDDQ with the value [i] required by the instruction LDM1. Instruction LDA1 is executed, causing value [i] to be transferred from queue LDDQ to register R1. Instruction OP1 is executed and updates the contents of register R1. Unit ME
The MU has been released and the instruction LDM2 is also executed.

In the fourth cycle, the unit MEM
U receives the command ST2 (STM2, STA2). Instructions STM2 and STA1 are executed. Instruction STA1
Copies the contents of R1 ₁ of the register to the queue STDQ R1. The instruction STM2 is stacked on the queue STAQ at the address i + 1 where the result of the operation OP2 is written. In the same cycle, queue STAQ is detected to contain an address i, queue STDQ unit ALU is detected to contain data R1 _1. For memory bus is available, the data R1 ₁ is immediately written in the address i, the queue STAQ and STDQ are updated.

In the fifth cycle, the operations of the third cycle are repeated for a new loop iteration.

The above table illustrates that the memory unit MEMU executes an access instruction for each cycle. Therefore, efficiency is maximized. Further, the instruction queue does not fill. It does not require regular stopping of instruction serving to avoid queue overflow.

The queues STDQ and LDDQ represent receiving at most one element in this example. Thus, these queues can be simply registers, which are usually provided in conventional units for latching input and output data.

In other cases for more complex loops, it is clear that the queues STDQ and LDDQ receive one or more elements. At that time, the queue STD
The number of Q and LDDQ locations is incremented to avoid any risk of overflow.

Of course, the present invention is capable of various alterations, modifications and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and equivalents thereof.

[Brief description of the drawings]

FIG. 1 is a conventional DSP architecture.

FIG. 2 is a DSP architecture according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 memory access unit, MEMU 12 calculation and logical unit, ALU 14 branch unit, BRU 16 memory 18 first instruction queue 19 second instruction queue

Claims (7)

[Claims] At least one memory access unit (MEMU) for providing a read or write address to an address bus of a memory (16) in response to execution of a read or write instruction, and operating in parallel with the memory access unit. , A computation and logic unit (AL) arranged at least to provide data to a data bus of the memory while the memory access unit provides a write address.
U) and a write address queue (STAQ) in which each write address provided by the memory access unit that waits until data availability is written is stored therein. 2. The computing and logical unit (ALU)
Includes two independent instruction queues (18, 19) for receiving instructions awaiting execution, the first instruction queue (18) for receiving logical and computational instructions. , The second instruction queue (19) may include an instruction field (f) provided to the memory access unit (MEMU) to identify registers of the computation and logical unit (ALU) included in a read or write operation. 2. The processor according to claim 1, wherein the processor is adapted to receive). 3. The computing and logical unit (ALU)
Wherein each data to be written into the memory (16) includes a store data queue (STDQ) that waits until a write address is present in the write address queue (STAQ). The processor according to claim 1. 4. The computing and logical unit (ALU)
Is the memory (1) for the computation and logical units.
4. A processor according to claim 1 or 3, wherein each data from 6) includes a load data queue (LDDQ) into which is written and waits until the computation and logic unit is available. 5. A method for receiving instructions and including a branch unit (BRU) for distributing the instructions in parallel between the memory access unit (MEMU) and the computation and logic unit (ALU) itself. The processor of claim 1, wherein: 6. Each of the units includes a store data queue (STDQ) in which each data to be written to the memory waits until a write address of the write address queue (STAQ) exists. The processor according to claim 5, wherein 7. Each of said units includes a load data queue (LDDQ) into which each data is to be written from said memory for said unit, and waits until said unit is available. Item 7. The processor according to item 5 or 6.