JP2000029435A - Driving circuit of display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of a driving circuit of LCD(liquid crystal display). SOLUTION: The circuit has adding circuits 121, 122 and 123 which generate reference voltage data CDR, CDG and CDB by adding bright data BD and subbright data SBR, SBG and SBB, and selectors 111, 112 and 113 which switch and output the reference voltage data CDR, CDG and CDB instead of digital data DR, DG and DB by a timing control signal Tc during a blanking period only. Thus, direct current components are controlled by clamping the reference voltage level, which is controlled in accordance with the bright level and the subbright level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (L).
The present invention relates to a drive circuit for a CD (Liquid Crystal Display), and more particularly to a drive circuit that performs brightness adjustment and sub-brightness adjustment with a simple circuit configuration.

[0002]

2. Description of the Related Art An LCD is constructed by sealing liquid crystal between electrode substrates having transparent electrodes formed on a transparent substrate. Since the liquid crystal has electro-optical anisotropy, by applying a desired voltage between the electrodes to form an electric field in the liquid crystal, the liquid crystal exhibits optical characteristics according to the electric field intensity. By utilizing this property and applying a different voltage to each pixel, a display image is created as an aggregate of pixels exhibiting a desired luminance. As described above, the LCD has a display image created by voltage control, has advantages such as small size, thin shape, and low power consumption, and has been put to practical use in fields such as OA equipment and AV equipment.

FIG. 5 is a configuration diagram of such an LCD module. (1) is a signal processing circuit for performing brightness control, contrast control, γ correction, and the like of the input R, G, and B digital data VD, and (2) is a digital digital signal output from the signal processing circuit (1). A D / A converter for converting data VD into an analog signal,
(3) is R output from the D / A converter (2),
An RGB driver for switching and controlling the inversion / non-inversion amplification of the G and B analog video signals, and (4) an LCD.

FIG. 6 is a configuration diagram of a bright control circuit in the signal processing circuit (1). Adder circuit (15)
Are supplied with R, G, B digital data VD and bright data BD, and are added. Here, the bright data BD is, for example, 8-bit data created according to an adjustment knob or key input from the outside. The digital data VD is, for example, 8 bits, and the bright data BD is
The digital data VD is added to, for example, the third bit or less, corrected to 10-bit digital data, and output. The bright control circuit has the same configuration for each of R, G, and B.

Although illustration is omitted in the RGB driver (3), if there is a variation between the R, G, and B series, the hue changes. It is provided and can be adjusted for each IC.

[0006]

As described above, when fine brightness control is performed, the number of bits of correction data output from the brightness control circuit is larger than that of input data. Therefore, the D / A converter (2)
And the cost increases. Also, if the number of bits is reduced in order to avoid an increase in cost, the image quality deteriorates.

[0007] The sub-bright adjustment terminal is composed of an external variable resistor or the like. However, miniaturization of the package has been hindered and manufacturing costs have been increased.

It is also possible to use a built-in D / A converter as a variable resistor and control it by a microcomputer. However, a D / A converter is required for each of R, G, and B. Still, an increase in circuit scale is inevitable.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and a drive circuit of a display device in which a plurality of display elements are arranged has a function of controlling a brightness within a blanking period of an input video signal. A reference voltage control circuit that controls a reference voltage level based on a signal and a sub-bright control signal, a clamp circuit that clamps a reference voltage level of a signal output from the reference voltage control circuit, and a signal that is output from the clamp circuit. And an amplifying circuit for amplifying.

As described above, since the DC component of the voltage signal is controlled by clamping the reference voltage level controlled according to the bright level and the sub-bright level, the brightness control and the brightness control can be performed without increasing the circuit scale. Sub-bright control can be performed.

[0011]

FIG. 1 is a configuration diagram of a reference voltage control circuit according to an embodiment of the present invention. This reference voltage control circuit is provided in the signal processing circuit (1) in place of the bright control circuit of FIG.
The first to third selectors (1
11, 112, 113) and first to third adders (121, 122, 123). Bright data BD is added to each of the adding circuits (121, 122, 123).
And the sub-bright data SBR, SBG, and SBB are input and added. Here, the bright data BD
Are common to R, G, and B, and the sub-bright data SBR, SBG, and SBB are data that match the characteristics of each of the R, G, and B streams, and are controlled by software.
Alternatively, it is set to a predetermined value. These bright data BD and each of the sub-bright data SBR, SBG, SB
Each of the addition results with B is used as reference voltage data CDR, C for controlling both the bright level and the sub-bright level.
Each selector (111, 112, 1) is used as DG and CDB.
13) is input to one side. Selector (111, 11
2, 113) are supplied with video digital data DR, DG, DB of R, G, B, and digital data DR, D in response to a timing control signal Tc.
G, DB data and reference voltage data CDR, CDG, CD
B is output. More specifically, the digital data DR, DG, and DB data are output during the valid display period of the digital data DR, DG, and DB data, and the reference voltage data CDR, CDG, and CDB are provided during the blanking period.
Is output.

FIG. 2 shows an RG according to an embodiment of the present invention.
It is a detailed block diagram of a B driver (3). Inverting amplifier circuit (31), non-inverting amplifier circuit (32), selector (3
3), a capacitor (34) and a clamp circuit (35). R sent from the D / A converter (2),
The G and B analog video signals are supplied to the clamp circuit (35) after the DC component is removed by the capacitor (34). In the clamp circuit (35), the DC component is reproduced by clamping the reference voltage level of the analog video signal according to the clamp pulse CLP that is turned on during the blanking period of the analog video signal. The analog video signal thus DC-reproduced is supplied to an inverting amplifier circuit (31).
To be inverted and amplified, and sent to a non-inverting amplifier circuit (32) to be non-inverted and amplified.

The inverted amplified signal and the non-inverted amplified signal are sent to a selector (33), and a polarity inversion pulse FRP
, And is sent to the LCD (4) as an image signal whose polarity is inverted.

FIGS. 3 and 4 are signal waveform diagrams according to the present invention. 3 (a) and 4 (a) are timing control signals Tc, FIGS. 3 (b) and 4 (b) are clamp pulses CLP, and FIGS. 3 (c) and 4 (c) are FIGS.
3 (d) and 4 (d) are analog video signals obtained by A / D-converting the output from the reference voltage control circuit of FIG. 3A, and FIG. 3 (e) and FIG. e) is a polarity inversion pulse FRP, and FIGS. 3F and 4F are image signals finally output from the RGB driver (3) and sent to the LCD (4). FIGS. 3 and 4 illustrate a feature of the present invention that the reference voltage level V
cl is different.

An embodiment of the present invention will be described with reference to FIGS. In the reference voltage control circuit of FIG. 1, digital video data controlled to a reference voltage level corresponding to a bright level and a sub-bright level is D / A.
3 (c) or 4 (c) in the converter (2)
Is converted into an analog video signal having an amplitude of 0.75 V, for example. The reference voltage level of this analog video signal is clamped to, for example, 2 V in a clamp circuit (35) in the RGB driver (3) as shown in FIG. 3D or 4D. The analog video signal is further processed by an inverting amplifier circuit (31) and a non-inverting amplifier circuit (32) around, for example, 6 V and
Inversion amplification and non-inversion amplification are performed so that V becomes 4V.
The inverted amplified signal and the non-inverted amplified signal are selectively switched according to the polarity inversion pulse FRP shown in FIG. 3 (e) or FIG. 4 (e), and as shown in FIG. 3 (f) or FIG. An image signal whose polarity has been switched is obtained. Here, in FIGS. 3 and 4, the first half (left side in the figure) is a non-inversion period, and the second half (right side in the figure) is an inversion period.

When FIG. 3C is compared with FIG. 4C, the relative voltage with respect to the signal amplitude of the reference voltage level Vcl is different. That is, the reference voltage level Vc in FIG.
l, L are low, and the reference voltage level Vcl, H in FIG.
Is high. In the reference voltage circuit of FIG. 1, the height is determined according to the bright level and the sub-bright level. However, when the bright level or the sub-bright level is high, the reference voltage level Vcl, L is low. ,
When the bright level or the sub-bright level is low, the reference voltage level Vcl, H is raised. The reference voltage level VclH, L is determined by the clamp circuit (35) in FIG. 3 (d) and FIG.
As shown in (d), DC regeneration is performed at a constant value, for example, 2V.

As a result, the white level VW and the black level VB in FIGS. 3C and 4C become 2.5 V and 1.75 V in FIG. 3D, respectively, and FIG. At 2.25 V and 1.5 V, respectively. That is, since DC reproduction is always performed with the reference voltage level Vcl as a constant absolute voltage value, by changing the relative voltage of the reference voltage level Vcl in FIGS. 3C and 4C, FIG.
As shown in (d) and FIG. 4 (d), the DC level of the analog video signal clamped and DC-reproduced can be controlled.

The signal whose DC voltage level is controlled in this manner is supplied to an inverting amplifier circuit (31) and a non-inverting amplifier circuit (3).
In 2), as a result of amplifying the 2V level to the 4V level and inverting and non-inverting around 6V, FIG.
When the reference voltage level Vcl is relatively low as in (c), the analog video signal is higher than the amplified reference voltage level 4V, and the signal in FIG.
As shown in (f), the lower end is 2.5V and the upper end is 9.5V.
Is amplified to a signal of small amplitude. In the LCD (4), the AC inversion drive centering on 6 V is performed, so that the applied voltage is low overall, that is, in the normally white mode, the luminance level is controlled to be high overall.

Conversely, when the reference voltage level Vcl is relatively high as shown in FIG. 4C, the analog video signal is lower than 4 V after amplification, and As shown in FIG. 4F, the signal is amplified to a signal having a large amplitude with the lower end being 2.1 V and the upper end being 9.9 V. Therefore, the brightness level is controlled to be lower overall. As described above, by controlling the reference voltage level Vcl in the blanking period according to the bright level and the sub-bright level, the bright control and the sub-bright control are performed without greatly increasing the circuit scale.

[0020]

As is apparent from the above description, according to the present invention, the reference voltage level during the blanking period of the input video signal is changed based on the bright signal and the sub-bright signal, thereby clamping this reference voltage level. The DC component of the signal is controlled. Therefore, the number of bits,
Bright control and sub-bright control can be performed without increasing the circuit scale, thereby achieving both cost reduction and high image quality.

[Brief description of the drawings]

FIG. 1 is a partial configuration diagram of a reference voltage control circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an RGB driver according to the embodiment of the present invention.

FIG. 3 is a signal waveform diagram according to the embodiment of the present invention.

FIG. 4 is a signal waveform diagram according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of an LCD module.

FIG. 6 is a configuration diagram of a conventional bright control circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 signal processing circuit 2 D / A converter 3 RGB driver 4 LCD 11 selector 12 reference voltage data generation circuit 31 inverting amplifier circuit 32 non-inverting amplifier circuit 33 selector 34 capacitor 35 clamp circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yusuke Tsutsui 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. (reference) 2H093 NA43 NA53 NA64 NC13 NC16 NC21 ND03 ND17 ND35 ND49 ND54 5C006 AF52 AF73 BB11 BC16 BF28 FA43 FA51 5C080 AA10 BB05 DD22 DD27 JJ02 JJ04

Claims (1)

[Claims] In a drive circuit of a display device in which a plurality of display elements are arranged, a reference voltage control for controlling a reference voltage level based on a bright control signal and a sub-bright control signal during a blanking period of an input video signal. A driving circuit for a display device, comprising: a circuit; a clamp circuit for clamping a reference voltage level of a signal output from the reference voltage control circuit; and an amplifier circuit for amplifying a signal output from the clamp circuit.