JP2000020158A - Time adjusting method for logical computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a guest OS to use the standard time irrelevantly to whether or not a function for referring to the standard time supplied from an external timer mechanism is available by allowing a logical computer control part to set the time on each logical computer to the standard time. SOLUTION: Information for controlling respective logical computers LPAR is prepared by the LPARs in a PRMA. The control information includes control information 3110 on a logical IP belonging to a logical computer and LPAR information 3120 as control information on the LPARs. Information on the time difference between a logical TOD and a physical TOD is stored as information by logical IPs in a time difference information storage area 3111. Then information on the time difference between the logical TOD and standard time which is generated as a result of the execution of the time correcting processing of a physical computer is added to a time difference information storage area 3111 for all logical IPs of all the LPARs. Through this processing, the guest OS is able to continue the same operation as that before time correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical computer system installed outside a logical computer system and having a function of matching a standard time supplied by an external clock mechanism with the time of the logical computer. A function to correct the time of each logical computer to the standard time without depending on the function of the OS (guest OS) operating on the logical computer and without affecting the operation state of the guest OS on the logical computer. Features.

[0002]

2. Description of the Related Art Conventionally, when the time is corrected while the system is operating, the time correction amount is divided into n pieces in order to minimize the influence on the operating state of the system due to the change of the system time. A method of correcting the time by 1 / n is repeated n times to complete the final time correction. Related to this type of time correction method is, for example, a patent application publication number “Japanese Patent Application Laid-Open No. 9-179651”.
No. Gazette.

In a logical computer system, a time difference between the time of the clock mechanism of the physical computer and the time of the clock mechanism of the logical computer is held in the logical computer control unit. The guest OS running on the logical computer has the time of the logical computer
A value obtained by adding the time of the physical computer and the time difference of the logical computer is reported.

When executing the time correction process with the standard time during the operation of the system, the logical computer controller completes the correction of the time of the clock mechanism in the physical computer, and then converts the corrected time to the time difference of each logical computer. to add. At this time, the guest OS on each logical computer does not recognize that the time has changed.

[0005] Thereafter, when the logical computer control unit reports the occurrence of a time deviation from the standard time to each guest OS, each guest OS recognizes the occurrence of the deviation from the standard time and individually executes time correction processing. I do.

[0006]

The above-described conventional time correction processing by each guest OS running on the logical computer has the following problems.

(1) Guest O operating on each logical computer
S refers to the standard time supplied from the external clock,
It must have a time correction function that gradually corrects the current time to match the standard time.

(2) During execution of the time correction processing of the guest OS, normal operation of the processing operating on the guest OS cannot be guaranteed, and therefore, processing other than the correction processing cannot be executed. In particular, if the standard time is earlier than the current time,
When the system time is returned, inconsistency occurs in the system information. Therefore, in each correction process divided into n times, all processes are stopped for a certain period of time within a range that does not affect the operation of the system, and the process waits for the standard time to catch up Becomes

For this reason, the processing for correcting the time difference requires a large overhead for the system. Further, when a plurality of guest OSs are operating on the same physical computer, each guest OS individually performs time correction processing, so that the overhead due to the time correction processing increases according to the number of LPARs.

An object of the present invention is to execute a process of correcting the time of a logical computer by a logical computer control unit when a physical IP is assigned to the logical computer. It is an object of the present invention to enable each guest OS to operate at a standard time regardless of whether or not the function is provided and without affecting the operation state of the guest OS on each logical computer.

[0011]

FIG. 1 shows the configuration of a logical computer system according to the present invention. In FIG. 1, reference numeral 1000 denotes an external clock mechanism that is provided outside the logical computer system and supplies standard time information to the logical computer system. 20
00 is a physical computer system on which the logical computer system operates. 3000 is a logical computer system (PRMA) to which the present invention is applied. In the logical computer system,
A logical computer control unit 3100 for controlling the operation of each logical computer (LPAR) and a time control unit 3200 for controlling the time of the system are included. The logical computer control unit is provided with a time difference storage area 3111 for storing a time difference from a physical TOD prepared for each logical computer. 4000 is a logical computer (LPA) built on the logical computer system.
R), and 5000 is a guest OS running on the logical computer system.

Timekeeping mechanism (TOD) 2 of the physical computer system
100 updates the time in synchronization with the external clock mechanism. P
The RMA time control unit 3200 uses the standard time acquired from the external clock
Set to D mechanism. Thus, the physical TOD time and the standard time match.

On the other hand, a logical computer LPAR (4000)
Sends a logical timekeeping mechanism (TOD) (41
00). The time of the logical TOD mechanism is obtained by adding the time difference information (3111) unique to the LPAR to the time of the physical TOD (2100) on the physical computer system.

The time difference between the external clock mechanism and the physical TOD is reported to the time control unit 3200 of the PRMA by an interrupt. The PRMA time control unit obtains the standard time from the external clock mechanism when the interrupt occurs, and sets the standard time in the physical TOD.

When the time of the physical TOD is changed by the correction processing, the PRMA time control unit stores the time change in the time difference storage area 3111 and the time difference change value storage area 3121 of each LPAR. By this processing, the logical TOD of each logical computer indicates the same time as before the execution of the correction processing of the standard time, and cannot be recognized by the guest OS.

Next, the guest OS (51) on each logical computer
00), the time control unit of the PRMA reports the occurrence of a time lag of the external clock mechanism by an interrupt. Due to the occurrence of the interrupt, the guest OS recognizes the occurrence of a time lag from the external clock mechanism, acquires the standard time from the external clock mechanism, and individually performs time adjustment processing to the standard time.

[0017]

FIG. 2 shows an embodiment of the present invention.
Information for controlling each logical computer (LPAR) is prepared in the PRMA for each LPAR. The control information includes control information 3110 of the logical IP belonging to the logical computer and L
LPAR information 3120 which is PAR control information is included. The time difference information between the logical TOD and the physical TOD is the logical IP
The information is stored in the time difference information storage area 3111 as information for each.

The time difference information between the logical TOD and the standard time generated by the execution of the time correction process of the physical computer is stored in the time difference information storage area 3111 of all the logical IPs of all the LPARs
Is added to. With this process, the guest OS can continue operating as before the time correction. The time difference information is stored in the time difference change value storage area 3121 of each LPAR.
Also stored.

After the completion of the information storage processing, the operation of each LPAR is started. During the operation of the LPAR, the guest OS is operated by sequentially assigning the physical IP to the logical IP belonging to each LPAR. At the time of this physical IP assignment, the time difference between each LPAR and the standard time is absorbed.

FIGS. 3A and 3B are flowcharts of an embodiment of a process for absorbing a time difference from the standard time set in each LPAR.

(1) When assigning a physical IP to a logical IP,
It is checked whether there is a logical IP that belongs to the same LPAR in operation other than the logical IP. Other same LPAR
If the logical IP belonging to is already operating, this process ends without doing anything.

(2) If the time stored in the time zone change value storage area 3121 is positive (the time is delayed), the processing of (3) is executed. If negative (advance time), (4)
Execute the processing of

(3) The time elapsed since the physical IP was previously allocated is represented by the current time and the IP final allocation time 31.
Calculated from 12. Then, the elapsed time is compared with the time stored in the time difference change value storage area 3121. If the time difference change value is larger, the time difference change value is subtracted from the value stored in the time difference storage area 3111. Otherwise,
The elapsed time is subtracted from the value stored in the time difference storage area. The same value is subtracted from the time difference change value storage area. Thereafter, the processing of (5) is executed.

(4) When the time stored in the time difference change value storage area 3121 is smaller than 1 millisecond, when the time stored in the difference storage area is longer, the time stored in the difference storage area In the time difference information storage area 3111
If the time stored in the difference storage area is longer than 1 millisecond subtracted from the time difference, the time stored in the difference storage area is subtracted from the time difference information storage area 3111.

(5) Other logic I belonging to the same LPAR
The same information as that of the own logical IP is stored in the time difference information storage area of P. At the same time, from the LPAR difference storage area 3121,
The same value as the time difference information storage area 3111 is subtracted. The above processing is executed until the value stored in the difference storage area 3121 becomes zero.

As described above, when the time difference stored in the difference storage area has disappeared, the times of all logical IPs coincide with the standard time, and the LPAR of the LPAR is not affected without affecting the operating guest OS. Time setting is completed.

[0027]

The following effects can be obtained by configuring the logical computer system as described above.

(1) According to the present invention, the time on each logical computer is set to the standard time by the logical computer control unit.
There is an effect that the standard time can be used regardless of whether the guest OS operating on the logical computer has a function of referring to the standard time supplied from the external clock mechanism.

(2) According to the present invention, there is an effect that the time correction process of the logical computer can be executed without affecting the normal operation of the guest OS and each process operating under the guest OS.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of a logical computer system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a logical computer system according to an embodiment of the present invention.

FIGS. 3A and 3B are flowcharts of one embodiment relating to time correction processing of the present invention.

[Explanation of symbols]

3200: time control unit, 4100: logical clock mechanism, 51
00: OS time control unit.

Claims (2)

[Claims] 1. A logical computer system comprising at least one logical computer (LPAR), a control mechanism (PRMF) for controlling the logical computer, and an external clock mechanism for supplying a standard time from the outside to the logical computer system OS running on each logical computer in a logical computer system equipped with
(Guest OS) corrects the time of each logical computer to the standard time regardless of whether or not the (guest OS) has the function of obtaining the standard time information and correcting the time. Method. 2. The logical computer system according to claim 1, wherein the time of the logical computer is corrected to a time when the physical IP is not allocated to the logical computer, thereby enabling the guest O
A time adjustment method for a logical computer, wherein the time of the logical computer can be corrected to a standard time without affecting the operation state of S.