JP2000019543A - Active matrix type liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the occurrence of display unevenness accompanying fluctuations in electrode finishing widths by imparting correlative relations to the changes in the finishing dimensions of active element dimension, etc., and the changes in the finishing dimensions of electrode dimensions of pixel electrodes, etc. SOLUTION: TFT channel dimensions, spacings 1 between pixel electrodes and storage capacitor forming part areas are formed by the same source and drain (SD) stage. The liquid crystal display device is so constituted that the fluctuations in these dimensions by the fluctuations in SD stage conditions occur simultaneously while having the correlation. Namely, the formation of the spacings 1 between the pixel electrodes, the TFT channel dimensions and the storage capacitor dimensions is simultaneously executed in the SD stage. If the finishing widths of the electrodes in the SD stage fluctuate, the driving method thereof is composed of the full-common AC driving in which AC is used for both of the common fixed driving or the high and low of gate pulses. As a result, the directions of the changes in the effective driving voltages caused by the dimensional fluctuations act in the direction where the changes in the optical characteristics induced by the dimensional changes of the electrodes to be impressed with transverse electric fields are always compensated, by which the compensation effect is effectively and surely acted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix type liquid crystal display device using a horizontal electric field method.

[0002]

2. Description of the Related Art The display of a liquid crystal display device changes the orientation of the liquid crystal molecules by applying an electric field to the liquid crystal molecules of the liquid crystal layer sandwiched between the substrates. Done.

In particular, an active matrix type liquid crystal display device using an active element typified by a thin film transistor element replaces a CRT in terms of response characteristics such as high definition and capable of responding to a moving image, and is used for OA equipment with lower power consumption. It is expected as a display terminal.

A conventional TN display type active matrix type liquid crystal display device has a drawback that a viewing angle is narrow.
In terms of image quality, it has been a problem for CRT replacement.

[0005] On the other hand, a method (horizontal electric field method) in which the direction of an electric field applied to liquid crystal using a comb-teeth electrode is made substantially parallel to the substrate surface and display is performed by utilizing a change in the birefringence of the liquid crystal is known. No. 63-21907, "R. Kiefer, B. Weber, F. Windcheid a
nd G. Baur, Proceedings of the Twelfth International
Display Research Conference (Japan Display '92)
pp. 547-550 ".

The lateral electric field method has advantages such as a wide viewing angle and a low load capacity as compared with the conventional TN method.
This is a promising technology as an active matrix type liquid crystal display device capable of replacing T.

[0007]

The electric field is applied to the liquid crystal in the TN mode by applying a vertical electric field to the liquid crystal layer using a solid (transparent) electrode, whereas in the lateral electric field mode, a stripe-shaped comb is applied. A lateral electric field is applied using tooth electrodes. In the lateral electric field method, since the electric field is applied by the comb-shaped electrodes, there is a problem that the characteristics are largely fluctuated by an electrode finishing width in a manufacturing process.

That is, when a comb-shaped electrode is formed by the conventional technique, when the electrode width varies due to photomask accuracy, exposure uniformity of photolithography, and variation in etching, the electrode spacing varies due to the variation. Even if the same voltage is applied between the electrodes, the horizontal electric field intensity varies, and the luminance of the display surface becomes uneven. Further, looking at the electro-optical characteristics including the threshold value, in the TN method, the electro-optical characteristics are paired, and the thickness of the liquid crystal layer is equal to the distance between the electrodes for applying an electric field to the liquid crystal layer in pairs. For this reason, the characteristics do not directly depend on the distance between the electrodes (= the thickness of the liquid crystal layer), whereas the in-plane switching method has a direct dependency independently of these, and the change in the characteristics due to the fluctuation is large.

Therefore, in the lateral electric field method, when the interval between the comb-tooth electrodes fluctuates due to the variation in the finished electrode width, a large shift in the electro-optical characteristic curve occurs, which is a major cause of display luminance unevenness.

In order to solve this problem, a counter electrode for applying a horizontal electric field to the liquid crystal layer is formed on the same layer, the display surface is divided, and a small area high-precision photo process is combined with a stepper to improve the electrode finishing accuracy. For example, `` Y.
Matsutani, S. Tahata, M. Hayashi, T.Onawa, K.Kobaya
shi, K.Nagata and M.Morishita, (SID97 Digest) p
p. 14-18 ". However, this method takes a long time to perform the divided photo process using the stepper, and thus is inferior in mass productivity. In particular, it is considered that a serious problem will be caused when the screen size of the liquid crystal display device further increases in the future. As described above, the conventional lateral electric field type active matrix type liquid crystal display device is susceptible to the influence of the variation in the mass production process of the electrode finish width, and the display luminance unevenness due to the variation is likely to occur, and the mass productivity is poor. there were.

An object of the present invention is to provide an active matrix type liquid crystal display device using an in-plane switching method, which has less display unevenness due to variations in electrode finish width, has high image quality, and is excellent in mass productivity. To provide.

[0012]

SUMMARY OF THE INVENTION In the present invention, the above object is achieved by simultaneously generating other fluctuation factors for canceling out and compensating for the effect of the electrode interval fluctuation, and displaying the liquid crystal display device in the horizontal electric field system due to the electrode interval fluctuation. The problem is to be solved by reducing the uneven brightness.

First, a description will be given of the relationship between the fluctuation factors that cause display luminance unevenness in the horizontal electric field method.

Display brightness unevenness is caused by uneven transmittance in a transmissive liquid crystal display element, and is most easily visually recognized at a low transmittance (relative transmittance of 10% to 20%) corresponding to low brightness. Since it is considered that the transmittance-voltage (TV) characteristic in the low transmittance region governs the luminance variation due to the pixel electrode width variation, the T-voltage in the low transmittance region is low.
Consider a model in which the V characteristic is approximated by a straight line. That is, the transmittance-electric field (TE) characteristic of the low transmittance region is linearly approximated as T (E) = α (E−Eth) Eth = (π / d) √ (K2 / Δε) (Eth is The threshold electric field is considered to be a constant here).
= V / l, the transmittance-voltage (TV) characteristic can be expressed as T (V) = (α / l) (V−Ethl).

It should be noted that the TV characteristic model is not limited to the low transmittance region and can be considered as a model obtained by tangent approximation at an arbitrary point.

From the above equation, the variation (ΔT) of the transmittance due to the slight variation of each parameter is as follows: ΔT = (ΔT / ΔV) ΔV + (ΔT / Δl) Δl + (ΔT / Δα) Δα = ( α / l) ΔV− (αV / l ＾ 2) Δl + ((V−Ethl) / l) Δα (1) It is an expression for sensitivity analysis of each variation factor with respect to the total transmittance variation ΔT, and the term Δl is the term of the variation of the electrode interval l due to the variation of the pixel electrode width, which is the subject now.
This is the main cause of the transmittance variation ΔT on the left side, and is a cause of display luminance unevenness. As a method of reducing the transmittance variation ΔT to reduce the display luminance unevenness, a method of canceling the variation among a plurality of terms which are factors of the transmittance variation can be considered. For example, if the liquid crystal drive voltage V in the second term on the right side simultaneously increases (or decreases) with a positive correlation with the electrode spacing change in the first term, the changes compensate each other to reduce the total transmittance change. Can be smaller. This compensation condition is expressed by the following equation: (V / l) Δl = ΔV (2) The above equation shows that the reduction of the lateral electric field applied to the liquid crystal layer due to the enlargement Δl of the pixel electrode interval on the left side (EΔl to (V / l) 1) The condition that the effect of Δl) is compensated by the increase ΔV of the effective drive voltage on the right side (the same is true for the fluctuations in the opposite directions).

It has been found that, in order to compensate for the influence of the electrode spacing fluctuation by the driving voltage fluctuation, the driving voltage fluctuation must occur simultaneously with a positive correlation with the electrode spacing fluctuation as a precondition.

Next, a method for simultaneously generating the above two variations will be described with reference to the drawings. FIG. 1 shows a thin film transistor (TFT: Thin Fir) as an active element.
TFT as an example of an in-plane switching mode active matrix type liquid crystal display device of the present invention using a TFT (Transistor).
FIG. 2 is a conceptual plan view of one pixel on a substrate side and a peripheral portion thereof. FIG. 2 is a section taken along line 6-6 in FIG. FIG. 3 is a sectional view taken along line 7-7 in FIG.
It is sectional drawing in a cut surface. FIG. 4 is a sectional view taken along line 8-8 of FIG. As shown in these drawings, in the present invention, one of the common electrode and the pixel electrode that apply a lateral electric field to the liquid crystal as a pair,
Same layer (SD) as source / drain electrodes on top of this TFT
Layer). Further, as shown in FIG. 4, in the present invention, the storage capacitance is formed by the overlap between the common electrode and the pixel electrode, and the overlap area for determining the storage capacitance value is the pixel electrode side in the SD layer. This is the configuration determined by The present invention is further configured such that the electrodes of the SD layer are collectively formed (all display surfaces) in the same photomask as the SD process. That is,
The present invention is directed to a pixel-common electrode interval that affects the lateral electric field applied to the liquid crystal and a source / drain electrode that affects the TFT characteristics when the electrode finish width of the SD layer fluctuates due to variations in photolithography or etching in the SD process. Size,
It is configured such that the overlap area between the pixel and the common electrode that determines the storage capacitance fluctuates simultaneously with a correlation. According to this configuration, the effect of the finished dimensional variation of the SD layer on the display characteristics is the largest compared to the dimensional variation of the other layers. Most of the influence of can be suppressed.

The electrodes formed in the same layer as the TFT source / drain electrodes are not limited to the pixel electrodes in the above example, but may be common electrodes or both pixel electrodes or common electrodes. In any case, since the dimensions of the TFT source / drain electrodes and the dimensions of the storage capacitor and the distance between the pixel and the common electrode are determined in the same process (photo and etching processes), their dimensional fluctuations occur simultaneously with correlation. ing.

Next, with the configuration of the present invention as a background, let us consider conditions for compensating for transmittance fluctuations due to electrode spacing fluctuations. Fluctuations in the effective drive voltage occur due to the electrode size fluctuations in the SD process, and if this works in a direction to compensate for the effects of the electrode spacing fluctuations described above, as a result, the luminance (transmittance) fluctuations due to the electrode finish size fluctuations in the SD process are reduced. It is thought that it can be done.

Next, a description will be given of a method of causing a change in the effective drive voltage such that the above-described compensation occurs due to a change in the SD process dimension.

A so-called feed-through voltage is known as a mechanism for changing the driving voltage due to the dimensional fluctuation of the TFT electrode and the like as described above. The field-through voltage is a decrease in the source potential due to the capacitance division of the electric charge held in the TFT parasitic capacitance immediately after the TFT is turned off. This feedthrough voltage ΔV _S is generally ignored if it is considered that the influence of recharging due to a delay of a gate pulse, which causes a difference in image quality between the center and both ends of the display screen, is suppressed to some extent by design. Is expressed by the following equation.

[0023] _{ΔV S = (1 / Ctot)} {Cgson (V GH -V GL) -ΔCgs (V D -V GL)} ... (3) Ctot = Cgsoff + Cstg + Clc ΔCgs = Cgson-Cgsoff Here, Cgson, Cgsoff each The gate-source parasitic capacitance when the TFT is on and off, Clc and Cstg are the pixel liquid crystal capacitance and the storage capacitance, respectively, and V _GH , V _GL and V _D are the high gate pulse potential, the low gate pulse potential and the drain potential, respectively.

From the above equation, it can be seen that the feedthrough voltage depends on the high gate pulse potential and the drain potential viewed from the low gate pulse potential, and is determined by the gate-source parasitic capacitance Cgs of the TFT.
Considering this Cgs, the Mayer model assuming a sufficiently high write rate (V _GS −V _TH >> V _DS ) for the intrinsic parasitic capacitance and the MIS-type capacitance for the overlap capacitance, Cgson = (W _a Co) _{/ 2) l g Cgsoff = {} (W Co Ca) / (Co + Ca)} l s = {(W Co)
/ 2} {Ca / (Co + Ca)} expressed as (l _g -L).

Here, L and W are the TFT channel length and width shown in the sectional view 3 and the plan view 5 of the TFT portion, respectively (where W is defined as the width of the source electrode which determines Cgsoff).
In, W _a is the width of the amorphous silicon (a-Si) layer that determines the Cgson when the TFT ON (this W _a is SD
It is determined not in the process but in the a-Si layer process).

[0026] l _s, l _d is the overlap between the gate electrode portion of each source-drain electrode (width l _g), where assumed (hence L = l _g -2l and both equal
_s ). Co and Ca are a gate insulating layer and a-Si, respectively.
The capacity per unit area of the layer.

From the above equation, the TFT size variation in the SD process and C
Considering the relationship of the variation of gs, Cgson is not affected by the dimensional variation of the SD process, whereas Cgsoff and ΔCgs
Changes depending on the channel length L and the width W determined in the SD process.

Next, the change in the effective drive voltage caused by the change in the TFT channel size will be described. First, in the case of driving in which the common electrode potential is fixed and whose conceptual driving waveform is shown in FIG. 6, the effective voltage actually applied to the liquid crystal in consideration of the feedthrough voltage is considered. For common fixed drive, the drain potential positive writing (V _D ⁺⁾ and negative writing of the image signal voltage V _SIG (V _D ^-) corresponds to is expressed by the following equation.

V _D ± = ± V _SIG + V _D-CENTER Here, the image signal voltage V _SIG is approximately: 0 (black display) ≦, where V _MAX is a drive voltage that has a peak transmittance in the TV characteristic of the pixel. It is input in the range of V _SIG ≦ V _MAX (white display) (in the horizontal electric field method, black and white are usually opposite to the TN method).

The liquid crystal driving effective value voltage V _LC changes as shown in FIG.
_{Specifically, V LC = √ [{(} V D + -ΔV S + -V COM) ^ 2 + (V D - -ΔV S -
−V _COM ) ^ 2} / 2].

Here, ΔV _S ⁺ and ΔV _S ^- are feed-through voltages at the time of positive and negative writing, respectively.

[0032] the above equation, the equation above _{V D ±, V COM = V} D-CENTER - obtained by substituting the formula ^{_{- (1/2) (ΔV S +}} + ΔV S).

[0033] _{V LC = | V SIG + (} 1/2) (ΔV S - -Δ
V _S ⁺ ) | The second term on the right side is a change in the drive voltage due to the contribution of the feed-through voltage, and the amount of change is half the difference between the feed-through voltages during positive and negative writing.

In the above equation, the field through voltage Δ in equation (3)
Substituting the equation for V _S and the above equation for V _D ±, eventually V _LC becomes V
_{Since SIG} ≧ 0 and ΔCgs> 0, V _LC = V _SIG {1+ (ΔCgs / Ctot)}.

From this equation, the change in the drive voltage due to the feedthrough voltage in the case of the common fixed drive is ΔCgs / Ctot
It turns out that it is proportional to.

Next, consider the case of common AC drive in which the common electrode potential is changed to AC, which is often used as a method for reducing the withstand voltage of the drain driver.

In the common AC drive, as the name implies, the common potential is _converted into _AC with a voltage width V _CPP centered on V _COMC as follows.

V _COM ± = ± (１ ／) V _CPP + V _COMC Here, the central potential V _COMC is given by the following equation, which is the same as that for fixing common.

[0039] _{V COM = V D-CENTER -} (1/2) - think in common alternating current at the time of the drain potential is also the same form V _D ± at the time of the common fixed _{= ± V SIG + V D-} CENTER (ΔV S + + ΔV S) However, since the image signal voltage V _{SIG in} the case of common AC is swung including the phase with respect to the AC common potential, V _SIG can be positive or negative. In-phase.

In the case where the equation is made to correspond to the equation in the case where the common is fixed, assuming that the common potential amplitude V _CPP = V _MAX , − (１ ／) V _MAX (black display) ≦ V _SIG ≦ (１ ／) V _MAX (white (Shown).

That is, since V _SIG is swung both positively and negatively as in the above equation, the variation width of V _SIG is the same
It becomes _MAX , but the change width of the drain potential (output width of the drain driver) is half that when the common is fixed.

In the actual common AC driving, the voltage applied to the pixel is not changed from 0 V but is changed from the threshold value V _TH of the TV characteristic of the pixel in order to further reduce the change width of the drain potential. To

That is, the common potential amplitude is increased by V _TH and V
Amount that was _{CPP = V MAX + V TH,} - (1/2) (V MAX -V TH) ( black display) ≦ V _SIG ≦ (1/2)
(V _MAX -V _TH ) (white display) and the change width of the drain potential is further reduced by V _{TH to} V _MAX -V
_TH . After all, the effective value voltage V _LC of the liquid crystal drive when the common alternating _{current, V LC = √ [{(} V D + -ΔV S + -V COM -) ^ 2 + (V D - -ΔV S
^- represented by ^{_{-V COM +) ^ 2} /}} 2].

By substituting the above equations for V _COMC and V _D ±, the following equation is obtained.

[0045] _{V LC = (1/2) | 2V} SIG + V CPP + ΔV S - -ΔV S + | and then think about the field-through voltage at the time of the common AC drive, at the time of the common exchanges in the formula of the preceding ΔV _S gate considering that it is also the alternating ^{_{voltage, ΔV S + = (1 /}} Ctot) {Cgson (V GH - -V GL -) -ΔCgs
^{_{(V D + -V GL -)}} } ΔV S - = (1 / Ctot) {Cgson (V GH + -V GL +) -ΔCgs
Obtaining a ^{_{- (V D -V GL +)}} }.

By substituting the above equation into the equation for _VLC , the following equation is obtained.

V _LC = (1/2) | 2 V _SIG + V _CPP + (Cgso
^{_{n / Ctot) (V GH +}} -V GL + -V GH - + V GL -) + (ΔCgs / C
tot) (V _D ⁺ −V _D ⁻ + V _GL ⁺ −V _GL ⁻ ) | Here, the alternating of the gate potential is performed by converting the gate low potential into the same potential and the same amplitude as the common potential, and the amplitude V
_{Assuming that} the _GPP gate pulse is superimposed, it is expressed by the following equation.

V_GL± = ± (1/2) V_CPP+ V_GLC  V_GH± = V_GPP+ V_GL± That is, the gate pulse waveform is a quaternary AC waveform.

By substituting these, Cgs is obtained from the above equation of _VLC .
When the term of on disappears and the expression of V _D ± is further substituted, eventually V
_LC is V _LC = V ′ _SIG {1+ (ΔCgs / Ctot)} where V ′ _SIG = V _SIG + V _CPP / 2.

In the above equation, V ' _SIG = V _SIG + V _CPP / 2 corresponds to V _SIG when the common is fixed. Therefore, this equation is considered to be equivalent to the corresponding equation when the common is fixed.

Accordingly, the variation of the effective drive voltage due to the variation in the SD process dimension during the common AC drive (hereinafter referred to as full common AC drive) in which the gate pulse is similarly AC-converted in both low and high as described above is described. It is considered the same as when the common was fixed in the previous section.

On the other hand, in a common AC drive actually used in a product, a gate low potential is almost always AC-converted as in the above-mentioned case, but a method using a gate pulse with a fixed gate high potential is used. It is used because the withstand voltage of the driver is low and the circuit can be simplified.

The gate pulse waveform in this case is expressed by the following equation.

V _GL ± = ± ()) V _CPP + V _GLC V _GH ± = V _{GPP In other} words, the gate high potential remains unchanged between positive and negative write, and the gate pulse waveform becomes a ternary AC waveform.

When the above gate pulse waveform is substituted into the equation of _VLC , in this case, the term of Cgson does not disappear and the remaining _VLC is expressed by the following equation.

V _LC = V ′ _SIG [1+ (ΔCgs / Ctot) −
(Cgson / Ctot) {V _CPP / (2V _SIG + V _CPP )｝] In the above equation, the newly added Cgson term is the difference in the fall width of the gate pulse at the time of positive / negative writing (the full common AC drive described above). Is the same).

Summarizing the above results, the effective drive voltage is expressed by the following generalized equation for both the common fixed and the common AC drive.

V _LC = V ′ _SIG ｛1+ (ΔC′gs / Ctot)} In the common fixed drive, V ′ _SIG = V _SIG , ΔC′gs = ΔCgs In the full common AC drive in which both the gate low potential and the gate high potential are exchanged. V ′ _SIG = V _SIG + V _CPP / 2 ΔC′gs = ΔCgs In a normal common AC drive in which only the gate low potential is changed to AC, V ′ _SIG = V _SIG + V _CPP / 2 ΔC′gs = ΔCgs− {V _CPP / (2V _SIG + V _CPP )} Cgson = (V _SIG / V ′ _SIG ) Cgson−Cgsoff

The last equation shows that in a normal common AC drive in which only the gate low potential is converted into an AC (in contrast to ΔC′gs = ΔCgs> 0 in a fixed common and full common AC drive), the effective ΔC ′ is obtained. gs is changed by the image signal potential V _SIG, indicates that considered can become a ΔC'gs <0 (at low luminance).

Here, the means of the present invention described so far are reconfirmed. In the lateral electric field type active matrix type liquid crystal display element of the present invention, the TFT channel dimensions L, W
The pixel electrode interval l and the storage capacitor formation area S are formed by the same source / drain (SD) process.
These dimensional variations due to variations in the D process conditions are configured to occur simultaneously with a correlation.

Specifically, assuming that the amount of one-side retreat from the designed value of the finished value of the pixel electrode width in the SD process is Δl,
The pixel electrode interval 1 which is the interval between the pixel and the common electrode in the gate common (GC) layer in FIG. 2 changes by Δl.

On the other hand, the one-side retreat amount Δl in the above-mentioned SD step
Considering the contribution of both the source and drain electrodes, ΔL of the TFT channel length L = 2Δl and ΔW of the channel width W = −2
Δl fluctuates.

Further, the variation of the electrode finish width in the SD process is formed by the variation of the liquid crystal pixel capacitance Clc included in Ctot in the equation of the effective drive voltage _VLC (due to Δl) and the overlap of the pixel / common electrode. The change ΔS of the overlap area S of the storage capacitor Cstg occurs, and the change of the effective drive voltage due to these changes is given by the following equation. _{ΔV LC (ΔL, ΔW, Δl} , ΔS) = ∂V LC / ∂L ΔL + ∂V LC / ∂W ΔW + ∂V LC / ∂l Δl + ∂V LC / ∂S ΔS = {(∂ΔC'gs / ∂L) (∂V LC / ∂ΔC'gs) + (∂Ctot / ∂L) (∂V LC / ∂Ctot)} (2Δl) + {(∂ΔC _{'gs / ∂W) (∂V LC} / ∂ΔC'gs) + (∂Ctot / ∂W) (∂V LC / ∂Ctot)} (- 2Δl) + {(∂Ctot / ∂l) (∂V LC / ∂Ctot)} Δl + (∂Ctot / ∂S) (∂V LC / ∂Ctot)} {- 2 (1 + a) l st} Δl = [(∂ΔC'gs / ∂L-∂ΔC'gs / ∂ W) (∂V _LC / ∂ΔC′gs) + {∂Ctot / ∂L−∂Ctot / ∂W + (1/2) ∂Ctot / ∂l − (1 + a) l _st (∂Ctot / ∂S)｝ ( in ∂V _LC / ∂Ctot)] 2Δl above equation, the shape of the portion overlapping electrodes forming the storage capacitance Cstg in short side l _st considered rectangular long side a l _st, this part by one retraction amount Δl The change ΔS in area is (Δl
Of ignoring the second-order _{term), ΔS = (l st -2Δl} ) (a l st -2Δl) -a l st ^ 2
−２−2 (1 + a) l _st Δl

By substituting this equation into the compensation condition equation (2) obtained from the sensitivity analysis, V _LC / l = 2 [(∂ΔC'gs / ∂L-∂ΔC'gs / ∂W)
(∂V _LC / ∂ΔC'gs) + ｛∂Ctot / ∂L-∂Ctot / ∂
W + (1/2) ∂Ctot / ∂l- (1 + a) l st (∂Ctot /
{S)｝ (｝ V _LC / ∂Ctot)] Each partial differential term in the above equation is evaluated and rearranged using ltot, which is defined later, to eventually obtain the following equation as a compensation condition equation.

[0065] (1 / l) {1+ ( ΔC'gs / Ctot)} = (1 / Ctot) (Cgsoff / l s + 2Cgsoff / W + ΔC'gs / ltot) ... (4) above equation left side pixel electrode spacing variation, The right side is the term of the drive voltage fluctuation caused by the feedthrough voltage, and the above equation expresses the condition that these two contributions are compensated (within the range of minute fluctuation) and the total transmittance fluctuation is apparently zero.

To further explain the physical meaning of each term in the above equation, the first item on the left side is a pixel electrode interval variation item, and the second item is a correction item due to a change in the effective drive voltage due to the feedthrough voltage.

Normally, ΔC′gs≪Ctot, so this correction term is almost negligible compared to the first term on the left side.

On the other hand, looking at the respective items of the drive voltage fluctuation on the right side, the first and second items on the right side contribute to changes in the TFT channel lengths L and W, respectively.
In the term of change in tot, the coefficient of the change, 1 / ltot, is defined by the following equation.

[0069] 1 / ltot = (1 / Ctot ) [Cgsoff / l s +
2Cgsoff / W + Clc / l + 2 {(1 + a) / a} Cstg / l
_st ] Realistically, most of this 1 / ltot is a variation term of the storage capacitance Cstg which is the last term.

The coefficient of the variation term of the storage capacitance (the last term on the right side of the above equation) is the rate of change of the area S of the electrode overlapping portion forming the storage capacitance per electrode one-side retreat amount Δl, (ΔS / S ) / Δl to −2 (1 + a) l _st / {al _st ＾
2} = − 2 {(1 + a) / a｝ / _lst .

The coefficient (ΔS / S) / Δl changes depending on the shape of the above-mentioned electrode overlapping portion.

For example, it is assumed that the shape of the storage capacitor forming portion is changed, and the long side of the above-mentioned rectangle is divided into N equal parts and separated to form a storage capacitor.

In this case, the total area does not change, and each rectangle has an area S ′ = l _st (a / N) l _st and N storage capacitors are formed.

[0074] coefficients in this case (ΔS / S) / Δl is, (ΔS / S) Δl = {NΔS '/ (NS')} / Δl = -N2 (1 + a / N) l st / {N (a / N) l _st {2} = − 2 {1+ (a / N)} / {(a / N) l _st }, and Cstg remains the same, and a becomes apparently a / N (ΔS / S) It can be seen that Δl can be increased, and as a result, 1 / ltot can be increased by the shape effect of the storage capacitor.

Next, the above compensation conditions are considered for each of the individual driving methods.

First, considering a full common AC drive in which both the fixed common and the gate high / low are converted to AC,
Since C′gs = ΔCgs and ΔCgs> 0, all three terms of the right-hand side drive voltage fluctuation are positive and work in a direction that always compensates for the left-hand side image electrode interval fluctuation.

In the case of the fixed common and full common AC drive, the compensation condition formula is formally independent of the drive voltage condition (actually, the pixel capacitance Clc in Ctot is less than the drive voltage dependency Clc (V _LC ). Has) shape.

Next, considering the case of common AC drive in which only the normally used gate low potential is converted to AC, in this case, unlike the above case, ΔC′gs is the direct drive voltage parameter V _SIG / V ′ _SIG . Because of this, it has direct image signal voltage dependence.

The above-described range of the image signal voltage at the time of the common AC drive, V _CPP = V _MAX + V _TH- (1/2) (V _MAX -V _TH ) (black display)
≦ V _SIG ≦ (１ ／) (V _MAX −V _TH ) (displayed in white) and V _TH ≦ V ′ _SIG ≦ V _MAX , this parameter V _SIG / V ′ _SIG has a low transmittance that causes uneven brightness. In the compensation condition (4), ΔC′gs = (V _SIG / V ′ _SIG ) Cgson−Cgsoff <0 on the right side in the compensation condition (4) because the ratio has a negative value.

Therefore, in the case of ordinary common AC driving, on the low transmittance side, the third item on the right side (variation term of the total load capacity) of the above-mentioned compensation condition expression is usually as large as the first and second items on the right side. Therefore, in most cases, the right term is not large enough to compensate for the effect of the pixel electrode interval variation on the left side, or the whole right side is negative, because in most cases, the three terms on the right side cancel each other out. As a result, it is conceivable that the left side does not become a direction for compensating, and conversely, a direction for increasing the length.

At this time, the correction term of the electrode spacing variation term of the second item on the left side also becomes negative, and acts in a direction to reduce the transmittance variation due to the effect. As described above, the effect of this correction term is relatively small. The effect of the ineffectiveness of the drive voltage compensation described above is much greater.

The common AC drive generally used in the above point is disadvantageous in principle in comparison with the common fixed and the full common AC drive in the above configuration in order to increase the margin of variation in the dimension of the SD process by the drive voltage compensation. It turns out there is.

Therefore, according to the configuration of the present invention described above, the pixel electrode interval, the TFT channel size, and the storage capacitor portion size are simultaneously formed in the SD process, and the finished width of the electrodes in the SD process varies. If the pixel-common electrode interval l that affects the horizontal electric field applied to the liquid crystal and the TFT channel size and the storage capacitor area that affect the effective driving voltage are simultaneously fluctuated with a correlation, the driving method is the common fixed driving. Alternatively, by changing the gate pulse high and low to full AC drive, the direction of the change in the effective drive voltage caused by the dimensional fluctuation is always changed by the dimensional change of the electrode to which the lateral electric field is applied. In the direction of compensating, so that the compensating action works effectively and reliably.

By the compensation effect described above, the gate voltage of all the display surfaces and all the pixel TFTs of the liquid crystal display device of the present invention is always turned on with the gate voltage not lower than the threshold value. ２０20% relative luminance) and the same luminance display on the entire display surface with the same
Compared with the case where the FT is displayed with the FT turned on and off temporally in the same manner as the actual use state, the display luminance non-uniformity is greatly improved in the latter in which the compensation effect works as compared with the former in which the compensation effect does not work. .

As a result of various studies, it has been found that in order to obtain the same display uniformity under almost the same conditions as in the method of assuring the finished electrode dimensional accuracy by combining the small area high-precision photo process with the stepper described in the prior art, It has been found that the reduction rate of the display luminance unevenness may be set to 20% or more.

As described above, according to the present invention, in a lateral electric field type active matrix liquid crystal display device, the electrode finishing width is hardly affected by a variation in the mass production process, and the display brightness unevenness caused by the variation is less likely to occur. An active matrix liquid crystal display device excellent in mass productivity can be obtained. FIG. 19 illustrates the overall configuration of the present invention described above. Scan electrode drive circuit 18 for driving scan electrodes and signal electrode drive circuit 1 for driving signal electrodes
9, a control circuit 17 for controlling the scan electrode drive circuit 18 and the signal electrode drive circuit 19, a common electrode drive circuit 20 for driving the common electrodes, and a liquid crystal panel unit 21. The liquid crystal display panel 21 includes a signal line for transmitting a signal under the control of the signal electrode driving circuit 19 and the scanning electrode driving circuit 1.
A thin film semiconductor (TFT), a liquid crystal capacitance portion Clc, and a storage capacitance portion Cstg are formed at each intersection of the eight scanning lines.

[0087]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows an active device according to the present invention.
FIG. 2 is a plan view showing one pixel of a matrix type color liquid crystal display device and its periphery. As shown in FIG. 1, each pixel has a gate signal line (scanning signal line or horizontal signal line) GL, a counter voltage wiring (common voltage signal line) CL, and two adjacent drain signal lines (video signal line or video signal line). The vertical signal lines) are arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a common electrode CT.
The gate signal lines GL and the counter voltage signal lines CL extend in the left-right direction in FIG. The drain signal lines DL extend in the up-down direction, and a plurality of drain signal lines DL are arranged in the left-right direction. The pixel electrode PX is electrically connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL. Here, the gate signal line GL is for transmitting a gate signal to the thin film transistor element of each pixel, and the drain signal line DL is for supplying a drain signal voltage to the pixel electrode PX of each pixel via the thin film transistor element. The common voltage signal line CL is for supplying a common voltage to the common electrode CT of each pixel.

The pixel electrode PX and the common electrode CT are opposed to each other, and the optical state of the liquid crystal LC is controlled by an electric field substantially parallel to the substrate surface generated between each pixel electrode PX and the common electrode CT. Control. The pixel electrode PX and the common electrode CT are formed in a comb shape, and each is an electrode that is elongated in the vertical direction in the figure.

In this embodiment, the common electrode CT in one pixel
Are three, and the number of pixel electrodes PX is two. However, the present invention is not limited to this, and the number O (the number of comb teeth) of the common electrode CT and the number P (the number of comb teeth) P of the pixel electrode PX in one pixel are O = P
What is necessary is just to comprise so that it may have a relation of +1.

The electrode interval between the pixel electrode PX and the common electrode CT changes depending on the liquid crystal material used. this is,
Since the electric field intensity that achieves the maximum transmittance varies depending on the liquid crystal material, the electrode spacing is set according to the liquid crystal material, and within the range of the maximum amplitude of the signal voltage set by the withstand voltage of the drain signal drive circuit (signal side driver) used. , So that the maximum transmittance can be obtained.

As shown in FIGS. 2 to 4, the liquid crystal composition layer L
With reference to C, a thin film transistor TFT, a storage capacitor Cstg and an electrode group are formed on the lower transparent glass substrate SUB1 side, and a color filter FIL and a light shielding black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side.

Further, the transparent glass substrates SUB1, SUB2
Are provided with alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal on the inner surface (on the liquid crystal LC side) of the substrate, and the polarizing plate POL1 is provided on the outer surfaces of the transparent glass substrates SUB1 and SUB2. , POL2 are provided.

First, the lower transparent glass substrate SUB1 side (T
The configuration of the FT substrate will be described in detail. When a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain of the thin film transistor TFT decreases,
When the bias is set to zero, the channel resistance operates so as to increase.

As shown in FIG. 3, the thin film transistor TFT includes a gate electrode GT, an insulating film GI, and an i-type (intrinsic,
nsic, an i-type semiconductor layer AS made of amorphous silicon (Si not doped with a conductivity type determining impurity), and a pair of source electrode SD1 and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during operation, so that the source and drain are switched during operation. For the sake of convenience in the following description, one is fixed as a source and the other is fixed as a drain.

The gate electrode GT is formed continuously with the gate signal line GL, and is configured so that a partial region of the gate signal line GL becomes the gate electrode GT. The gate electrode GT is a portion beyond the active area of the thin film transistor TFT. In this example, the gate electrode GT is formed of a single-layer conductive film g3. As the conductive film g3, for example, a chromium-molybdenum alloy (Cr-M
o) A membrane is used, but is not limited thereto. Further, two layers of different kinds of metals may be formed.

The gate signal line GL is made of a conductive film g3. The conductive film g3 of the gate signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed. The gate signal line GL, is supplied from an external circuit of the gate voltage (gate voltage) V _G to the gate electrode GT. In this example, as the conductive film g3, for example, a chromium-molybdenum alloy (Cr-
Mo) film is used. Further, the gate signal line GL and the gate electrode GT are not limited to the chromium-molybdenum alloy, and may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum for low resistance. . Further, the portion that intersects with the drain signal line DL may be thinned in order to reduce the probability of a short circuit with the drain signal line DL, or may be bifurcated so that even if a short circuit occurs, it can be separated by laser trimming.

The opposite voltage signal line CL is formed of the conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the gate signal line GL, and the common electrode CT, and is formed integrally with the common electrode CT. The common voltage V _COM is applied from an external circuit to the common electrode CT by the counter voltage signal line CL.
To supply. Further, the counter voltage signal line CL is not limited to only the chromium-molybdenum alloy, for example,
A two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum may be used to reduce resistance. Further, the portion that intersects with the drain signal line DL may be thinned in order to reduce the probability of a short circuit with the drain signal line DL, or may be bifurcated so that even if a short circuit occurs, it can be separated by laser trimming.

The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. Insulating film GI
Are formed above the gate electrode GT and the gate signal line GL. As the insulating film GI, for example, plasma CVD
Silicon nitride film formed by
It is formed to a thickness of 00 ° (about 3500 ° in this embodiment). The insulating film GI also functions as an interlayer insulating film between the gate signal line GL, the counter voltage signal line CL, and the drain signal line DL, and also contributes to electrical insulation thereof.

The i-type semiconductor layer AS is made of amorphous silicon.
In a thickness of 150 to 2500 mm (in this embodiment, 1200
Å film thickness). The layer d0 is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and an i-type semiconductor layer AS exists below,
It is left only where the conductive layer d3 exists on the upper side.

The i-type semiconductor layer AS and the layer d0 are also provided between the gate signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the drain signal line DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the gate signal line GL and the counter voltage signal line CL and the drain signal line DL at the intersection.

Each of the source electrode SD1 and the drain electrode SD2 is a conductive film d which is in contact with the N (+) type semiconductor layer d0.
3 is comprised.

The conductive film d3 is made of chromium-
Using a molybdenum alloy (Cr-Mo) film,
It is formed to a thickness of 00 ° (about 2500 ° in this embodiment). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WS) in addition to the Cr—Mo film.
i ₂ ) A film may be used, or a laminated structure with aluminum or the like may be used.

The drain signal line DL is connected to the source electrodes SD1,
It is composed of a conductive film d3 of the same layer as the drain electrode SD2. Further, the drain signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d3 uses a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering and has a thickness of 500 to 3000 ° (in this example,
(About 2500 °). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, in addition to the Cr—Mo film, a high melting point metal (Mo, Ti, T
a, W) film, refractory metal silicide (MoSi ₂ , Ti)
Si ₂ , TaSi ₂ , WSi ₂ ) film may be used, or a laminated structure with aluminum or the like may be used.

The conductive film d3 forming the storage capacitor Cstg is:
The source electrode SD1 of the thin film transistor TFT is formed so as to overlap the counter voltage signal line CL. As is clear from FIG. 5, this superposition is formed in the same manufacturing process using the source electrode SD1 (d3) as one electrode, and is formed integrally with the pixel electrode PX, and the common voltage signal CL is connected to the other electrode. To form a storage capacitor (capacitance element) Cstg. The dielectric film of the storage capacitor Cstg is constituted by an insulating film GI used as a gate insulating film of the thin film transistor TFT.

As shown in FIG. 1, the storage capacitance Cst
g is formed on a part of the counter voltage signal line CL.

A protective film PS is formed on the thin film transistor TFT.
V1 is provided. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 0.1 to 1 μm.

The protection film PSV1 is connected to the external connection terminals DTM,
Removed to expose GTM. Protective film PSV1
And the thickness of the insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in the transconductance gm of the transistor.

The protective film PSV1 may have a laminated structure with a thick organic film such as polyimide.

The pixel electrode PX is formed in the same manufacturing process as the source electrode SD1, and is formed integrally with the source electrode SD1 and the conductive film d3 of the storage capacitor forming portion.

The common electrode CT is formed integrally with the counter voltage signal line CL.

[0112] is configured as a common voltage V _COM is applied to the common electrode CT. In the present embodiment, the common voltage V _COM is used when the thin film transistor element TFT is turned off from an intermediate DC potential between the minimum level driving voltage V _DMIN and the maximum level driving voltage V _DMAX applied to the drain signal line DL. It is set to a potential lower feed-through voltage [Delta] V _S content generated.

The common potential is set to a temporally constant potential in order to exhibit the effect of compensating for the influence of the dimensional variation of the present invention.

Next, returning to FIGS. 1 and 2, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.

The upper transparent glass substrate SUB2 has a structure shown in FIG.
As shown in the BM boundary line shown in FIG.
A light-shielding film BM (so-called black matrix) is formed so that transmitted light from a gap other than the gap between the common electrode CT and the common electrode CT is emitted to the display surface side and the contrast ratio and the like are not reduced. The light-shielding film BM also plays a role of preventing external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light-shielding films BM and the large gate electrode GT, so that external natural light or backlight does not shine.

Although the light-shielding film BM shown in FIG. 1 is shown only for one pixel, it is formed so that the inside is open for every pixel. Also, this pattern
This is one example. In a portion where the direction of the electric field is disturbed, such as a comb-teeth electrode end, the display of the portion corresponds to the video information in the pixel on a one-to-one basis, and is black in black and white in white. Therefore, it can be used as a part of the display.

However, the light shielding film BM must have a light shielding property. In particular, the pixel electrode PX and the common electrode C
The gap between T requires an optical density of 3 or more in order to suppress crosstalk (vertical smear) in the drain signal line direction. Further, it may be formed of a conductive metal such as Cr, but is preferably formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the common electrode CT. In this embodiment, a black organic pigment is mixed into a resist material to form a film having a thickness of about 1.2 μm. Also,
Carbon and titanium oxide (TixOy) may be mixed in order to improve the light shielding property as long as the insulating property can maintain 108 Ωcm or more that does not affect the electric field in the liquid crystal composition layer.

Since the light-shielding film BM divides the effective display area of each row, it also has a role of clarifying the outline of the pixels of each row.

The light-shielding film BM is also formed in a peripheral part in a frame shape, and its pattern is formed continuously with the pattern of the matrix part shown in FIG. The light-shielding film BM in the peripheral portion is extended to the outside of the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion, and to prevent light such as a backlight from being out of the display area. To prevent leakage. On the other hand, this light shielding film BM is
It is fixed about 0.3 to 1.0 mm inside the edge of the substrate 2 and is formed avoiding the cutting area of the substrate SUB2. The color filters FIL are formed in stripes at positions facing the pixels by repeating red, green, and blue. Color filter F
IL is formed so as to overlap the light shielding film BM.

The color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. Note that a dye may be used for dyeing.

The overcoat film OC is formed of a color filter F
It is provided to prevent leakage of the IL dye into the liquid crystal composition layer LC and to flatten the steps formed by the color filter FIL and the light shielding film BM. The overcoat film OC is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin. Further, as the overcoat film OC, an organic film such as polyimide having good fluidity may be used.

Next, a liquid crystal layer, an alignment film, a polarizing plate and the like will be described.

As the liquid crystal composition LC, a dielectric anisotropy Δ
ε is positive and its value is 13.2, refractive index anisotropy Δn is 0.0
A nematic liquid crystal of 81 (589 nm, 20 ° C.) is used. The thickness (gap) of the liquid crystal composition layer is 3.8 μm, and the retardation Δn · d is 0.31 μm. The value of the retardation Δn · d is set between 0.25 μm and 0.35 μm, preferably between 0.28 μm and 0.32 μm. Is 4 from the initial orientation direction to the electric field direction.
When rotated by 5 °, a maximum transmittance can be obtained, and transmitted light having almost no wavelength dependency within a visible light range can be obtained.

The thickness (gap) of the liquid crystal composition layer
Is controlled by polymer beads subjected to a vertical alignment treatment. This stabilizes the alignment of liquid crystal molecules around the beads during black display, obtains a good black level, and improves the contrast ratio.

Note that the liquid crystal material LC is not particularly limited, and the dielectric anisotropy Δε may be negative. When the value of the dielectric anisotropy Δε is larger, the driving voltage can be reduced, and when the value of the refractive index anisotropy Δn is smaller, the thickness (gap) of the liquid crystal layer can be increased.
In addition, gap variations can be reduced.

The specific resistance of the liquid crystal composition is 10
9 Ωcm or more and 1014 Ωcm or less, preferably 1011 Ωcm
Those having a size of 1013 Ωcm or less are used. In this method, the voltage charged between the pixel electrode and the common electrode can be sufficiently maintained even if the resistance of the liquid crystal composition is low, and the lower limit is 109 Ωcm, preferably 1011 Ωcm. this is,
This is because the pixel electrode and the common electrode are formed on the same substrate. On the other hand, if the resistance is too high, it is difficult to alleviate static electricity that has entered the manufacturing process, so that the resistance is 1014 Ωcm or less, preferably 1013 Ωcm or less.

For the orientation film ORI, polyimide is used. The initial alignment direction RDR is made parallel to the upper and lower substrates. Rubbing is the most common method for imparting the initial alignment direction, but oblique evaporation is another method. FIG. 18 shows the relationship between the initial alignment direction RDR and the applied electric field direction EDR. In this embodiment, the initial alignment direction RDR is set to about 75 ° with respect to the horizontal direction.

The angle formed between the initial alignment direction RDR and the applied electric field direction EDR is 45 ° C. or more and less than 90 ° C. if the dielectric anisotropy Δε of the liquid crystal material is positive.
If is negative, it must be greater than 0 ° and less than or equal to 45 °.

As the polarizing plate POL, a conductive polarizing plate is used, and the polarization transmission axis MAX of the lower polarizing plate POL1 is used.
1 with the initial alignment direction RDR, and the upper deflector PO
The polarization transmission axis MAX2 of L2 is made orthogonal to it. FIG.
FIG. 8 shows the relationship. As a result, a normally-closed characteristic in which the transmittance increases with an increase in the voltage (the voltage between the pixel electrode PX and the common electrode CT) applied to the pixel of the present invention can be obtained. In addition, high quality black display can be achieved.

In this embodiment, measures are taken against display failure and EMI caused by external static electricity by imparting conductivity to the polarizing plate. Regarding the conductivity, the sheet resistance is desirably 108 Ω / □ or less if only for the purpose of countermeasures against the influence of static electricity, and is 104 Ω / □ or less if the EMI is also countered. Further, a conductive layer may be provided on the back surface (the surface on which the polarizing plate is adhered) of the sandwiching surface of the liquid crystal composition of the glass substrate.

FIG. 7 shows the upper and lower glass substrates SUB1, SUB.
FIG. 4 is a diagram showing a main part plane around a matrix (AR) of a display panel PNL including the LCD panel 2. FIG. 6 is a diagram showing a cross section near the gate terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0132] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. FIGS. 7 and 8 show the latter example. Both FIGS. 7 and 8 show the upper and lower substrates SUB1 and SUB.
2 shows the state after cutting, and LN indicates the edge of both substrates before cutting. In any case, in the completed state, the external connection terminal group T
g, Td, and the terminal COT (subscript omitted) (the upper side and the left side in the figure) are located on the upper substrate S so as to expose them.
The size of UB2 is limited inside the lower substrate SUB1. Each of the terminal groups Tg and Td collectively names a plurality of gate terminals GTM and drain terminals DTM, which will be described later, and their lead wiring portions in units of a tape carrier package TCP on which the integrated circuit chip CHI is mounted. The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is due to the arrangement pitch of the package TCP and each package T
This is for adjusting the terminals DTM and GTM of the display panel PNL to the connection terminal pitch of the CP. The common electrode terminal COT is a terminal for applying a common voltage to the common electrode CT from an external circuit. The counter voltage signal line CL of the matrix portion is drawn out on the opposite side (right side in the figure) of the gate terminal GTM, and the common voltage signal lines are grouped together by a common bus line CB and connected to the common electrode terminal COT.

Along the edge between the transparent glass substrates SUB1 and SUB2, except for the liquid crystal filling opening INJ, the liquid crystal LC
Is formed to form a seal pattern SL.
The sealing material is made of, for example, an epoxy resin.

The layers of the alignment films ORI1 and ORI2 are formed inside the seal pattern SL. Polarizing plates POL1, P
OL2 is formed on the outer surface of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI for setting the direction of liquid crystal molecules.
1 and the upper alignment film ORI2 are sealed in a region partitioned by a seal pattern SL. Lower alignment film ORI1
Is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

FIG. 9 shows a gate signal line GL of the display matrix.
2A and 2B are diagrams showing a connection structure from the external connection terminal GTM to the external connection terminal GTM, wherein FIG. 2A is a plane view, and FIG. 2B is a cross section taken along the line BB of FIG. This figure corresponds to the vicinity of the lower part of FIG. 7, and the diagonal wiring portion is represented by a straight line for convenience.

In the figure, the Cr-Mo layer g3 is hatched for easy understanding.

The gate terminal GTM includes a Cr-Mo layer g3,
Furthermore, the surface is protected and TCP (Tape Carrier Pack
age) and a transparent conductive layer i1 for improving the reliability of the connection with the semiconductor device. The transparent conductive layer i1 uses a transparent conductive film ITO.

In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed therefrom so as to be able to make electrical contact with an external circuit. Has become. Although only one pair of the gate line GL and the gate terminal is shown in the drawing, a plurality of such pairs are arranged vertically to form a terminal group Tg (FIG. 9), and the left end of the gate terminal is In the manufacturing process, the wiring is extended beyond the cutting region of the substrate and short-circuited by the wiring SHg (not shown). This is useful for preventing electrostatic breakdown at the time of rubbing of the alignment film ORI1 in the manufacturing process.

FIGS. 10A and 10B are diagrams showing the connection from the drain signal line DL to its external connection terminal DTM, where FIG. 10A shows the plane and FIG. 10B shows a cross section taken along the line BB of FIG. Show. 7 corresponds to the vicinity of the upper right of FIG. 7 and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end of the substrate SUB1.

TSTD is an inspection terminal to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The external connection drain terminals DTM are vertically arranged. The drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 7 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by a wiring SHd (not shown) to prevent electric breakdown. The inspection terminals TSTD are formed on every other drain signal line DL as shown in FIG.

The drain connection terminal DTM is connected to the transparent conductive layer i1.
And the portion where the protective film PSV1 is removed is connected to the drain signal line DL. This transparent conductive film i
1 uses a transparent conductive film ITO as in the case of the gate terminal GTM.

The lead wiring from the matrix portion to the drain terminal portion DTM has a layer d3 at the same level as the drain signal line DL.

FIGS. 11A and 11B are diagrams showing the connection from the counter voltage signal line CL to its external connection terminal CTM. FIG. 11A is a plan view, and FIG. 11B is a cross section taken along the line BB of FIG. Is shown. This figure corresponds to the vicinity of the upper left of FIG.

Each counter voltage signal line CL is connected to a common bus line C
B1 collectively leads to the common electrode terminal CTM. The common bus line CB1 has a structure in which the conductive layer 3 is laminated on the conductive layer g3, and they are electrically connected by the transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the common voltage is sufficiently supplied from the external circuit to each counter voltage signal line CL. This structure is characterized in that the resistance of the common bus line can be reduced without particularly adding a new conductive layer.

The common electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3. This transparent conductive film i1 is made of a transparent conductive film IT like the other terminals.
O is used. The transparent conductive layer i1 has good durability in order to protect its surface and prevent electrolytic corrosion and the like by the transparent conductive layer i1.
Covers the conductive layer g3. The connection between the transparent conductive layer i1 and the conductive layers g3 and d3 is made conductive by forming through holes in the protective film PSV1 and the insulating film GI.

On the other hand, FIG. 12 is a diagram showing the connection from the other end of the counter voltage signal line CL to the external connection terminal CTM2, (A) showing the plane, and (B) showing (A).
2 shows a cross section taken along line BB of FIG. Note that FIG.
Corresponds to near the upper right. Here, in the common bus line CB2, the other end of each counter voltage signal line CL (gate terminal G)
(TM side) and are led out to the common electrode terminal CTM2. The difference from the common bus line CB1 is that the common bus line CB1 is formed of a conductive layer d3 and a transparent conductive layer i1 so as to be insulated from the gate signal line GL. Further, insulation from the gate signal line GL is performed by the insulating film GI.

FIG. 13 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although this figure is a circuit diagram,
It is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a drain signal line DL,
Subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the gate signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The gate signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the drain signal line X (subscript omitted).
Is connected to the drain signal drive circuit H.

The SUP transmits information for a CRT (cathode ray tube) from a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source or a host (upper processing unit).
This is a circuit including a circuit for exchanging information for an FT liquid crystal display device.

FIG. 6 shows a driving waveform of the liquid crystal display device of this embodiment. The common voltage V _COM is set to a temporally constant potential in order to exhibit the dimensional variation compensation effect of the present invention.

[0153] The gate signal V _G to each scanning period, takes on level, others take off level. The drain signal voltage is applied such that the positive electrode and the negative electrode are inverted for each frame at twice the amplitude of the voltage to be applied to the liquid crystal layer and transmitted to one pixel. Here, the polarity of the drain signal voltage V _D is inverted every column, and the polarity is also inverted every two rows. As a result, a configuration (dot inversion driving) in which the pixels whose polarities are inverted are arranged up and down and left and right is provided, so that flicker and crosstalk (smear) can be suppressed. In addition, the common voltage V _COM is set to a voltage that is reduced by a fixed amount from the center voltage of the polarity inversion of the drain signal voltage.

This is for correcting a feed-through voltage generated when the thin film transistor element changes from on to off, and is performed in order to apply an AC voltage having a small DC component to the liquid crystal (DC is applied to the liquid crystal). And afterimages,
Deterioration etc. will be severe). Next, a manufacturing process of the active matrix type liquid crystal display device according to the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

FIGS. 14 to 16 show each step in the center.
The left side shows a sectional view taken along the line 7-7 in FIG. 1 and the right side shows a sectional view taken along the line 6-6 in FIG.

As shown in FIG. 14 to FIG.
The active matrix type liquid crystal display device according to the present invention is manufactured through a plurality of steps (G) to (G). Excluding the steps (B) and (D), the steps (A) to (G)
Is a section corresponding to each photographic processing, and shows a stage in which the processing after the photographic processing is completed and the photoresist is removed in any cross-sectional view of each process. In the present description, photographic processing refers to a series of operations from application of a photoresist, through selective exposure using a mask, to development thereof.

Step (A) will be described.

In the process (A), as a first step, A
On the lower transparent glass substrate SUB1 made of N635 glass (trade name), a conductive film g3 made of Cr—Mo or the like having a thickness of 2000 ° is provided by sputtering. After the photographic processing for Cr-Mo in the second step, the conductive film g3 is selectively etched with ceric ammonium nitrate. By this step, the gate electrode GT is formed in the TFT portion, and the common electrode CT is formed in the pixel comb electrode portion. Note that, in places not shown, the gate signal line GL and the common voltage signal line C
L, a gate terminal GTM, a first conductive layer of the common bus line CB1, a first conductive layer of the common electrode terminal CTM1, and a bus line Shg connecting the gate terminal GTM are formed.

Step (B) will be described.

In the step (B), an ammonia gas, a silane gas and a nitrogen gas are introduced into a plasma CVD apparatus to provide a 3500 ° -thick Si nitride film, and a silane gas and a hydrogen gas are introduced into the plasma CVD apparatus to form a film. 1200mm thick
After the i-type amorphous Si film is provided, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form a film having a thickness of 300 Å.
N (+) type amorphous Si film is provided.

The step (C) will be described.

In the step (C), after photographic processing for a-Si, an N (+) type amorphous Si film and an i type amorphous Si film are selected by using SF ₆ and CCl 4 as a dry etching gas. By etching, islands of the i-type semiconductor layer AS are formed.

Step (D) will be described.

In the process (D), as a first step,
A conductive film d3 made of Cr having a thickness of 300 ° is provided by sputtering. After a photographic process for Cr-Mo as a second step, the conductive film d3 is etched with the same liquid as in the step (A) as a third step to form a drain signal line D
L, a source electrode SD1 (including a storage capacitor Cstg forming part),
Pixel electrode PX, drain electrode SD2, common bus line C
A first conductive layer of B2 and a bus line SHd (not shown) for short-circuiting the drain terminal DTM are formed (they are patterned by the same photomask and formed collectively).

[0165] Then, by introducing the dry etching apparatus in CCl4, SF ₆ as a fourth step, by etching the N (+) type amorphous Si film, N between the source and the drain (+) type The semiconductor layer d0 is selectively removed. After patterning the conductive film d3 with a mask pattern, the N (+) type semiconductor layer d0 is removed using the conductive film d3 as a mask. That is, in the N (+)-type semiconductor layer d0 remaining on the i-type semiconductor layer AS, portions other than the conductive films d1 and d2 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to completely remove its thickness, the i-type semiconductor layer AS is also slightly etched at its surface, but the degree is controlled by the etching time. do it.

The step (E) will be described.

As a first step of the step (E), an ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to provide a 0.4 μm-thick Si nitride film. After photolithography for SiN as a second step, the protection film PSV1 and the insulating film GI are patterned by selectively etching the Si nitride film using SF ₆ as a dry etching gas as a third step. Here, the protective film PSV1 and the insulating film GI are patterned using the same photomask, and are processed collectively.

FIG. 16 shows the display panel PN shown in FIG.
FIG. 4 is a top view showing a state in which a drain signal driving circuit H and a vertical scanning circuit V are connected to L. CHI is display panel PNL
(The lower five driving IC chips on the vertical scanning circuit side and the left ten driving IC chips on the drain signal driving circuit side). TCP is a tape carrier package on which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), and PCB1 is a driving circuit board on which the above-described TCP and capacitors are mounted. It is divided into two for signal drive circuits. FGP is a frame ground pad, and a spring-like fragment provided by cutting into the shield case SHD is soldered.
FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the figure, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material plated with Sn) are sandwiched and supported by a stripe-shaped polyethylene layer and a polyvinyl alcohol layer.

FIG. 17 is an exploded perspective view showing each component of the liquid crystal display module MDL. SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide, RM is a reflection plate, and BL is a backlight fluorescent tube. , LCA are backlight cases, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module MDL is a shield case SH
The entirety is fixed by claws and hooks provided on D.

The backlight case LCA includes a backlight fluorescent tube BL, a light diffusion plate SPB, a light diffusion plate, a light guide LCB,
The light guide LCB has a shape to accommodate the reflection plate RM.
The light of the backlight fluorescent tube BL arranged on the side surface is made uniform on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and emitted toward the liquid crystal display panel PNL.

An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power supply for the backlight fluorescent tube BL.

As described above, in order to quantitatively measure the display unevenness of the liquid crystal display element constructed in this embodiment, the display surface is set to a CCD camera in a low luminance (10% relative luminance of the maximum luminance) display state where the display unevenness is most noticeable. (After removing the gradual brightness shading over a wide range of the entire display surface that is not recognized as display unevenness), and measuring the contrast of the maximum brightness unevenness is about 2%. No display was observed at all, and a highly uniform display was obtained.

Further, all pixel TFTs of the above liquid crystal display device
The display luminance unevenness when 10% relative luminance of the above-mentioned maximum luminance is displayed by always turning on the gate voltage at or above the threshold value, and the same luminance display on the same entire display surface are temporally performed in the same manner as when the TFT is actually used. Compared to the case where the display is turned on / off, the former display in which the TFT is always on is caused by a dimensional change in the electrode forming step of the TFT substrate (the inspection is performed after disassembly and the T
The unevenness of the display luminance can be visually confirmed by removing the alignment film and the like on the surface of the FT substrate and observing and measuring the variation of the electrode dimensions). Did not.

In the comparison by the above-mentioned measurement with the CCD camera, the contrast of the maximum luminance unevenness of the latter is 3 times larger than that of the former.
It was reduced by 0%.

[0176] (Example 2) Example 1 above, the AC voltage of the common voltage V _COM applied to the common electrode CT, time varying between approximately 2 value in synchronization with the change of the drain signal voltage, further the gate signal V _G other than changing as take approximately 4 value in synchronism with the change of the common voltage in the same manner as in example 1 to create a liquid crystal display device, and the second embodiment.

The above-described gate signal having substantially four values is used for the display unevenness compensating effect due to the electrode dimension variation of the present invention.
In synchronism with the above-mentioned alternating common voltage, either the on-level binary value or the off-level binary value so that the fall width of the gate pulse at the time of TFT off at the time of positive / negative writing becomes substantially the same. Was selected.

Since the maximum amplitude of the drain signal voltage could be reduced by the conversion of the common voltage into an alternating current, a low withstand voltage was used for the drain signal drive circuit (signal side driver).

In the liquid crystal display device according to the second embodiment, when the contrast of the maximum luminance unevenness was measured in the same manner as in the first embodiment, it was about 1%. Even in the visual image quality inspection, no display unevenness was observed, and the uniformity was high. The display was obtained.

As in the case of the first embodiment, all pixels T
When the FT gate voltage is equal to or higher than the threshold value and the display is always on and the relative luminance is displayed at 10% of the maximum luminance, the display luminance unevenness on the entire display surface and the same luminance display on the entire display surface are equal to T.
Compared to the case where the FT is turned on and off temporally in the same manner as in the actual use state, the contrast of the maximum luminance unevenness of the latter is half that of the former in comparison with the measurement by the CCD camera as in the first embodiment. It was reduced below.

[0181] (Comparative Example 1) In the above second embodiment, the gate signal V _G is to take a substantially binary in synchronization with the change of the common voltage only its off level, the on-level positive and
A liquid crystal display device was prepared in the same manner as in Example 2 except that approximately three values were taken as substantially the same value in negative writing, and Comparative Example 1 was obtained.

As in the case of the first embodiment, the display luminance non-uniformity in the case where the gate voltage of all the display screens and all the pixel TFTs is always higher than the threshold value and the relative luminance is displayed at 10% of the maximum luminance is displayed. And the same brightness display on all display surfaces
Compared to the case where the FT was turned on and off temporally in the same manner as in the actual use state, there was almost no visual difference between the two, and in both cases, the display luminance unevenness caused by the dimensional change could be visually confirmed.

Therefore, in the case of the present comparative example using the above-mentioned gate signal having substantially three values, in the low-luminance display where the display unevenness is most conspicuous, the display unevenness compensation effect due to the electrode dimension variation of the present invention is not exhibited. it is conceivable that.

Next, in the same manner as in Example 1, the display surface of the liquid crystal display device according to Comparative Example 1 was imaged with a CCD camera, and the contrast of the maximum luminance unevenness was measured. The color unevenness of the display due to the fluctuation of the thickness difference of the liquid crystal layer was also noticeable visually.

In comparison with the measurement by the CCD camera, the case where all the pixel TFTs are always on and the case where
There was almost no difference in the contrast of the maximum luminance unevenness between the two in the case of the normal drive in which ON / OFF was performed temporally.

Next, the compensation effects of Examples 1 and 2 and Comparative Example 1 will be compared based on the compensation condition (4) used for explaining the operation of the present invention.

Specifically, the compensation condition expression (4) is replaced by the expression (1,
The following equation (the slope α of the luminance-voltage curve) modified with reference to 2)
And the unit one-side retreat amount Δ standardized by the video signal voltage V ′ _SIG
It is evaluated by the transmittance change ΔT per 1).

[0188] _{{1 / (αV 'SIG)} } (ΔT / Δl) = - (1 / l ^ 2) {1+ (ΔC'gs / Ctot)} + {1 / (l Ctot)} (Cgsoff / l s + 2Cgsoff / W + ΔC'gs / ltot) = A + B Here, A and B are defined as follows.

A = − (1 / l ＾ 2) − {ΔC′gs / (l ＾ 2 Ctot)} B = {Cgsoff / (l _s l Ctot)} + {2Cgsoff / (W l
Ctot)｝ + {ΔC′gs / (ltot 1 Ctot)} A and B are contribution components of the effect of the gap variation between the pixel electrodes and the variation of the TFT channel size on the transmittance variation, respectively.

The above and the compensation ratio R defined by R = −B / A
(R = 1 means complete compensation, and minus means that the influence of each variation between pixel electrodes is increased).
Table 1 shows the results calculated using the design parameters of Comparative Example 2 and Comparative Example 1.

Here, the image signal voltage V at the time of common AC driving is
_{For SIG} , V _SIG = (1 / 3-1) which roughly corresponds to a relative transmittance of 10%, which is considered to be most noticeable in luminance unevenness.
/ 2) (V _MAX -V _TH ), ΔC'gs =-(1/4) Cgso
n-Cgsoff was used.

[0192]

[Table 1]

As described in detail in the operation of the present invention from Table 1 above, the first embodiment using the dot inversion drive fixed at the common and the second embodiment using the full common AC drive using the quaternary gate pulse. Are 0.29 and 0.2, respectively.
35, and it is estimated that about 30% of the luminance fluctuation caused by the pixel electrode interval fluctuation is compensated for by the effective driving voltage fluctuation caused by the TFT and the storage capacitance forming portion dimensional fluctuation occurring simultaneously. It turns out that it corresponds well with the result.

On the other hand, in the case of Comparative Example 1 in which common AC drive using a ternary gate pulse, which is usually used in most cases, the above-mentioned effective drive voltage fluctuation has a slightly negative value and the pixel electrode Since the effect of the dimensional variation of the TFT and the storage capacitor forming portion acts in the direction of increasing the luminance variation due to the interval variation, it can be seen that the electrode dimensional variation appears as it is as display luminance unevenness.

[0195]

As described above in detail, according to the present invention, in an active matrix type liquid crystal display device using an in-plane switching method, display unevenness due to variations in electrode dimensions caused by variations caused by an electrode forming process is generated. It is possible to provide an active matrix type liquid crystal display device which has a small number of pixels, has high image quality, and is excellent in mass productivity.

[Brief description of the drawings]

FIG. 1 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix color liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a pixel taken along section line 6-6 in FIG. 1;

FIG. 3 is a sectional view of the thin film transistor element TFT taken along section line 7-7 in FIG. 1;

FIG. 4 is a cross-sectional view of the storage capacitor Cstg taken along section line 8-8 in FIG. 1;

FIG. 5 is an enlarged plan view of a peripheral portion of the thin film transistor TFT shown in FIG. 1;

FIG. 6 is a diagram showing an example of a driving waveform of the active matrix type color liquid crystal display device of the present invention.

FIG. 7 is a plan view illustrating a configuration of a matrix peripheral portion of the display panel.

FIG. 8 is a cross-sectional view showing a panel edge portion without a gate signal terminal on the left side and no external connection terminal on the right side.

FIG. 9 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 10 is a plan view and a sectional view showing the vicinity of a connection portion between a drain terminal DTM and a drain signal line DL.

FIG. 11 shows a common electrode terminal CTM1 and a common bus line C.
FIG. 3 is a plan view and a cross-sectional view showing the vicinity of a connection portion between B1 and a common voltage signal line CL.

FIG. 12 shows common electrode terminals CTM2 and common bus lines C
FIG. 5 is a plan view and a cross-sectional view showing the vicinity of a connection portion between B2 and a common voltage signal line CL.

FIG. 13 is a circuit diagram including a matrix portion and its periphery of the active matrix type color liquid crystal display device of the present invention.

FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 15 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion, showing manufacturing steps of steps D to E on the substrate SUB1 side.

FIG. 16 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.

FIG. 17 is an exploded perspective view of the liquid crystal display module.

FIG. 18 is a diagram showing a relationship among a direction of an applied electric field, a rubbing direction, and a transmission axis of a polarizing plate.

FIG. 19 is a diagram showing an overall configuration of the present invention.

[Explanation of symbols]

SUB: transparent glass substrate, GL: gate signal line, DL ...
Drain signal line, CL: counter voltage signal line, PX: pixel electrode, CT: common electrode, GI: insulating film, GT: gate electrode, AS: i-type semiconductor layer, SD: source electrode or drain electrode, PSV: protective film , BM: light shielding film, LC: liquid crystal,
TFT: thin film transistor, PH: through hole, g,
d: conductive film, Cstg: storage capacity, AOF: anodic oxide film,
AO: Anodizing mask, GTM: Gate terminal, DTM ...
Drain terminal, CB: Common bus line, CTM: Common electrode terminal, SHD: Shield case, PNL: Liquid crystal display panel, SPB: Light diffusion plate, LCB: Light guide, BL: Backlight fluorescent tube, LCA: Backlight case , RM
…reflector.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsuneori Yamamoto 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Makoto Tsumura 7, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1-1 Inside Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Masahiko Ando 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Katsumi Kondo Hitachi, Ibaraki Prefecture 7-1-1, Omikacho Hitachi Research Laboratories Hitachi Research Laboratory, Ltd. (72) Inventor Masahiro Ishii 3300 Hayano Mobara-shi, Chiba Pref.

Claims (11)

[Claims] 1. An active matrix type liquid crystal display device having a plurality of active elements each including a pair of transparent substrates, and a liquid crystal layer sandwiched between the pair of substrates. One of the substrates has a pixel electrode and a common electrode which are extended in the same direction as the signal electrodes on the substrate and arranged in different phases to apply an electric field substantially parallel to the substrate surface to the liquid crystal layer, The pixel electrode has a first connection portion extending in the scanning electrode direction and connected to at least two pixel electrodes, and the common electrode extends in the scanning electrode direction and is connected to a plurality of common electrodes. A second connection portion, wherein the first connection portion and the second connection portion overlap each other to form a capacitance forming portion, wherein the active element size and the finished dimension change of the capacitance forming portion are changed. Pixel electrode or common electrode Electrode size active matrix liquid crystal display device configured to correlate occur finished dimension change of. 2. The active matrix type liquid crystal display device according to claim 1, wherein a direction of an effective drive voltage change caused by a change in the size of the active element and a finished size of the capacitor forming portion is equal to the size of the pixel electrode or the common electrode. An active matrix type liquid crystal display device which works in a direction to compensate for a change in optical characteristics caused by a change in finished dimensions. 3. An active matrix liquid crystal display device having a pair of transparent substrates, a liquid crystal layer sandwiched between the substrates, and a plurality of active elements, wherein one of the pair of substrates is provided. Has a pixel electrode and a common electrode which are extended in the same direction as the signal electrode on the substrate and arranged in different phases to apply an electric field substantially parallel to the substrate surface to the liquid crystal layer, and the pixel electrode is A first connecting portion extending in the scanning electrode direction and connected to at least two pixel electrodes, wherein the common electrode extends in the scanning electrode direction and is connected to a plurality of common electrodes. A connection portion, wherein the first connection portion and the second connection portion overlap each other to form a capacitance forming portion, and the active element and the pixel electrode or the common electrode are patterned by the same photomask; The pixel electrode Alternatively, an active matrix liquid crystal display device in which the electrode potential of the common electrode is always substantially constant. 4. An active matrix liquid crystal display device comprising a pair of transparent substrates, a liquid crystal layer sandwiched between the substrates, and a plurality of active elements, wherein one of the pair of substrates is provided. Has a pixel electrode and a common electrode which are extended in the same direction as the signal electrode on the substrate and arranged in different phases to apply an electric field substantially parallel to the substrate surface to the liquid crystal layer, and the pixel electrode is A first connecting portion extending in the scanning electrode direction and connected to at least two pixel electrodes, wherein the common electrode extends in the scanning electrode direction and is connected to a plurality of common electrodes. A connection portion, wherein the first connection portion and the second connection portion overlap each other to form a capacitance forming portion, and at least one of the pair of substrates includes:
An optical unit that changes optical characteristics according to a molecular alignment state of the liquid crystal layer, wherein the active element and the pixel electrode or the common electrode are formed in the same layer in the substrate surface, and the liquid crystal layer has At least one electrode potential of a pair of electrodes for applying an electric field substantially parallel to the substrate surface temporally changes between substantially two values, and a signal voltage waveform for turning on / off the active element is changed. An active matrix type liquid crystal display device which temporally changes between approximately four values. 5. The active matrix type liquid crystal display device according to claim 4, wherein said active element and said pixel electrode or common electrode are patterned by the same photomask. 6. An active matrix liquid crystal display comprising at least one pair of transparent substrates, a liquid crystal layer sandwiched between the substrates, and a plurality of active elements, wherein one of the pair of substrates is provided. Has a comb-shaped electrode for applying an electric field substantially parallel to the substrate surface to the liquid crystal layer, and a capacitance forming portion formed between some of these electrodes, The active element dimension and the finished dimension of the storage capacitor forming portion are formed so that the finished dimension change of the active element dimension and the capacitance forming section and the finished dimension change of at least one electrode dimension of the comb-teeth electrode occur simultaneously. The direction of the change in the effective drive voltage caused by the change is at least one of the pair of electrodes for applying an electric field substantially parallel to the substrate surface to the liquid crystal layer. An active matrix type liquid crystal display device, which works in a direction to compensate for a change in optical characteristics caused by a change in a finished dimension of an extreme dimension. 7. An active matrix liquid crystal display device comprising a pair of substrates, at least one of which is transparent, a liquid crystal layer sandwiched between said substrates, and a plurality of active elements, wherein one of said pair of substrates is Has a comb-shaped electrode for applying an electric field substantially parallel to the substrate surface to the liquid crystal layer, and a capacitance forming portion formed between some of these electrodes, At least one electrode of the active element and the storage capacitor forming part, and patterning of at least one electrode of the comb-shaped electrode by a photo process are performed by the same photomask, and the liquid crystal layer is substantially parallel to a substrate surface. An active matrix type liquid crystal display device wherein at least one electrode potential of a pair of electrodes for applying an electric field has a substantially constant value at all times. 8. A liquid crystal layer sandwiched between at least one of the substrates, a liquid crystal layer sandwiched between the substrates, and an electric field formed on one of the pair of substrates and substantially parallel to the substrate surface. A plurality of sets of at least one pair of electrodes for applying are provided, a plurality of active elements connected to these electrodes, a storage capacitor connected to these active elements, and at least one of the pair of substrates. An active matrix type liquid crystal display device comprising: an optical unit formed and changing optical characteristics according to a molecular orientation state of the liquid crystal layer, wherein at least one electrode of the active element and the storage capacitor forming part; and the liquid crystal layer At least one electrode of a pair of electrodes for applying an electric field substantially parallel to the substrate surface is formed in the same layer in the substrate surface, and a small number of the electrodes of the pair is formed. At least one electrode potential temporally changes between approximately two values, and a signal voltage waveform for turning on / off the active element temporally changes between approximately four values. Active matrix type liquid crystal display device. 9. The active matrix type liquid crystal display device according to claim 6, wherein an electric field substantially parallel to a substrate surface is applied to at least one electrode of said active element and said storage capacitor forming portion, and said liquid crystal layer. An active matrix type liquid crystal display device, wherein patterning of at least one electrode of a pair of electrodes to be performed by a photo process is performed using the same photomask. 10. The active matrix liquid crystal display device according to claim 6, wherein a change width of a change in optical characteristics over the entire display surface when the same display is performed by all pixels including the plurality of sets of electrodes. However, an active matrix type liquid crystal display device in which the active element is turned on / off temporally and displayed is smaller than when the active element is always turned on and displayed. 11. The active matrix type liquid crystal display device according to claim 6, wherein, when the same display is performed in all pixels including the plurality of sets of electrodes, a change width of a change in optical characteristics over the entire display surface is the active width. An active matrix type liquid crystal display device, wherein a reduction rate when displaying by turning on and off the active element temporally is 20% or more with respect to a case where display is performed with elements always on.