JP2000012696A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein if functional modules to be mounted increase according to a user's required specifications, the wiring load of buses as seen from a bus master module 9 will not easily exceed the ability of a bus driver. SOLUTION: In the semiconductor integrated circuit 10 having a bus master module 20A and a plurality of bus slave modules 20B-20G connected through a bus 11 on a semiconductor substrate, first transfer gates 30B-30G controlled by the bus master module 20A to set on in response to an access to the bus slave modules 20B-20G are provided between the bus 11 and bus slave modules 20B-20G, and those bus slave modules 20B-20G connected to the bus slave modules which the bus master module 20A is to access are set on and others are set off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a technology for distributing a bus load as viewed from the driving side, for example, an ASIC (Application Specific Integrator)
ted Circuits) or CBIC (Cell Based Integrated)
The present invention relates to a technology that is effective when applied to a large-scale integrated circuit designed in the form of circuits (circuits).

[0002]

2. Description of the Related Art In a system called ASIC or CBIC, a specification required by a user is set to a short TAT (Turn Around Ti
This is a design method realized by me), and uses design data of various functional modules registered in a library completed through design and verification in advance. One semiconductor integrated circuit is designed by combining the layout data of such functional modules. A functional module for a building block type CBIC is called, for example, a so-called megacell, and has a relatively large logical scale such as a processor core, a RAM, a ROM, and a DSP. Such functional modules share a bus such as a data bus,
Information will be transmitted.

At this time, if the number of functional modules to be mounted increases, the load component of the bus according to the entire logical scale,
In other words, the parasitic capacitance component of the bus and the wiring resistance increase. This is because the number of bus signal lines is increased and the number of transistors connected to the bus is also increased. If the bus load caused by such wiring capacity exceeds the bus drive capability of the driver of the functional module, the high-speed signal transmission via the bus is impaired, and the signal transmission waveform is deteriorated. A malfunction may occur.

In order to cope with such a situation, the bus driver of the functional module is changed to one having a high driving capability.
Alternatively, it is conceivable to reduce the number of functional modules sharing an individual signal line, thereby distributing the allocation of the functional modules to the signal lines, and reducing the wiring load itself.

[0005]

However, when using the layout data of various functional modules registered in the library, it is not easy to partially change the configuration of the functional modules. For this reason, when the number of mounted functional modules increases according to the user's requirement and the wiring resistance and parasitic capacitance of the bus exceed the capability of the bus driver, in order to meet the user's requirement, Connections between functional modules must be determined to distribute the allocation. Depending on the required specifications, this cannot be dealt with even after all, and in some cases, re-layout in the functional module may be required.

An object of the present invention is to provide a semiconductor integrated circuit in which the bus wiring resistance and the parasitic capacitance seen from the bus master module do not easily exceed the capability of the bus driver even if the number of functional modules mounted according to the specification required by the user increases. It is to provide a circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a bus master module (20A) and a plurality of bus slave modules (2
0B to 20G) connected by a bus (11), and between the bus and the bus slave module, is controlled to be in an on state in response to access of the bus slave module by the bus master module. First transfer gates (30B to 30G) are provided. The first transfer gate that is connected to the bus slave module to be accessed by the bus master module is turned on, and the others are turned off. Thus, the wiring load seen from the bus master module is reduced by the amount of the bus slave module from the first transfer gate in the off state. Therefore, even if the number of functional modules mounted according to the specification required by the user increases, the bus wiring resistance and the parasitic capacitance viewed from the bus master module do not easily exceed the capability of the bus driver. To address the user's requirements,
There is no need to change the design or re-layout of the functional module.

When the bus master module directly outputs a module select signal, the first transfer gate can input a module select signal for a corresponding bus slave module as a switch control signal.

If the bus master module does not directly output a module select signal, decoding means (12) for decoding an address signal output from the bus master module and outputting a module select signal to the bus slave module is provided. The first transfer gate can receive a module select signal for the corresponding bus slave module as a switch control signal.

In order to further reduce the wiring load of the bus as viewed from the bus master module, second buses are provided on both sides of the bus with the connection node (N1) between the bus and the bus master module interposed therebetween.
Transfer gates (32A, 32B). The bus master module is connected to the bus slave module via a path selected by the first and second transfer gates.

In a specific embodiment, the bus master module is a processor core module (20A) including a CPU (21A), and the bus slave module is a peripheral circuit module (20B to 20G) accessed by the processor core module. Accordingly, the semiconductor integrated circuit can be realized as a microcomputer or a data processor designed in the CBIC or ASIC format.

[0014]

FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 10 shown in FIG. 1 is not particularly limited, but includes one bus master module 20A and six bus slave modules 20B to 20B.
20G shares the bus 11 and is configured as one semiconductor chip made of single crystal silicon or the like. Bus master module 20A and bus slave module 20
Although not particularly limited, B to 20G are functional modules such as megacells, and are circuits formed based on mask pattern data on which logic design, circuit design, and layout design have been completed. Megacell mask pattern data has already been registered in the library, and is selected from the library and used according to the specifications required by the user. Therefore, in the design method of CBIC and ASIC aiming at shortening the TAT, the internal circuit or layout pattern of the bus master module 20A and the bus slave modules 20B to 20G selected according to the specification required by the user should be used without being changed in principle. Is common, and that is the best.

When the semiconductor integrated circuit 10 is a data processor or a microcomputer, the bus master module 20A includes a processor core module including a CPU 21A and the like, and bus slave modules 20B to 20C.
20G is a DSP (Digital Signal Processor), RA
M (Random Access Memory), ROM (Read only Memo)
ry), A / D (Analog to Digital Converter), D /
A (Digital to Analog Converter), timer counter,
It can be a peripheral circuit module such as a general-purpose input / output port circuit.

The bus 11 and the bus slave module 2
0B to 20G, first transfer gates 30B to 30G that are turned on in response to the access of the bus slave modules 20B to 20G by the bus master module 20A are provided. The bus 11
Is a general term for an address bus, a data bus, and a control bus. Accordingly, although the transfer gates 30B to 30G are illustrated as one MOS switch, they are actually provided with a bus switch for each signal line.

The bus master module 20A directly outputs module select signals MSN1 to MSN6. The module select signals MSN1 to MSN6 are transmitted to the corresponding bus slave modules 20B to 20G and the transfer gate 3 via the individual signal lines 31B to 31G.
0B to 30G. The transfer gate 3
0B to 30G are module select signals MSN1 to MSN
N6 is input as a switch control signal.

As a result, the transfer gates 30B-
In 30G, the one corresponding to the bus slave module to be accessed by the bus master module 20A is turned on, and the others are turned off. Therefore, the wiring load seen from the bus master module 20A is reduced by the wiring path from the transfer gate in the off state to the bus slave module. Therefore, even if the number of function modules mounted according to the specification required by the user increases, the wiring resistance and the parasitic capacitance of the bus viewed from the bus master module 20A do not easily exceed the capability of the bus driver. In order to cope with the specification required by the user, it is not necessary to change the design or re-layout of the functional module. The bus driver means a final output stage circuit to the bus in the bus master module and the bus slave module, for example, a circuit such as an output buffer.

FIG. 2 shows a calculation model (simulation model) of a signal transmission delay time between functional modules. In FIG. 2, a target cell is a model of a bus driver of a driving-side functional module, a target net is a model of a wiring load of a signal transmission path, and a next-stage cell is a driven-side input first-stage circuit. The time required for signal transmission between the functional blocks, that is, the time required for signal transmission from the target cell to the next cell according to FIG.
ts (time until signal change input to the target cell is determined, that is, delay time for the slope), ti (internal operation delay time until output of the target cell is determined), tc (target net wiring) It can be estimated by the total time of the capacitance or the parasitic capacitance delay time) and tl (the delay time due to the wiring resistance). The delay time tc increases as the number of mounted functional modules such as a bus slave module increases. This is because the input capacitance represented by the input capacitance of the next cell increases,
This is because the wiring amount increases. When the transfer gates 30B to 30G are interposed as shown in FIG.
If it is off, the bus master module 2
For 0A, the wiring load from the transfer gate to the next cell in the preceding stage becomes invisible. For example, as illustrated in FIG. 3, the wiring load seen from the bus master module 20 </ b> A in a state where all the transfer gates 30 </ b> B to 30 </ b> G are turned off is limited to a portion that enters the hatched area 40. When the bus master module 20A accesses the bus slave module, only the wiring load from the transfer gate which is turned on to the access target module is added. When the transfer gates 30B to 30G are not provided, as apparent from FIG. 4, the wiring load of the bus 11 seen from the bus master module 20A becomes larger than that in FIG.

FIG. 5 shows a second example of the semiconductor integrated circuit according to the present invention. The difference from FIG. 1 is that an address decoder 12 for decoding an address signal output from the bus master module 20A and outputting module select signals MSN1 to MSN6 to the bus slave modules 20B to 20G is provided, and the transfer gate 30B
The difference is that module select signals MSN1 to MSN6 for the corresponding bus slave modules are supplied as switch control signals to .about.30G. Other configurations are the same as those in FIG. 1, and a detailed description is omitted. The address signal supplied to the address decoder 12 can be, for example, upper three bits of a physical address signal corresponding to the address signal generated by the CPU 21A. The configuration in FIG. 5 is optimal when a processor core module having no function of directly outputting a module selection signal is employed.

FIG. 6 shows a third example of the semiconductor integrated circuit according to the present invention. The difference from FIG. 1 is that the bus 11 can be driven by dividing the bus 11 into two parts starting from the bus master module 20A. That is, the bus 1
The second transfer gate 32 is provided on both sides of the bus 11 with the connection node N1 between
A, 32B are interposed. Bus master module 20A
Turns on the transfer gate 32A when accessing the bus slave modules 20B, 20D and 20E, and turns on the transfer gate 32B when accessing the bus slave modules 20C, 20F and 20G. The switch control signal CTLA (CTLB) of the transfer gate 32A (32B) is a logical sum signal of the module select signals MSN2, MSN5, and MSN6 (logical sum signal of the module select signals MSN1, MSN3, and MSN4). The switch control signals CTLA, CTL
B may be generated outside the bus master module 20A using the module selection signal. At this time, the module selection signal may be generated by the address decoder of FIG.

If the configuration of FIG. 6 is adopted, the wiring load to be driven by the bus master module 20A only needs to include one of the hatched areas 42A and 42B of FIG. Therefore, the wiring load seen from the bus master module 20A can be further reduced by half as compared with the case of FIG.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto, and various changes can be made without departing from the gist of the invention. No.

For example, the type of the functional module is not limited to the above description and can be changed as appropriate. Further, in the above description, one bus master module is used to facilitate understanding of the contents.
The present invention is also applicable to a case where a plurality of bus master modules are provided, such as a y Access Controller module and a processor core module. For example, the switch control of the corresponding transfer gate may be performed by taking the logical sum of the module selection signal from each bus master module supplied to each bus slave module.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer or a data processor which is a utilization field as the background has been described.
It goes without saying that the present invention can be applied to a semiconductor integrated circuit called SI.

[0026]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, between the bus and the bus slave module, the second bus is controlled to be turned on in response to the access of the bus slave module by the bus master module.
Since one transfer gate is provided, the wiring load as seen from the bus master module is reduced by the amount of the bus slave module from the first transfer gate in the off state, thereby increasing the number of function modules mounted according to the specification required by the user. However, the bus wiring resistance and the parasitic capacitance viewed from the bus master module do not easily exceed the capability of the bus driver. In order to cope with the specification required by the user, it is not necessary to change the design of the functional module, re-layout or the like.

A second transfer gate is interposed on both sides of the bus with a connection node between the bus and the bus master module interposed therebetween, and the bus master module is connected to the bus slave mode via a path selected by the first and second transfer gates. By connecting to the bus module, the wiring load of the bus viewed from the bus master module can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is an explanatory diagram showing a calculation model (simulation model) of a signal transmission delay time between functional modules.

FIG. 3 is an explanatory view exemplarily showing a wiring load seen from a bus master module in the configuration of FIG. 1;

FIG. 4 is an explanatory diagram exemplarily showing a wiring load of a bus seen from a bus master module when a transfer gate is not provided.

FIG. 5 is a block diagram showing a configuration in which a module selection signal is generated by an address decoder as a second example of the semiconductor integrated circuit according to the present invention.

FIG. 6 is a block diagram showing, as a third example of the semiconductor integrated circuit according to the present invention, a configuration in which the bus wiring load seen from the bus master module is further reduced.

[Explanation of symbols]

Reference Signs List 10 semiconductor integrated circuit 11 bus 12 address decoder 20A bus master module (processor core module) 21A CPU 20B-20G bus slave module (peripheral circuit module) 30B-30G first transfer gate 32A, 32B second transfer gate MSN1-MSN6 module Select signal

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (5)

[Claims] 1. A semiconductor integrated circuit formed by connecting a bus master module and a plurality of bus slave modules to a semiconductor substrate by a bus, wherein a bus master module includes a bus master module between the bus and the bus slave module. A semiconductor integrated circuit comprising a first transfer gate controlled to be turned on in response to an access. 2. The semiconductor according to claim 1, wherein said bus master module outputs a module select signal, and said first transfer gate inputs a module select signal for a corresponding bus slave module as a switch control signal. Integrated circuit. 3. The bus transfer module according to claim 1, further comprising decoding means for decoding an address signal output by said bus master module and outputting a module select signal to said bus slave module, wherein said first transfer gate is a module for a corresponding bus slave module. 2. The semiconductor integrated circuit according to claim 1, wherein the select signal is input as a switch control signal. 4. A second transfer gate is interposed on both sides of the bus with a connection node between the bus and the bus master module interposed therebetween, and the bus master module comprises first and second transfer gates.
4. The semiconductor integrated circuit according to claim 2, wherein said semiconductor integrated circuit is connected to a bus slave module via a path selected by said transfer gate. 5. The bus master module is a processor core module including a CPU, and the bus slave module is a peripheral circuit module accessed by the processor core module, and is formed as a microcomputer. 5. The semiconductor integrated circuit according to claim 4.