ITMI971471A0 - - Google Patents
Info
- Publication number
- ITMI971471A0 ITMI971471A0 ITMI971471A ITMI971471A ITMI971471A0 IT MI971471 A0 ITMI971471 A0 IT MI971471A0 IT MI971471 A ITMI971471 A IT MI971471A IT MI971471 A ITMI971471 A IT MI971471A IT MI971471 A0 ITMI971471 A0 IT MI971471A0
- Authority
- IT
- Italy
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Nonlinear Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97MI001471A IT1292392B1 (it) | 1997-06-20 | 1997-06-20 | Metodo per realizzare alberi di temporizzazione in circuiti elettronici digitali sincroni e relativo stadio tampone buffer |
| US09/096,919 US6373288B1 (en) | 1997-06-20 | 1998-06-12 | Method of implementing clock trees in synchronous digital electronic circuits, and a programmable delay buffer stage therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97MI001471A IT1292392B1 (it) | 1997-06-20 | 1997-06-20 | Metodo per realizzare alberi di temporizzazione in circuiti elettronici digitali sincroni e relativo stadio tampone buffer |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI971471A0 true ITMI971471A0 (US06559137-20030506-C00071.png) | 1997-06-20 |
| ITMI971471A1 ITMI971471A1 (it) | 1998-12-20 |
| IT1292392B1 IT1292392B1 (it) | 1999-02-08 |
Family
ID=11377408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT97MI001471A IT1292392B1 (it) | 1997-06-20 | 1997-06-20 | Metodo per realizzare alberi di temporizzazione in circuiti elettronici digitali sincroni e relativo stadio tampone buffer |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6373288B1 (US06559137-20030506-C00071.png) |
| IT (1) | IT1292392B1 (US06559137-20030506-C00071.png) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6703869B2 (en) * | 2002-06-05 | 2004-03-09 | Agilent Technologies, Inc. | Method and apparatus for low latency distribution of logic signals |
| DE10227618B4 (de) * | 2002-06-20 | 2007-02-01 | Infineon Technologies Ag | Logikschaltung |
| US6952813B1 (en) * | 2003-07-30 | 2005-10-04 | Xilinx, Inc. | Method and apparatus for selecting programmable interconnects to reduce clock skew |
| KR100892684B1 (ko) * | 2007-11-09 | 2009-04-15 | 주식회사 하이닉스반도체 | 데이터 센터 트랙킹 회로 및 이를 포함하는 반도체 집적회로 |
| CN116911248B (zh) * | 2023-07-28 | 2024-08-09 | 珠海凌烟阁芯片科技有限公司 | 一种反向时钟树的实现方法及反向时钟树结构 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5376842A (en) * | 1991-12-20 | 1994-12-27 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit with reduced clock skew and divided power supply lines |
| US5831459A (en) * | 1995-11-13 | 1998-11-03 | International Business Machines Corporation | Method and system for adjusting a clock signal within electronic circuitry |
-
1997
- 1997-06-20 IT IT97MI001471A patent/IT1292392B1/it active IP Right Grant
-
1998
- 1998-06-12 US US09/096,919 patent/US6373288B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6373288B1 (en) | 2002-04-16 |
| ITMI971471A1 (it) | 1998-12-20 |
| IT1292392B1 (it) | 1999-02-08 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted |