IT9020803A0 - Metodo di scrittura a lampo per testare una ram - Google Patents
Metodo di scrittura a lampo per testare una ramInfo
- Publication number
- IT9020803A0 IT9020803A0 IT9020803A IT2080390A IT9020803A0 IT 9020803 A0 IT9020803 A0 IT 9020803A0 IT 9020803 A IT9020803 A IT 9020803A IT 2080390 A IT2080390 A IT 2080390A IT 9020803 A0 IT9020803 A0 IT 9020803A0
- Authority
- IT
- Italy
- Prior art keywords
- ram
- test
- write method
- flash write
- flash
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890016775A KR920007909B1 (ko) | 1989-11-18 | 1989-11-18 | 램 테스트시 고속 기록방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| IT9020803A0 true IT9020803A0 (it) | 1990-06-28 |
| IT9020803A1 IT9020803A1 (it) | 1991-12-29 |
| IT1287696B1 IT1287696B1 (it) | 1998-08-07 |
Family
ID=19291793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT02080390A IT1287696B1 (it) | 1989-11-18 | 1990-06-28 | Metodo di scrittura a lampo per testare una ram |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5046049A (it) |
| JP (1) | JP2585831B2 (it) |
| KR (1) | KR920007909B1 (it) |
| CN (1) | CN1018401B (it) |
| DE (1) | DE4010292A1 (it) |
| FR (1) | FR2654865B1 (it) |
| GB (1) | GB2238638B (it) |
| IT (1) | IT1287696B1 (it) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2673395B2 (ja) * | 1990-08-29 | 1997-11-05 | 三菱電機株式会社 | 半導体記憶装置およびそのテスト方法 |
| JP2704041B2 (ja) * | 1990-11-09 | 1998-01-26 | 日本電気アイシーマイコンシステム株式会社 | 半導体メモリ装置 |
| US5241500A (en) * | 1992-07-29 | 1993-08-31 | International Business Machines Corporation | Method for setting test voltages in a flash write mode |
| US5424988A (en) * | 1992-09-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Stress test for memory arrays in integrated circuits |
| US5319606A (en) * | 1992-12-14 | 1994-06-07 | International Business Machines Corporation | Blocked flash write in dynamic RAM devices |
| US5452405A (en) * | 1993-01-25 | 1995-09-19 | Hewlett-Packard Company | Method and apparatus for delta row decompression |
| US5488691A (en) * | 1993-11-17 | 1996-01-30 | International Business Machines Corporation | Memory card, computer system and method of operation for differentiating the use of read-modify-write cycles in operating and initializaiton modes |
| US5452429A (en) * | 1993-11-17 | 1995-09-19 | International Business Machines Corporation | Error correction code on add-on cards for writing portions of data words |
| DE10245713B4 (de) * | 2002-10-01 | 2004-10-28 | Infineon Technologies Ag | Testsystem und Verfahren zum Testen von Speicherschaltungen |
| CN100343923C (zh) * | 2003-01-28 | 2007-10-17 | 华为技术有限公司 | 一种测试sdram器件的方法 |
| JP5125028B2 (ja) * | 2006-08-18 | 2013-01-23 | 富士通セミコンダクター株式会社 | 集積回路 |
| KR200488043Y1 (ko) * | 2018-08-30 | 2018-12-06 | 오영동 | 차량의 클리닝 장치 |
| CN109448771B (zh) * | 2018-12-25 | 2023-08-15 | 北京时代全芯存储技术股份有限公司 | 记忆体装置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58139399A (ja) * | 1982-02-15 | 1983-08-18 | Hitachi Ltd | 半導体記憶装置 |
| JPH0666436B2 (ja) * | 1983-04-15 | 1994-08-24 | 株式会社日立製作所 | 半導体集積回路装置 |
| JPS60115099A (ja) * | 1983-11-25 | 1985-06-21 | Fujitsu Ltd | 半導体記憶装置 |
| US4661930A (en) * | 1984-08-02 | 1987-04-28 | Texas Instruments Incorporated | High speed testing of integrated circuit |
| JPS61202400A (ja) * | 1985-03-05 | 1986-09-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS6446300A (en) * | 1987-08-17 | 1989-02-20 | Nippon Telegraph & Telephone | Semiconductor memory |
| JPS63104296A (ja) * | 1986-10-21 | 1988-05-09 | Nec Corp | 半導体記憶装置 |
| JP2609211B2 (ja) * | 1987-03-16 | 1997-05-14 | シーメンス・アクチエンゲゼルシヤフト | メモリセルの検査回路装置および方法 |
| JP2610598B2 (ja) * | 1987-03-16 | 1997-05-14 | シーメンス・アクチエンゲゼルシヤフト | 半導体メモリへのデータの並列書込み回路装置 |
| JPS643893A (en) * | 1987-06-25 | 1989-01-09 | Nec Corp | Semiconductor storage device |
| US5051995A (en) * | 1988-03-14 | 1991-09-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a test mode setting circuit |
-
1989
- 1989-11-18 KR KR1019890016775A patent/KR920007909B1/ko not_active IP Right Cessation
-
1990
- 1990-03-20 US US07/496,517 patent/US5046049A/en not_active Expired - Lifetime
- 1990-03-29 JP JP2079039A patent/JP2585831B2/ja not_active Expired - Lifetime
- 1990-03-30 DE DE4010292A patent/DE4010292A1/de not_active Ceased
- 1990-03-30 FR FR9004087A patent/FR2654865B1/fr not_active Expired - Lifetime
- 1990-03-30 GB GB9007255A patent/GB2238638B/en not_active Expired - Lifetime
- 1990-06-20 CN CN90104919A patent/CN1018401B/zh not_active Expired
- 1990-06-28 IT IT02080390A patent/IT1287696B1/it active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| FR2654865A1 (fr) | 1991-05-24 |
| FR2654865B1 (fr) | 1994-10-28 |
| DE4010292A1 (de) | 1991-05-23 |
| JPH03168999A (ja) | 1991-07-22 |
| CN1052209A (zh) | 1991-06-12 |
| IT9020803A1 (it) | 1991-12-29 |
| GB2238638A (en) | 1991-06-05 |
| JP2585831B2 (ja) | 1997-02-26 |
| IT1287696B1 (it) | 1998-08-07 |
| US5046049A (en) | 1991-09-03 |
| CN1018401B (zh) | 1992-09-23 |
| KR920007909B1 (ko) | 1992-09-19 |
| KR910010530A (ko) | 1991-06-29 |
| GB2238638B (en) | 1994-08-03 |
| GB9007255D0 (en) | 1990-05-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970730 |