IT8523295A0 - Metodo ed apparecchio per piastrina di combinazione per modulazione di codice di impulso avente un perfezionato circuito di autoazzeramento. - Google Patents

Metodo ed apparecchio per piastrina di combinazione per modulazione di codice di impulso avente un perfezionato circuito di autoazzeramento.

Info

Publication number
IT8523295A0
IT8523295A0 IT8523295A IT2329585A IT8523295A0 IT 8523295 A0 IT8523295 A0 IT 8523295A0 IT 8523295 A IT8523295 A IT 8523295A IT 2329585 A IT2329585 A IT 2329585A IT 8523295 A0 IT8523295 A0 IT 8523295A0
Authority
IT
Italy
Prior art keywords
pulse code
code modulation
combination plate
zeroing circuit
improved auto
Prior art date
Application number
IT8523295A
Other languages
English (en)
Other versions
IT1186477B (it
Inventor
Pierangelo Confalonieri
Daniel Senderowicz
Augusto Tirelli
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT23295/85A priority Critical patent/IT1186477B/it
Publication of IT8523295A0 publication Critical patent/IT8523295A0/it
Priority to US06/936,369 priority patent/US4805192A/en
Priority to GB8628794A priority patent/GB2184906B/en
Priority to DE3643160A priority patent/DE3643160C2/de
Priority to FR868617902A priority patent/FR2592257B1/fr
Priority to JP61301869A priority patent/JPS62157423A/ja
Application granted granted Critical
Publication of IT1186477B publication Critical patent/IT1186477B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
    • H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation
    • H03M1/825—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation by comparing the input signal with a digital ramp signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Networks Using Active Elements (AREA)
  • Manipulation Of Pulses (AREA)
IT23295/85A 1985-12-19 1985-12-19 Metodo ed apparecchio per piastrina di combinazione per modulazione di codile di impulso avente un perfezionato circuito di autoazzeramento IT1186477B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT23295/85A IT1186477B (it) 1985-12-19 1985-12-19 Metodo ed apparecchio per piastrina di combinazione per modulazione di codile di impulso avente un perfezionato circuito di autoazzeramento
US06/936,369 US4805192A (en) 1985-12-19 1986-12-01 Method and apparatus for pulse code modulation combination chip having an improved autozero circuit
GB8628794A GB2184906B (en) 1985-12-19 1986-12-02 An appartus for correcting an offset signal
DE3643160A DE3643160C2 (de) 1985-12-19 1986-12-17 Nullpunkteinstellung für ein Kombinations-PCM-Chip
FR868617902A FR2592257B1 (fr) 1985-12-19 1986-12-19 Procede et appareil pour pastille de combinaison pour modulation par impulsions codees ayant un circuit perfectionne de remise a zero automatique
JP61301869A JPS62157423A (ja) 1985-12-19 1986-12-19 改良されたオ−トゼロ回路を持つパルス符号変調方法およびその装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT23295/85A IT1186477B (it) 1985-12-19 1985-12-19 Metodo ed apparecchio per piastrina di combinazione per modulazione di codile di impulso avente un perfezionato circuito di autoazzeramento

Publications (2)

Publication Number Publication Date
IT8523295A0 true IT8523295A0 (it) 1985-12-19
IT1186477B IT1186477B (it) 1987-11-26

Family

ID=11205779

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23295/85A IT1186477B (it) 1985-12-19 1985-12-19 Metodo ed apparecchio per piastrina di combinazione per modulazione di codile di impulso avente un perfezionato circuito di autoazzeramento

Country Status (6)

Country Link
US (1) US4805192A (it)
JP (1) JPS62157423A (it)
DE (1) DE3643160C2 (it)
FR (1) FR2592257B1 (it)
GB (1) GB2184906B (it)
IT (1) IT1186477B (it)

Families Citing this family (16)

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Publication number Priority date Publication date Assignee Title
US4965867A (en) * 1987-08-20 1990-10-23 Pioneer Electronic Corporation Offset compensation circuit
US5245340A (en) * 1989-06-27 1993-09-14 Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Communications Digital transmultiplexer with automatic threshold controller
US4951051A (en) * 1989-08-31 1990-08-21 Itt Corporation Overload detector for an analog-to-digital converter
US5523756A (en) * 1994-01-18 1996-06-04 The Grass Valley Group, Inc. Analog-to-digital converter with offset reduction loop
US5483237A (en) * 1994-01-31 1996-01-09 At&T Corp. Method and apparatus for testing a CODEC
US5617473A (en) * 1995-06-23 1997-04-01 Harris Corporation Sign bit integrator and method
US5721547A (en) * 1996-01-04 1998-02-24 Asahi Kasei Microsystems Ltd. Analog-to-digital converter employing DC offset cancellation after modulation and before digital processing
JPH09261199A (ja) * 1996-03-22 1997-10-03 Kenwood Corp 受信装置
FR2754656B1 (fr) * 1996-10-14 1998-12-18 Commissariat Energie Atomique Unite et procede de codage de signal de photodetecteur, a correction de niveau d'entree, et utilisation d'une telle unite pour une gamma-camera
US6028543A (en) * 1997-10-03 2000-02-22 Eg&G Instruments, Inc. Apparatus for improvement of the speed of convergence to sub-least-significant-bit accuracy and precision in a digital signal averager and method of use
US6523233B1 (en) 1999-04-22 2003-02-25 Agere Systems, Inc. Method and apparatus for telephone network impairment detection and compensation in signal transmission between modems
US6239634B1 (en) 1999-05-19 2001-05-29 Parthus Technologies Apparatus and method for ensuring the correct start-up and locking of a delay locked loop
US6262608B1 (en) 1999-05-21 2001-07-17 Parthus Technologies Plc Delay locked loop with immunity to missing clock edges
US7047270B2 (en) * 2002-11-22 2006-05-16 Texas Instruments Incorporated Reporting a saturated counter value
WO2005027349A1 (en) * 2003-09-08 2005-03-24 Infineon Technologies Ag Reset-free delay-locked loop
EP1979996A4 (en) * 2006-02-03 2010-04-28 Videojet Technologies Inc WAVEGUIDE LASER WITH REDUCED SIZE AND / OR REDUCED OPTICAL AXIS DISTORTION

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1113700A (en) * 1966-11-22 1968-05-15 Standard Telephones Cables Ltd Encoders for electrical signals
DE2205792A1 (de) * 1972-02-08 1973-08-16 Bodenseewerk Perkin Elmer Co Schaltungsanordnung fuer den automatischen nullinienabgleich
DE2205793C3 (de) * 1972-02-08 1974-09-12 Bodenseewerk Perkin-Elmer & Co Gmbh, 7770 Ueberlingen Schaltungsanordnung zum Abgleich der Nullinie
FR2171960B1 (it) * 1972-02-17 1978-03-03 Labo Cent Telecommunicat
US3951221A (en) * 1974-09-30 1976-04-20 National Controls, Inc. Computing postal scale
JPS6011849B2 (ja) * 1976-02-10 1985-03-28 日本電気株式会社 オフセツト補償回路
DE2625476C2 (de) * 1976-06-05 1987-04-02 Maatschappij van Berkel's, Patent N.V., Rotterdam Waage mit Auswertegerät zum selbstständigen Justieren der Nullpunktlage der Gewichtswert-Anzeige
FR2396463A1 (fr) * 1977-06-30 1979-01-26 Ibm France Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique
US4193039A (en) * 1978-02-10 1980-03-11 The Valeron Corporation Automatic zeroing system
JPS6014534B2 (ja) * 1979-12-14 1985-04-13 富士通株式会社 オフセット補償方法及び回路
IT7923478A0 (it) * 1979-06-12 1979-06-12 Sits Soc It Telecom Siemens Disposizione circuitale per il collaudo di un convertitore analogico-digitale di un sistema di telecomunicazioni.
US4384278A (en) * 1981-07-22 1983-05-17 Bell Telephone Laboratories, Incorporated One-bit codec with slope overload correction
JPS5885931A (ja) * 1981-11-16 1983-05-23 Matsushita Electric Ind Co Ltd 磁気記録媒体
JPS58120351A (ja) * 1982-01-13 1983-07-18 Fujitsu Ltd 直流ずれ補償方式
JPS59181719A (ja) * 1983-03-31 1984-10-16 Fujitsu Ltd オフセツト補償回路
JPS60197016A (ja) * 1984-03-21 1985-10-05 Toshiba Corp アナログ・デジタル変換回路装置

Also Published As

Publication number Publication date
JPS62157423A (ja) 1987-07-13
FR2592257B1 (fr) 1992-02-14
FR2592257A1 (fr) 1987-06-26
US4805192A (en) 1989-02-14
GB2184906B (en) 1989-11-29
GB8628794D0 (en) 1987-01-07
DE3643160C2 (de) 1996-02-01
DE3643160A1 (de) 1987-06-25
GB2184906A (en) 1987-07-01
IT1186477B (it) 1987-11-26

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227