IT7923796A0 - Struttura dielettrica a piu' strati per il montaggio di circuiti integrati. - Google Patents
Struttura dielettrica a piu' strati per il montaggio di circuiti integrati.Info
- Publication number
- IT7923796A0 IT7923796A0 IT7923796A IT2379679A IT7923796A0 IT 7923796 A0 IT7923796 A0 IT 7923796A0 IT 7923796 A IT7923796 A IT 7923796A IT 2379679 A IT2379679 A IT 2379679A IT 7923796 A0 IT7923796 A0 IT 7923796A0
- Authority
- IT
- Italy
- Prior art keywords
- assembly
- integrated circuits
- dielectric structure
- layer dielectric
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Waveguides (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/918,214 US4193082A (en) | 1978-06-23 | 1978-06-23 | Multi-layer dielectric structure |
| US05/918,213 US4202007A (en) | 1978-06-23 | 1978-06-23 | Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IT7923796A0 true IT7923796A0 (it) | 1979-06-22 |
| IT1162549B IT1162549B (it) | 1987-04-01 |
Family
ID=27129747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT23796/79A IT1162549B (it) | 1978-06-23 | 1979-06-22 | Struttura dielettrica a piu' strati per il montaggio di circuiti integrati |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0006444B1 (it) |
| DE (1) | DE2964342D1 (it) |
| IT (1) | IT1162549B (it) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818951A (ja) * | 1981-07-22 | 1983-02-03 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 半導体チツプ装着用基板 |
| US4472876A (en) * | 1981-08-13 | 1984-09-25 | Minnesota Mining And Manufacturing Company | Area-bonding tape |
| US4489364A (en) * | 1981-12-31 | 1984-12-18 | International Business Machines Corporation | Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface |
| US4535388A (en) * | 1984-06-29 | 1985-08-13 | International Business Machines Corporation | High density wired module |
| GB2168857A (en) * | 1984-11-14 | 1986-06-25 | Int Standard Electric Corp | Method and structure for interconnecting high frequency components |
| JP2592308B2 (ja) * | 1988-09-30 | 1997-03-19 | 株式会社日立製作所 | 半導体パッケージ及びそれを用いたコンピュータ |
| US5055973A (en) * | 1990-01-17 | 1991-10-08 | Aptix Corporation | Custom tooled printed circuit board |
| KR101155557B1 (ko) * | 2010-11-19 | 2012-06-19 | 한국철도기술연구원 | 내마모성이 개선된 절연재를 채용한 절연구분장치 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3456158A (en) * | 1963-08-08 | 1969-07-15 | Ibm | Functional components |
| US3518756A (en) * | 1967-08-22 | 1970-07-07 | Ibm | Fabrication of multilevel ceramic,microelectronic structures |
| NL7003372A (it) * | 1969-03-11 | 1970-09-15 | ||
| US3726002A (en) * | 1971-08-27 | 1973-04-10 | Ibm | Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate |
| US4037047A (en) * | 1974-12-31 | 1977-07-19 | Martin Marietta Corporation | Multilayer circuit board with integral flexible appendages |
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
| DE2742534C2 (de) * | 1977-09-21 | 1985-01-24 | Siemens AG, 1000 Berlin und 8000 München | Verbindungselement für elektronische Schaltungen |
-
1979
- 1979-05-22 DE DE7979101564T patent/DE2964342D1/de not_active Expired
- 1979-05-22 EP EP79101564A patent/EP0006444B1/de not_active Expired
- 1979-06-22 IT IT23796/79A patent/IT1162549B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| EP0006444B1 (de) | 1982-12-22 |
| EP0006444A1 (de) | 1980-01-09 |
| DE2964342D1 (en) | 1983-01-27 |
| IT1162549B (it) | 1987-04-01 |
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