IT1042658B - Procedimento per fabbricare circuiti elettrici integrati - Google Patents
Procedimento per fabbricare circuiti elettrici integratiInfo
- Publication number
- IT1042658B IT1042658B IT27373/75A IT2737375A IT1042658B IT 1042658 B IT1042658 B IT 1042658B IT 27373/75 A IT27373/75 A IT 27373/75A IT 2737375 A IT2737375 A IT 2737375A IT 1042658 B IT1042658 B IT 1042658B
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- electric circuits
- integrated electric
- manufacturing integrated
- manufacturing
- Prior art date
Links
Classifications
-
- H10W74/43—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H10P95/00—
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742445594 DE2445594A1 (de) | 1974-09-24 | 1974-09-24 | Verfahren zur herstellung integrierter schaltungen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT1042658B true IT1042658B (it) | 1980-01-30 |
Family
ID=5926596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT27373/75A IT1042658B (it) | 1974-09-24 | 1975-09-18 | Procedimento per fabbricare circuiti elettrici integrati |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5160175A (index.php) |
| DE (1) | DE2445594A1 (index.php) |
| FR (1) | FR2286504A1 (index.php) |
| GB (1) | GB1514288A (index.php) |
| IT (1) | IT1042658B (index.php) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3218309A1 (de) * | 1982-05-14 | 1983-11-17 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von integrierten mos-feldeffekttransistoren mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2040180B2 (de) * | 1970-01-22 | 1977-08-25 | Intel Corp, Mountain View, Calif. (V.St.A.) | Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht |
| US3833919A (en) * | 1972-10-12 | 1974-09-03 | Ncr | Multilevel conductor structure and method |
-
1974
- 1974-09-24 DE DE19742445594 patent/DE2445594A1/de active Pending
-
1975
- 1975-08-28 GB GB35464/75A patent/GB1514288A/en not_active Expired
- 1975-09-18 IT IT27373/75A patent/IT1042658B/it active
- 1975-09-22 FR FR7528930A patent/FR2286504A1/fr active Granted
- 1975-09-25 JP JP50115926A patent/JPS5160175A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2286504A1 (fr) | 1976-04-23 |
| FR2286504B1 (index.php) | 1978-04-07 |
| JPS5160175A (index.php) | 1976-05-25 |
| DE2445594A1 (de) | 1976-04-08 |
| GB1514288A (en) | 1978-06-14 |
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