IN2013CH05594A - - Google Patents

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Publication number
IN2013CH05594A
IN2013CH05594A IN5594CH2013A IN2013CH05594A IN 2013CH05594 A IN2013CH05594 A IN 2013CH05594A IN 5594CH2013 A IN5594CH2013 A IN 5594CH2013A IN 2013CH05594 A IN2013CH05594 A IN 2013CH05594A
Authority
IN
India
Prior art keywords
transistor
charge
rate
adjust
injection pull
Prior art date
Application number
Inventor
Goel Ankur
Kumar Rai Dharmendra
Bhusan Sahoo Biswa
Original Assignee
Lsi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Corp filed Critical Lsi Corp
Priority to IN5594CH2013 priority Critical patent/IN2013CH05594A/en
Priority to US14/510,190 priority patent/US9424900B2/en
Publication of IN2013CH05594A publication Critical patent/IN2013CH05594A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/227—Timing of memory operations based on dummy memory elements or replica circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Abstract

In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations.
IN5594CH2013 2013-12-04 2013-12-04 IN2013CH05594A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN5594CH2013 IN2013CH05594A (en) 2013-12-04 2013-12-04
US14/510,190 US9424900B2 (en) 2013-12-04 2014-10-09 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN5594CH2013 IN2013CH05594A (en) 2013-12-04 2013-12-04

Publications (1)

Publication Number Publication Date
IN2013CH05594A true IN2013CH05594A (en) 2015-06-12

Family

ID=54199414

Family Applications (1)

Application Number Title Priority Date Filing Date
IN5594CH2013 IN2013CH05594A (en) 2013-12-04 2013-12-04

Country Status (2)

Country Link
US (1) US9424900B2 (en)
IN (1) IN2013CH05594A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102377453B1 (en) * 2015-11-05 2022-03-23 삼성전자주식회사 Nonvolatile memory device and operating method thereof
US10580479B2 (en) * 2018-06-26 2020-03-03 Mediatek Singapore Pte. Ltd. Self-time scheme for optimizing performance and power in dual rail power supplies memories
US11362627B1 (en) * 2021-06-15 2022-06-14 Micron Technology, Inc. Process tracking pulse generator
CN113746455B (en) * 2021-09-14 2024-03-12 北京欧铼德微电子技术有限公司 Ring oscillator

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100278663B1 (en) * 1998-12-18 2001-02-01 윤종용 Bias Circuit of Semiconductor Integrated Circuits
US6198670B1 (en) * 1999-06-22 2001-03-06 Micron Technology, Inc. Bias generator for a four transistor load less memory cell
KR20120059991A (en) * 2010-12-01 2012-06-11 삼성전자주식회사 Memory device, test operation method thereof, and system having the same

Also Published As

Publication number Publication date
US20150155021A1 (en) 2015-06-04
US9424900B2 (en) 2016-08-23

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