IN2013CH04579A - - Google Patents

Info

Publication number
IN2013CH04579A
IN2013CH04579A IN4579CH2013A IN2013CH04579A IN 2013CH04579 A IN2013CH04579 A IN 2013CH04579A IN 4579CH2013 A IN4579CH2013 A IN 4579CH2013A IN 2013CH04579 A IN2013CH04579 A IN 2013CH04579A
Authority
IN
India
Prior art keywords
clock
suspension
emulator
signal
design
Prior art date
Application number
Inventor
Suresh Krishnamurthy
Kumar Agarwal Satish
Jain Amit
Gupta Sanjay
W Selvidge Charles
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Priority to IN4579CH2013 priority Critical patent/IN2013CH04579A/en
Priority to US14/087,531 priority patent/US9165099B2/en
Publication of IN2013CH04579A publication Critical patent/IN2013CH04579A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level

Abstract

Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software environment. A clock suspension allowance signal, indicating whether a suspension of design clock signals is permitted considering dynamic targets in the emulator, is generated based on slack information related to one or more clock signals associated with one or more dynamic targets of the emulator. Based on the clock suspension request signal and the clock suspension allowance signal, a clock suspension signal is generated for enabling temporary design clock suspensions.
IN4579CH2013 2013-10-09 2013-10-09 IN2013CH04579A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN4579CH2013 IN2013CH04579A (en) 2013-10-09 2013-10-09
US14/087,531 US9165099B2 (en) 2013-10-09 2013-11-22 Adaptive clock management in emulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN4579CH2013 IN2013CH04579A (en) 2013-10-09 2013-10-09

Publications (1)

Publication Number Publication Date
IN2013CH04579A true IN2013CH04579A (en) 2015-04-10

Family

ID=52778012

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4579CH2013 IN2013CH04579A (en) 2013-10-09 2013-10-09

Country Status (2)

Country Link
US (1) US9165099B2 (en)
IN (1) IN2013CH04579A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7222315B2 (en) * 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis

Also Published As

Publication number Publication date
US9165099B2 (en) 2015-10-20
US20150100931A1 (en) 2015-04-09

Similar Documents

Publication Publication Date Title
BR112015031231A2 (en) environmentally perceptive dialogue policies and response generation
IN2012DN02815A (en)
MX2016005769A (en) Sensor data time alignment.
MX2013007898A (en) Communicating channel state information (csi) of multiple transmission points.
WO2013188364A3 (en) Predicted software usage duration
WO2014140814A3 (en) Proof of presence via tag interactions
MX366285B (en) Aggregating and presenting event information.
IN2014DN08833A (en)
IN2014DN08256A (en)
IN2014CN04868A (en)
GB2505804A8 (en) Multi-domain information sharing
EP2534604A4 (en) Executable identity based file access
MX2017003142A (en) Utilizing machine learning to identify non-technical loss.
MX356769B (en) Shared vehicle management.
GB2510729A (en) Managing data usage of a computing device
WO2014165180A3 (en) Workflow software structured around taxonomic themes of regulatory activity
CA2813429C (en) Configurable aircraft data acquisition and/or transmission system
MX2015008184A (en) Damper for suspension of heavy-duty vehicle.
WO2013186638A3 (en) Analyzing user interaction
WO2014033639A3 (en) Introspection of software program components and conditional generation of memory dump
WO2014184675A3 (en) Field programmable hierarchical cloud billing system
WO2014200575A3 (en) Gas turbine engine rapid response clearance control system with air seal segment interface
GB2512785A (en) Distributed function execution for hybrid systems
WO2014042474A3 (en) Method and system for executing application, and device and recording medium thereof
MX2016013775A (en) Access management system, communication system, recording medium and access management method.